From 78ab9f59afcdba92fc00fa1ea79091fdeee02db6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 18:55:43 -0500 Subject: [PATCH] Updated GPIO signal names to reflect book. --- fpga/src/fpgaTop.v | 12 ++++++------ src/uncore/gpio_apb.sv | 12 ++++++------ src/uncore/uncore.sv | 8 ++++---- src/wally/wallypipelinedsoc.sv | 8 ++++---- testbench/testbench-linux.sv | 8 ++++---- testbench/testbench.sv | 6 +++--- testbench/testbench_imperas.sv | 6 +++--- 7 files changed, 30 insertions(+), 30 deletions(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 6a26be74..990495f4 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -88,7 +88,7 @@ module fpgaTop - wire [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + wire [31:0] GPIOIN, GPIOOUT, GPIOEN; wire SDCCmdIn; wire SDCCmdOE; @@ -183,8 +183,8 @@ module fpgaTop - assign GPIOPinsIn = {28'b0, GPI}; - assign GPO = GPIOPinsOut[4:0]; + assign GPIOIN = {28'b0, GPI}; + assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; assign calib = c0_init_calib_complete; @@ -231,9 +231,9 @@ module fpgaTop .HMASTLOCK(HMASTLOCK), .HREADY(HREADY), // GPIO - .GPIOPinsIn(GPIOPinsIn), - .GPIOPinsOut(GPIOPinsOut), - .GPIOPinsEn(GPIOPinsEn), + .GPIOIN(GPIOIN), + .GPIOOUT(GPIOOUT), + .GPIOEN(GPIOEN), // UART .UARTSin(UARTSin), .UARTSout(UARTSout), diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 7a8ac3c1..869f1bbd 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -41,8 +41,8 @@ module gpio_apb ( output logic [`XLEN-1:0] PRDATA, output logic PREADY, input logic [31:0] iof0, iof1, - input logic [31:0] GPIOPinsIn, - output logic [31:0] GPIOPinsOut, GPIOPinsEn, + input logic [31:0] GPIOIN, + output logic [31:0] GPIOOUT, GPIOEN, output logic GPIOIntr ); @@ -138,8 +138,8 @@ module gpio_apb ( // chip i/o // connect OUT to IN for loopback testing - if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOPinsOut) | (~output_en & GPIOPinsIn)) & input_en; - else assign input0d = GPIOPinsIn & input_en; + if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en; + else assign input0d = GPIOIN & input_en; // synchroninzer for inputs flop #(32) sync1(PCLK,input0d,input1d); @@ -148,8 +148,8 @@ module gpio_apb ( assign input_val = input3d; assign iof_out = iof_sel & iof1 | ~iof_sel & iof0; // per-bit mux between iof1 and iof0 assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val - assign GPIOPinsOut = gpio_out ^ out_xor; // per-bit flip output polarity - assign GPIOPinsEn = output_en; + assign GPIOOUT = gpio_out ^ out_xor; // per-bit flip output polarity + assign GPIOEN = output_en; assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)}; endmodule diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 2aeb8104..4f00a3da 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -51,8 +51,8 @@ module uncore ( output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT output logic MExtInt, SExtInt, // External interrupts from PLIC output logic [63:0] MTIME_CLINT, // MTIME, from CLINT - input logic [31:0] GPIOPinsIn, // GPIO pin input value - output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable + input logic [31:0] GPIOIN, // GPIO pin input value + output logic [31:0] GPIOOUT, GPIOEN, // GPIO pin output value and enable input logic UARTSin, // UART serial input output logic UARTSout, // UART serial output output logic SDCCmdOut, // SD Card command output @@ -133,9 +133,9 @@ module uncore ( gpio_apb gpio( .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), - .iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr); + .iof0(), .iof1(), .GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIntr); end else begin : gpio - assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; + assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0; end if (`UART_SUPPORTED == 1) begin : uart uart_apb uart( diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index ea975208..0e363245 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -51,9 +51,9 @@ module wallypipelinedsoc ( output logic HREADY, // I/O Interface input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic [31:0] GPIOIN, // inputs from GPIO + output logic [31:0] GPIOOUT, // output values for GPIO + output logic [31:0] GPIOEN, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output input logic SDCCmdIn, // SDC Command input @@ -85,7 +85,7 @@ module wallypipelinedsoc ( uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, - .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, + .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .MTIME_CLINT, .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); end diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index 1705b36f..908660ff 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -252,8 +252,8 @@ module testbench; logic [3:0] HPROT; logic [1:0] HTRANS; logic HMASTLOCK; - logic [31:0] GPIOPinsIn; - logic [31:0] GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN; + logic [31:0] GPIOOUT, GPIOEN; logic UARTSin, UARTSout; // FPGA-specific Stuff @@ -264,7 +264,7 @@ module testbench; logic [3:0] SDCDatIn; // Hardwire UART, GPIO pins - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; // Wally @@ -272,7 +272,7 @@ module testbench; .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, - .TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b546f88b..bb70a636 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -150,7 +150,7 @@ logic [3:0] dummy; string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; integer outputFilePointer; - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; logic SDCCLK; @@ -169,7 +169,7 @@ logic [3:0] dummy; logic InReset; // instantiate device to be tested - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; if(`EXT_MEM_SUPPORTED) begin @@ -199,7 +199,7 @@ logic [3:0] dummy; wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); // Track names of instructions diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 6ac11bc2..f63c640d 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -73,7 +73,7 @@ module testbench; string testName; string memfilename, testDir, adrstr, elffilename; - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; logic SDCCLK; @@ -217,7 +217,7 @@ module testbench; // instantiate device to be tested - assign GPIOPinsIn = 0; + assign GPIOIN = 0; assign UARTSin = 1; if(`EXT_MEM_SUPPORTED) begin @@ -247,7 +247,7 @@ module testbench; wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); // Track names of instructions