From 75a6097467027163e325b28aaab87f8a3190e1ba Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Sat, 5 Jun 2021 12:06:33 -0400 Subject: [PATCH] fixed lint warnings for fpu and lzd --- wally-pipelined/src/fpu/fctrl.sv | 5 ++-- wally-pipelined/src/fpu/fpdiv.sv | 26 +++++++++---------- wally-pipelined/src/fpu/fpu.sv | 17 ++++++++---- wally-pipelined/src/fpu/fpuhazard.sv | 4 +-- wally-pipelined/src/fpu/fsm.sv | 4 +-- wally-pipelined/src/generic/lzd.sv | 26 +++++++++---------- wally-pipelined/src/hazard/hazard.sv | 4 +-- .../src/wally/wallypipelinedhart.sv | 2 +- .../testbench/testbench-imperas.sv | 6 ++--- 9 files changed, 50 insertions(+), 44 deletions(-) diff --git a/wally-pipelined/src/fpu/fctrl.sv b/wally-pipelined/src/fpu/fctrl.sv index 851f384b..94143b87 100755 --- a/wally-pipelined/src/fpu/fctrl.sv +++ b/wally-pipelined/src/fpu/fctrl.sv @@ -57,12 +57,13 @@ module fctrl ( always_comb begin //checks all but FMA/store/load IllegalFPUInstr2D = 0; + FDivStartD = 1'b0; if(OpD == 7'b1010011) begin casez(Funct7D) //compare 7'b10100?? : FResultSelD = 3'b001; //div/sqrt - 7'b0?011?? : FResultSelD = 3'b000; + 7'b0?011?? : begin FResultSelD = 3'b000; FDivStartD = 1'b1; end //add/sub 7'b0000??? : FResultSelD = 3'b100; //mult @@ -129,8 +130,6 @@ module fctrl ( //this value is used enough to be shorthand - //if op is div/sqrt - start div/sqrt - assign FDivStartD = ~|FResultSelD; // is FResultSelD == 000 //operation control for each fp operation //has to be expanded over standard to account for diff --git a/wally-pipelined/src/fpu/fpdiv.sv b/wally-pipelined/src/fpu/fpdiv.sv index 0d493359..96723ca7 100755 --- a/wally-pipelined/src/fpu/fpdiv.sv +++ b/wally-pipelined/src/fpu/fpdiv.sv @@ -23,8 +23,8 @@ // // `timescale 1ps/1ps -module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, - FDivStartE, reset, clk, DivBusyM); +module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, + FDivStartE, reset, clk, FDivBusyE); input [63:0] FInput1E; // 1st input operand (A) input [63:0] FInput2E; // 2nd input operand (B) @@ -38,11 +38,11 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp input reset; input clk; - output [63:0] FDivResultM; // Result of operation - output [4:0] FDivFlagsM; // IEEE exception flags - output DivDenormM; // DivDenormM on input or output - output FDivSqrtDoneM; - output DivBusyM; + output [63:0] FDivResultE; // Result of operation + output [4:0] FDivFlagsE; // IEEE exception flags + output DivDenormE; // DivDenormE on input or output + output FDivSqrtDoneE; + output FDivBusyE; supply1 vdd; supply0 vss; @@ -101,7 +101,7 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp convert_inputs_div divconv1 (Float1, Float2, FInput1E, FInput2E, DivOpType, FmtE); // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input FDivFlagsM. The "sel_inv" is used in + // "Denormalized" Input FDivFlagsE. The "sel_inv" is used in // the third pipeline stage to select the result. Also, op1_Norm // and op2_Norm are one if FInput1E and FInput2E are not zero or denormalized. // sub is one if the effective operation is subtaction. @@ -138,9 +138,9 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp load_regr, load_regs, FmtE, DivOpType, exp_odd); // FSM : control divider - fsm control (FDivSqrtDoneM, load_rega, load_regb, load_regc, load_regd, + fsm control (FDivSqrtDoneE, load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, - clk, reset, FDivStartE, DivOpType, DivBusyM); + clk, reset, FDivStartE, DivOpType, FDivBusyE); // Round the mantissa to a 52-bit value, with the leading one // removed. The rounding units also handles special cases and @@ -152,9 +152,9 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp q1, qm1, qp1, q0, qm0, qp0, regr_out); // Store the final result and the exception flags in registers. - flopenr #(64) rega (clk, reset, FDivSqrtDoneM, Result, FDivResultM); - flopenr #(1) regb (clk, reset, FDivSqrtDoneM, DenormIO, DivDenormM); - flopenr #(5) regc (clk, reset, FDivSqrtDoneM, FlagsIn, FDivFlagsM); + flopenr #(64) rega (clk, reset, FDivSqrtDoneE, Result, FDivResultE); + flopenr #(1) regb (clk, reset, FDivSqrtDoneE, DenormIO, DivDenormE); + flopenr #(5) regc (clk, reset, FDivSqrtDoneE, FlagsIn, FDivFlagsE); endmodule // fpadd diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index e7a73427..10632467 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -42,7 +42,7 @@ module fpu ( output logic FStallD, output logic FWriteIntE, FWriteIntM, FWriteIntW, output logic [`XLEN-1:0] FWriteDataM, - output logic FDivSqrtDoneM, + output logic FDivBusyE, output logic IllegalFPUInstrD, output logic [`XLEN-1:0] FPUResultW); @@ -73,11 +73,11 @@ module fpu ( logic [`XLEN-1:0] FLoadStoreResultM, FLoadStoreResultW; // Result for load, store, and move to int-reg instructions // div/sqrt signals - logic DivDenormM, DivDenormW; + logic DivDenormE, DivDenormM, DivDenormW; logic DivOvEn, DivUnEn; - logic DivBusyM; - logic [63:0] FDivResultM, FDivResultW; - logic [4:0] FDivFlagsM, FDivFlagsW; + logic [63:0] FDivResultE, FDivResultM, FDivResultW; + logic [4:0] FDivFlagsE, FDivFlagsM, FDivFlagsW; + logic FDivSqrtDoneE, FDivSqrtDoneM; // FMA signals logic [105:0] ProdManE, ProdManM; @@ -263,6 +263,13 @@ module fpu ( flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, YNaNE, YNaNM); flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, ZNaNE, ZNaNM); + //***************** + // fpdiv E/M pipe registers + //***************** + flopenrc #(64) EMRegDiv1(clk, reset, PipeClearEM, PipeEnableEM, FDivResultE, FDivResultM); + flopenrc #(5) EMRegDiv2(clk, reset, PipeClearEM, PipeEnableEM, FDivFlagsE, FDivFlagsM); + flopenrc #(1) EMRegDiv3(clk, reset, PipeClearEM, PipeEnableEM, DivDenormE, DivDenormM); + //***************** // fpadd E/M pipe registers //***************** diff --git a/wally-pipelined/src/fpu/fpuhazard.sv b/wally-pipelined/src/fpu/fpuhazard.sv index 4c1344dc..959ef476 100644 --- a/wally-pipelined/src/fpu/fpuhazard.sv +++ b/wally-pipelined/src/fpu/fpuhazard.sv @@ -29,7 +29,7 @@ module fpuhazard( input logic [4:0] Adr1, Adr2, Adr3, input logic FWriteEnE, FWriteEnM, FWriteEnW, input logic [4:0] RdE, RdM, RdW, - input logic DivBusyM, + input logic FDivBusyE, input logic RegWriteD, input logic [2:0] FResultSelD, FResultSelE, input logic IllegalFPUInstrD, @@ -46,7 +46,7 @@ module fpuhazard( FForwardInput1D = 2'b00; FForwardInput2D = 2'b00; FForwardInput3D = 1'b0; - FStallD = DivBusyM; + FStallD = FDivBusyE; if (~IllegalFPUInstrD) begin // if taking a value from int register if ((Adr1 == RdE) & (FWriteEnE | ((FResultSelE == 3'b110) & RegWriteD))) diff --git a/wally-pipelined/src/fpu/fsm.sv b/wally-pipelined/src/fpu/fsm.sv index b5a503a1..a03980db 100755 --- a/wally-pipelined/src/fpu/fsm.sv +++ b/wally-pipelined/src/fpu/fsm.sv @@ -48,7 +48,7 @@ module fsm (done, load_rega, load_regb, load_regc, S25=5'd25, S26=5'd26, S27=5'd27, S28=5'd28, S29=5'd29, S30=5'd30; - always @(posedge clk) + always @(negedge clk) begin if(reset==1'b1) CURRENT_STATE=S0; @@ -245,7 +245,7 @@ module fsm (done, load_rega, load_regb, load_regc, S10: // done begin done = 1'b1; - divBusy = 1'b1; + divBusy = 1'b0; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; diff --git a/wally-pipelined/src/generic/lzd.sv b/wally-pipelined/src/generic/lzd.sv index 98642c15..2637934f 100755 --- a/wally-pipelined/src/generic/lzd.sv +++ b/wally-pipelined/src/generic/lzd.sv @@ -44,7 +44,7 @@ module lzd2 (P, V, B); assign V = B[0] | B[1]; assign P = B[0] & ~B[1]; -endmodule // lz2 +endmodule // lzd2 module lzd_hier #(parameter WIDTH=8) (input logic [WIDTH-1:0] B, @@ -78,8 +78,8 @@ module lzd4 (ZP, ZV, B); output logic [1:0] ZP; output logic ZV; - lz2 l1(ZPa, ZVa, B[1:0]); - lz2 l2(ZPb, ZVb, B[3:2]); + lzd2 l1(ZPa, ZVa, B[1:0]); + lzd2 l2(ZPb, ZVb, B[3:2]); assign ZP[0:0] = ZVb ? ZPb : ZPa; assign ZP[1] = ~ZVb; @@ -99,8 +99,8 @@ module lzd8 (ZP, ZV, B); output logic [2:0] ZP; output logic ZV; - lz4 l1(ZPa, ZVa, B[3:0]); - lz4 l2(ZPb, ZVb, B[7:4]); + lzd4 l1(ZPa, ZVa, B[3:0]); + lzd4 l2(ZPb, ZVb, B[7:4]); assign ZP[1:0] = ZVb ? ZPb : ZPa; assign ZP[2] = ~ZVb; @@ -120,8 +120,8 @@ module lzd16 (ZP, ZV, B); output logic [3:0] ZP; output logic ZV; - lz8 l1(ZPa, ZVa, B[7:0]); - lz8 l2(ZPb, ZVb, B[15:8]); + lzd8 l1(ZPa, ZVa, B[7:0]); + lzd8 l2(ZPb, ZVb, B[15:8]); assign ZP[2:0] = ZVb ? ZPb : ZPa; assign ZP[3] = ~ZVb; @@ -141,8 +141,8 @@ module lzd32 (ZP, ZV, B); output logic [4:0] ZP; output logic ZV; - lz16 l1(ZPa, ZVa, B[15:0]); - lz16 l2(ZPb, ZVb, B[31:16]); + lzd16 l1(ZPa, ZVa, B[15:0]); + lzd16 l2(ZPb, ZVb, B[31:16]); assign ZP[3:0] = ZVb ? ZPb : ZPa; assign ZP[4] = ~ZVb; @@ -162,8 +162,8 @@ module lzd64 (ZP, ZV, B); output logic [5:0] ZP; output logic ZV; - lz32 l1(ZPa, ZVa, B[31:0]); - lz32 l2(ZPb, ZVb, B[63:32]); + lzd32 l1(ZPa, ZVa, B[31:0]); + lzd32 l2(ZPb, ZVb, B[63:32]); assign ZP[4:0] = ZVb ? ZPb : ZPa; assign ZP[5] = ~ZVb; @@ -183,8 +183,8 @@ module lzd128 (ZP, ZV, B); output logic [6:0] ZP; output logic ZV; - lz64 l1(ZPa, ZVa, B[64:0]); - lz64 l2(ZPb, ZVb, B[127:63]); + lzd64 l1(ZPa, ZVa, B[64:0]); + lzd64 l2(ZPb, ZVb, B[127:63]); assign ZP[5:0] = ZVb ? ZPb : ZPa; assign ZP[6] = ~ZVb; diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 72857fb3..47b9cba4 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -33,7 +33,7 @@ module hazard( input logic LoadStallD, MulDivStallD, CSRRdStallD, input logic DataStall, ICacheStallF, input logic FPUStallD, - input logic DivBusyE, + input logic DivBusyE,FDivBusyE, // Stall & flush outputs output logic StallF, StallD, StallE, StallM, StallW, output logic FlushF, FlushD, FlushE, FlushM, FlushW @@ -57,7 +57,7 @@ module hazard( assign StallFCause = CSRWritePendingDEM && ~(TrapM || RetM || BPPredWrongE); assign StallDCause = (LoadStallD || MulDivStallD || CSRRdStallD || FPUStallD) && ~(TrapM || RetM || BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous - assign StallECause = DivBusyE; + assign StallECause = DivBusyE | FDivBusyE; assign StallMCause = 0; assign StallWCause = DataStall || ICacheStallF; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index b82e6825..a7a2355a 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -100,7 +100,7 @@ module wallypipelinedhart ( logic FStallD; logic FWriteIntE, FWriteIntW, FWriteIntM; logic [31:0] FSROutW; - logic FDivSqrtDoneM; + logic FDivBusyE; logic IllegalFPUInstrD, IllegalFPUInstrE; logic [`XLEN-1:0] FPUResultW; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 781ff78e..e12a3bfe 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -122,6 +122,7 @@ string tests32f[] = '{ }; string tests64d[] = '{ + // "rv64d/I-FDIV-D-01", "2000", "rv64d/I-FNMADD-D-01", "2000", "rv64d/I-FNMSUB-D-01", "2000", "rv64d/I-FMSUB-D-01", "2000", @@ -142,13 +143,12 @@ string tests32f[] = '{ // "rv64d/I-FCVT-S-D-01", "2000", // "rv64d/I-FCVT-W-D-01", "2000", // "rv64d/I-FCVT-WU-D-01", "2000", - // "rv64d/I-FDIV-D-01", "2000", "rv64d/I-FSD-01", "2000", "rv64d/I-FLD-01", "2420", "rv64d/I-FMADD-D-01", "2000", "rv64d/I-FMUL-D-01", "2000", - // "rv64d/I-FMV-D-X-01", "2000", - // "rv64d/I-FMV-X-D-01", "2000", + "rv64d/I-FMV-D-X-01", "2000", + "rv64d/I-FMV-X-D-01", "2000", "rv64d/I-FSGNJ-D-01", "2000", "rv64d/I-FSGNJN-D-01", "2000", "rv64d/I-FSGNJX-D-01", "2000",