From 7531bf1fd6b3d40c6608b0e0be0b7acd281c105f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:57:30 -0800 Subject: [PATCH] zbb result select mux structural --- src/ieu/bmu/bmuctrl.sv | 40 ++++++++++++++++++++-------------------- src/ieu/bmu/zbb.sv | 23 ++--------------------- 2 files changed, 22 insertions(+), 41 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index a3ed483a..d57aecfd 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -116,48 +116,48 @@ module bmuctrl( 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_0_0; // add.uw 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // roriw else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // sign extend instruction else BMUControlsD = `BMUCTRLW'b000_10_000_1_0_1_0_0_0_0_0; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv32) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_10_111_1_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_10_111_1_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_10_111_1_0_1_1_0_0_0_0; // xnor + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv32) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // minu + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // minu default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1c2ae6bc..fc191874 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -61,27 +61,8 @@ module zbb #(parameter WIDTH=32) ( assign MaxResult = (lt) ? B : A; assign MinResult = (lt) ? A : B; - //can replace with structural mux by looking at bit 4 in rs2 field - always_comb begin - case (ZBBSelect) - 3'b111: ZBBResult = ALUResult; // rotates, andn, xnor, orn - 3'b000: ZBBResult = CntResult; // count - 3'b100: ZBBResult = ExtResult; // sign/zero extend - 3'b011: ZBBResult = ByteResult; // byte instructions - 3'b110: ZBBResult = MinResult; // min, minu - 3'b101: ZBBResult = MaxResult; // max, maxu - /*15'b0010100_101_00111: ZBBResult = OrcBResult; - 15'b0110100_101_11000: ZBBResult = Rev8Result; - 15'b0110101_101_11000: ZBBResult = Rev8Result; - 15'b0110000_001_00000: ZBBResult = czResult; - 15'b0110000_001_00010: ZBBResult = cpopResult; - 15'b0110000_001_00001: ZBBResult = czResult; - 15'b0000100_100_00000: ZBBResult = zexthResult; - 15'b0110000_001_00100: ZBBResult = sextbResult; - 15'b0110000_001_00101: ZBBResult = sexthResult;*/ - default: ZBBResult = {(WIDTH){1'b0}}; - endcase - end + // ZBB Result select mux + mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); endmodule \ No newline at end of file