diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 4d346e5a..1a1bec35 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -132,7 +132,8 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_ENABLED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
 `define BPRED_SIZE 10
 
diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 639dbcd5..497d5987 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 0
+`define INSTR_CLASS_PRED 1
 
 module bpred (
    input logic              clk, reset,
diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv
index 6cfb5689..c41282d5 100644
--- a/pipelined/src/ifu/brpred/speculativegshare.sv
+++ b/pipelined/src/ifu/brpred/speculativegshare.sv
@@ -51,16 +51,15 @@ module speculativegshare
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
-  logic [k-1:0]            GHRF, OldGHRF;
+  logic [k-1:0]            GHRF;
   logic 				   GHRExtraF;
-  logic [k-1:0] 		   GHRD, OldGHRE, GHRE, GHRM, GHRW;
+  logic [k-1:0] 		   GHRD, GHRE, GHRM, GHRW;
   logic [k-1:0] 		   GHRNextF;
   logic [k-1:0] 		   GHRNextD;
   logic [k-1:0] 		   GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
   logic [k-1:0]            IndexD, IndexE;
   
-  logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
   
@@ -126,7 +125,7 @@ module speculativegshare
   // with instruction class prediction
   assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
 					WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
-  					WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}:       // shift left
+  					WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}:       // shift left
 					GHRF[k-1:0];
 
   flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
@@ -144,6 +143,4 @@ module speculativegshare
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
 endmodule
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index fd83c79b..db36d937 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -32,8 +32,8 @@
 `include "wally-config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 1
-`define BPRED_LOGGER 1
+`define PrintHPMCounters 0
+`define BPRED_LOGGER 0
 
 module testbench;
   parameter DEBUG=0;
@@ -408,7 +408,7 @@ logic [3:0] dummy;
     end // always @ (negedge clk)
 
 
-  if(`PrintHPMCounters) begin
+  if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin
     integer HPMCindex;
     string  HPMCnames[] = '{"Mcycle",
                             "------",