diff --git a/testbench/tests.vh b/testbench/tests.vh
index 311a0741..f894d58f 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -1445,42 +1445,40 @@ string arch64b[] = '{
 
 string arch32b[] = '{
     `RISCVARCHTEST,
+    "rv32i_m/B/src/clmul-01.S",
+    "rv32i_m/B/src/clmulh-01.S",
+    "rv32i_m/B/src/clmulr-01.S",
+    "rv32i_m/B/src/bclr-01.S",
+    "rv32i_m/B/src/bclri-01.S",
+    "rv32i_m/B/src/bext-01.S",
+    "rv32i_m/B/src/bexti-01.S",
+    "rv32i_m/B/src/binv-01.S",
+    "rv32i_m/B/src/binvi-01.S",
+    "rv32i_m/B/src/bset-01.S",
+    "rv32i_m/B/src/bseti-01.S",
     "rv32i_m/B/src/max-01.S",
     "rv32i_m/B/src/maxu-01.S",
     "rv32i_m/B/src/min-01.S",
     "rv32i_m/B/src/minu-01.S",
-    "rv32i_m/B/src/orcb_64-01.S",
-    "rv32i_m/B/src/rev8-01.S",
+    "rv32i_m/B/src/orcb_32-01.S",
+    "rv32i_m/B/src/rev8_32-01.S",
     "rv32i_m/B/src/andn-01.S",
     "rv32i_m/B/src/orn-01.S",
     "rv32i_m/B/src/xnor-01.S",
-    "rv32i_m/B/src/zext.h-01.S",
+    "rv32i_m/B/src/zext.h_32-01.S",
     "rv32i_m/B/src/sext.b-01.S",
     "rv32i_m/B/src/sext.h-01.S",
     "rv32i_m/B/src/clz-01.S",
-    "rv32i_m/B/src/clzw-01.S",
     "rv32i_m/B/src/cpop-01.S",
-    "rv32i_m/B/src/cpopw-01.S",
     "rv32i_m/B/src/ctz-01.S",
-    "rv32i_m/B/src/ctzw-01.S",
-    "rv32i_m/B/src/rolw-01.S",
     "rv32i_m/B/src/ror-01.S",
     "rv32i_m/B/src/rori-01.S",
-    "rv32i_m/B/src/roriw-01.S",
-    "rv32i_m/B/src/rorw-01.S",
     "rv32i_m/B/src/rol-01.S",
-    "rv32i_m/B/src/slli.uw-01.S",
-    "rv32i_m/B/src/add.uw-01.S",
     "rv32i_m/B/src/sh1add-01.S",
     "rv32i_m/B/src/sh2add-01.S",
     "rv32i_m/B/src/sh3add-01.S",
-    "rv32i_m/B/src/sh1add.uw-01.S",
-    "rv32i_m/B/src/sh2add.uw-01.S",
-    "rv32i_m/B/src/sh3add.uw-01.S",
     "rv32i_m/I/src/add-01.S",
     "rv32i_m/I/src/addi-01.S",
-    "rv32i_m/I/src/addiw-01.S",
-    "rv32i_m/I/src/addw-01.S",
     "rv32i_m/I/src/and-01.S",
     "rv32i_m/I/src/andi-01.S",
     "rv32i_m/I/src/auipc-01.S",
@@ -1495,49 +1493,29 @@ string arch32b[] = '{
     "rv32i_m/I/src/jalr-01.S",
     "rv32i_m/I/src/lb-align-01.S",
     "rv32i_m/I/src/lbu-align-01.S",
-    "rv32i_m/I/src/ld-align-01.S",
     "rv32i_m/I/src/lh-align-01.S",
     "rv32i_m/I/src/lhu-align-01.S",
     "rv32i_m/I/src/lui-01.S",
     "rv32i_m/I/src/lw-align-01.S",
-    "rv32i_m/I/src/lwu-align-01.S",
     "rv32i_m/I/src/or-01.S",
     "rv32i_m/I/src/ori-01.S",
     "rv32i_m/I/src/sb-align-01.S",
-    "rv32i_m/I/src/sd-align-01.S",
     "rv32i_m/I/src/sh-align-01.S",
     "rv32i_m/I/src/sll-01.S",
     "rv32i_m/I/src/slli-01.S",
-    "rv32i_m/I/src/slliw-01.S",
-    "rv32i_m/I/src/sllw-01.S",
     "rv32i_m/I/src/slt-01.S",
     "rv32i_m/I/src/slti-01.S",
     "rv32i_m/I/src/sltiu-01.S",
     "rv32i_m/I/src/sltu-01.S",
     "rv32i_m/I/src/sra-01.S",
     "rv32i_m/I/src/srai-01.S",
-    "rv32i_m/I/src/sraiw-01.S",
-    "rv32i_m/I/src/sraw-01.S",
     "rv32i_m/I/src/srl-01.S",
     "rv32i_m/I/src/srli-01.S",
-    "rv32i_m/I/src/srliw-01.S",
-    "rv32i_m/I/src/srlw-01.S",
     "rv32i_m/I/src/sub-01.S",
-    "rv32i_m/I/src/subw-01.S",
     "rv32i_m/I/src/sw-align-01.S",
     "rv32i_m/I/src/xor-01.S",
-    "rv32i_m/I/src/xori-01.S",
-    "rv32i_m/B/src/clmul-01.S",
-    "rv32i_m/B/src/clmulh-01.S",
-    "rv32i_m/B/src/clmulr-01.S",
-    "rv32i_m/B/src/bclr-01.S",
-    "rv32i_m/B/src/bclri-01.S",
-    "rv32i_m/B/src/bext-01.S",
-    "rv32i_m/B/src/bexti-01.S",
-    "rv32i_m/B/src/binv-01.S",
-    "rv32i_m/B/src/binvi-01.S",
-    "rv32i_m/B/src/bset-01.S",
-    "rv32i_m/B/src/bseti-01.S"
+    "rv32i_m/I/src/xori-01.S"
+   
     /*"rv64i_m/B/src/add.uw-01.S",
     "rv64i_m/B/src/bclr-01.S",
     "rv64i_m/B/src/bclri-01.S",