diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv
index 5208032a..ee4b261d 100644
--- a/wally-pipelined/src/mmu/pmpchecker.sv
+++ b/wally-pipelined/src/mmu/pmpchecker.sv
@@ -70,7 +70,7 @@ module pmpchecker (
               PMPCfg[j+3], PMPCfg[j+2], PMPCfg[j+1], PMPCfg[j]} = PMPCFG_ARRAY_REGW[j/8];
   endgenerate */
 
-  pmpadrdec pmpadrdec[`PMP_ENTRIES-1:0](
+  pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
     .PhysicalAddress, 
     .PMPCfg(PMPCFG_ARRAY_REGW),
     .PMPAdr(PMPADDR_ARRAY_REGW),
diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv
index 1cf63906..bd365280 100644
--- a/wally-pipelined/src/mmu/tlb.sv
+++ b/wally-pipelined/src/mmu/tlb.sv
@@ -95,7 +95,7 @@ module tlb #(parameter ENTRY_BITS = 3,
 
   // Index (currently random) to write the next TLB entry
   logic [ENTRY_BITS-1:0] WriteIndex;
-  logic [(2**ENTRY_BITS)-1:0] WriteLines; // used as the one-hot encoding of WriteIndex
+  logic [(2**ENTRY_BITS)-1:0] WriteLines, WriteEnables; // used as the one-hot encoding of WriteIndex
 
   // Sections of the virtual and physical addresses
   logic [`VPN_BITS-1:0] VirtualPageNumber;
@@ -121,6 +121,7 @@ module tlb #(parameter ENTRY_BITS = 3,
 
   // Decode the integer encoded WriteIndex into the one-hot encoded WriteLines
   decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
+  assign WriteEnables = WriteLines & {(2**ENTRY_BITS){TLBWrite}};
 
   // The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
   // this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower,
diff --git a/wally-pipelined/src/mmu/tlbcam.sv b/wally-pipelined/src/mmu/tlbcam.sv
index bd64afea..e45b124a 100644
--- a/wally-pipelined/src/mmu/tlbcam.sv
+++ b/wally-pipelined/src/mmu/tlbcam.sv
@@ -35,9 +35,9 @@ module tlbcam #(parameter ENTRY_BITS = 3,
   input logic [KEY_BITS-1:0]      VirtualPageNumber,
   input logic [1:0]               PageTypeWriteVal,
 //  input logic [`SVMODE_BITS-1:0]  SvMode, // *** may not need to be used.
-  input logic                     TLBWrite,
+//  input logic                     TLBWrite,
   input logic                     TLBFlush,
-  input logic [2**ENTRY_BITS-1:0] WriteLines,
+  input logic [2**ENTRY_BITS-1:0] WriteEnables,
 
   output logic [ENTRY_BITS-1:0]   VPNIndex,
   output logic [1:0]              HitPageType,
@@ -55,16 +55,24 @@ module tlbcam #(parameter ENTRY_BITS = 3,
   // original virtual page number from when the address was written, regardless
   // of page type. However, matches are determined based on a subset of the
   // page number segments.
+
+  camline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0](
+    .CAMLineWrite(WriteEnables),
+        .PageType(PageTypeList),
+        .Match(Matches),
+        .*);
+/*
   generate
     genvar i;
     for (i = 0; i < NENTRIES; i++) begin
       camline #(KEY_BITS, SEGMENT_BITS) camline(
-        .CAMLineWrite(WriteLines[i] && TLBWrite),
+        .CAMLineWrite(WriteEnables[i]),
         .PageType(PageTypeList[i]),
         .Match(Matches[i]),
         .*);
     end
   endgenerate
+  */
 
   // In case there are multiple matches in the CAM, select only one
   // *** it might be guaranteed that the CAM will never have multiple matches.
diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv
index 2012ed82..f13666bc 100644
--- a/wally-pipelined/src/mmu/tlbram.sv
+++ b/wally-pipelined/src/mmu/tlbram.sv
@@ -32,8 +32,8 @@ module tlbram #(parameter ENTRY_BITS = 3) (
   input logic [ENTRY_BITS-1:0]      VPNIndex,  // Index to read from
 //  input logic [ENTRY_BITS-1:0]      WriteIndex, // *** unused?
   input logic [`XLEN-1:0]           PTEWriteVal,
-  input logic                       TLBWrite,
-  input logic [2**ENTRY_BITS-1:0]   WriteLines,
+//  input logic                       TLBWrite,
+  input logic [2**ENTRY_BITS-1:0]   WriteEnables,
 
   output logic [`PPN_BITS-1:0]      PhysicalPageNumber,
   output logic [7:0]                PTEAccessBits
@@ -45,13 +45,16 @@ module tlbram #(parameter ENTRY_BITS = 3) (
   logic [`XLEN-1:0] PageTableEntry;
 
   // Generate a flop for every entry in the RAM
+  flopenr #(`XLEN) pteflops[NENTRIES-1:0](clk, reset, WriteEnables, PTEWriteVal, ram);
+/*
   generate
     genvar i;
     for (i = 0; i < NENTRIES; i++) begin:  tlb_ram_flops
-      flopenr #(`XLEN) pteflop(clk, reset, WriteLines[i] & TLBWrite,
+      flopenr #(`XLEN) pteflop(clk, reset, WriteEnables[i],
         PTEWriteVal, ram[i]);
     end
   endgenerate
+*/
 
   assign PageTableEntry = ram[VPNIndex];
   assign PTEAccessBits = PageTableEntry[7:0];