From 72e83db9fe2f6d4f20ffb46d048e1a5cce81ab3e Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 15 Feb 2022 19:59:29 +0000 Subject: [PATCH] removed csrn and all of its outputs because depricated --- pipelined/src/privileged/csr.sv | 23 +++--- pipelined/src/privileged/csrn.sv | 103 ------------------------- pipelined/src/privileged/csrsr.sv | 20 +---- pipelined/src/privileged/privileged.sv | 6 +- pipelined/src/privileged/trap.sv | 9 +-- 5 files changed, 19 insertions(+), 142 deletions(-) delete mode 100644 pipelined/src/privileged/csrn.sv diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 2608062c..cac7aa67 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -59,7 +59,7 @@ module csr #(parameter input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, - output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, + output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, @@ -76,12 +76,12 @@ module csr #(parameter ); localparam NOP = 32'h13; - logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM, CSRReadValM; + logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM, CSRReadValM; logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM; -(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW; +(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW; logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; - logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM; + logic WriteMSTATUSM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; logic STATUS_TVM; logic WriteFRMM, WriteFFLAGSM; @@ -90,7 +90,7 @@ module csr #(parameter logic [11:0] CSRAdrM; //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported - logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM; + logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; logic InstrValidNotFlushedM; @@ -126,10 +126,10 @@ module csr #(parameter .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM); csrsr csrsr(.clk, .reset, .StallW, - .WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM, + .WriteMSTATUSM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, - .MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW, + .MSTATUS_REGW, .SSTATUS_REGW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM); csrc counters(.clk, .reset, @@ -156,24 +156,19 @@ module csr #(parameter .SCOUNTEREN_REGW, .SATP_REGW, .SIP_REGW, .SIE_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); - csrn csrn(.clk, .reset, .InstrValidNotFlushedM, .StallW, - .CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM, - .NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW, - .CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW, - .UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM); csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM, .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, .IllegalCSRUAccessM); // merge CSR Reads - assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; + assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW); // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) | (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE); assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & - IllegalCSRSAccessM & IllegalCSRUAccessM & IllegalCSRNAccessM | + IllegalCSRSAccessM & IllegalCSRUAccessM | InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM; endmodule diff --git a/pipelined/src/privileged/csrn.sv b/pipelined/src/privileged/csrn.sv deleted file mode 100644 index d524313e..00000000 --- a/pipelined/src/privileged/csrn.sv +++ /dev/null @@ -1,103 +0,0 @@ -/////////////////////////////////////////// -// csrn.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// dottolia@hmc.edu 3 May 2021 - fix bug with utvec getting wrong value -// -// Purpose: User-Mode Control and Status Registers for User Mode Exceptions -// See RISC-V Privileged Mode Specification 20190608 Table 2.2 -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module csrn #(parameter - USTATUS =12'h000, - UIE = 12'h004, - UTVEC = 12'h005, - USCRATCH = 12'h040, - UEPC = 12'h041, - UCAUSE = 12'h042, - UTVAL = 12'h043, - UIP = 12'h044) ( - input logic clk, reset, - input logic InstrValidNotFlushedM, StallW, - input logic CSRNWriteM, UTrapM, - input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, - input logic [`XLEN-1:0] CSRWriteValM, - output logic [`XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW, - input logic [11:0] UIP_REGW, UIE_REGW, - output logic WriteUSTATUSM, - output logic IllegalCSRNAccessM - ); - - // User mode CSRs below only needed when user mode traps are supported - if (`N_SUPPORTED) begin:nmode // depricated; consider removing*** - logic WriteUTVECM; - logic WriteUSCRATCHM, WriteUEPCM; - logic WriteUCAUSEM, WriteUTVALM; - logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW; - logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW; - - // Write enables - assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & InstrValidNotFlushedM; - assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & InstrValidNotFlushedM; - assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & InstrValidNotFlushedM; - assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & InstrValidNotFlushedM; - assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & InstrValidNotFlushedM; - - // CSRs - flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW); - flopenr #(`XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW); - flopenr #(`XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW); - flopenr #(`XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW); - flopenr #(`XLEN) UTVALreg(clk, reset, WriteUTVALM, NextMtvalM, UTVAL_REGW); - - // CSR Reads - always_comb begin - IllegalCSRNAccessM = 0; - case (CSRAdrM) - USTATUS: CSRNReadValM = USTATUS_REGW; - UTVEC: CSRNReadValM = UTVEC_REGW; - UIP: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIP_REGW}; - UIE: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIE_REGW}; - USCRATCH: CSRNReadValM = USCRATCH_REGW; - UEPC: CSRNReadValM = UEPC_REGW; - UCAUSE: CSRNReadValM = UCAUSE_REGW; - UTVAL: CSRNReadValM = UTVAL_REGW; - default: begin - CSRNReadValM = 0; - IllegalCSRNAccessM = 1; - end - endcase - end - end else begin // if not supported - assign WriteUSTATUSM = 0; - assign CSRNReadValM = 0; - assign UEPC_REGW = 0; - assign UTVEC_REGW = 0; - assign IllegalCSRNAccessM = 1; - end - endmodule diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index d4db6ba1..e1f653b4 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -33,13 +33,13 @@ module csrsr ( input logic clk, reset, StallW, - input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, + input logic WriteMSTATUSM, WriteSSTATUSM, input logic TrapM, FRegWriteM, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic mretM, sretM, input logic WriteFRMM, WriteFFLAGSM, input logic [`XLEN-1:0] CSRWriteValM, - output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW, + output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, STATUS_TW, output logic STATUS_MIE, STATUS_SIE, @@ -66,11 +66,6 @@ module csrsr ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE, 1'b0*/ 2'b0, STATUS_SPIE, STATUS_UPIE, /*STATUS_MIE, 1'b0*/ 2'b0, STATUS_SIE, STATUS_UIE}; - assign USTATUS_REGW = {/*STATUS_SD, */ 59'b0, /*STATUS_SXL, STATUS_UXL, 9'b0, */ - /*STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, , 1'b0,*/ - /* STATUS_XS, STATUS_FS, /*STATUS_MPP, 8'b0, */ - /*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE, - /*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE}; end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -81,11 +76,6 @@ module csrsr ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE, 1'b0*/ 2'b0, STATUS_SPIE, STATUS_UPIE, /*STATUS_MIE, 1'b0*/ 2'b0, STATUS_SIE, STATUS_UIE}; - assign USTATUS_REGW = {/*STATUS_SD, */ 27'b0, /*STATUS_SXL, STATUS_UXL, 9'b0, */ - /*STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, , 1'b0,*/ - /*STATUS_XS, STATUS_FS, STATUS_MPP, 8'b0, */ - /*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE, - /*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE}; end // harwired STATUS bits @@ -181,10 +171,6 @@ module csrsr ( STATUS_UPIE <= #1 `U_SUPPORTED & CSRWriteValM[4]; STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1]; STATUS_UIE <= #1 `U_SUPPORTED & CSRWriteValM[0]; - end else if (WriteUSTATUSM) begin // write a subset of the STATUS bits - STATUS_FS_INT <= #1 CSRWriteValM[14:13]; - STATUS_UPIE <= #1 `U_SUPPORTED & CSRWriteValM[4]; - STATUS_UIE <= #1 `U_SUPPORTED & CSRWriteValM[0]; - end + end end endmodule diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 8bb4c05f..8493a15b 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -85,7 +85,7 @@ module privileged ( logic [1:0] NextPrivilegeModeM; logic [`XLEN-1:0] CauseM, NextFaultMtvalM; - logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW; + logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW; logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; @@ -158,7 +158,7 @@ module privileged ( .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .NextFaultMtvalM, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, - .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW, + .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEDELEG_REGW, .MIDELEG_REGW, .SATP_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, @@ -209,7 +209,7 @@ module privileged ( .LoadPageFaultM, .StoreAmoPageFaultM, .mretM, .sretM, .PrivilegeModeW, .NextPrivilegeModeM, - .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW, + .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .STATUS_MIE, .STATUS_SIE, .PCM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index a5273225..15c1e9e6 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -40,7 +40,7 @@ module trap ( (* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, (* mark_debug = "true" *) input logic mretM, sretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, - (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, + (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, input logic STATUS_MIE, STATUS_SIE, input logic [`XLEN-1:0] PCM, @@ -87,11 +87,10 @@ module trap ( assign RetM = mretM | sretM; always_comb - if (NextPrivilegeModeM == `U_MODE) PrivilegedTrapVector = UTVEC_REGW; - else if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; - else PrivilegedTrapVector = MTVEC_REGW; + if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; + else PrivilegedTrapVector = MTVEC_REGW; - // Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01) + // Handle vectored traps (when mtvec/stvec csr value has bits [1:0] == 01) // For vectored traps, set program counter to _tvec value + 4 times the cause code // // POSSIBLE OPTIMIZATION: