From 72bc64ef28448b2056a31ef662be24aa308bb43c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 5 Feb 2022 04:16:18 +0000 Subject: [PATCH] Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. --- pipelined/config/rv32e/wally-config.vh | 8 ++++---- pipelined/regression/sim-wally | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/testbench/testbench-tim.sv | 1 + pipelined/testbench/testbench.sv | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index bbeccbe8..b550407d 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -48,8 +48,8 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_BUS -`define IMEM `MEM_BUS +`define DMEM `MEM_TIM +`define IMEM `MEM_TIM `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 0 @@ -81,10 +81,10 @@ // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h000000FF +`define BOOTROM_RANGE 34'h00000FFF `define RAM_SUPPORTED 1'b1 `define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h000003FF +`define RAM_RANGE 34'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index 3eb310ca..2f88d9aa 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv32ic arch32i" +vsim -do "do wally-pipelined.do rv32e wally32e" diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index ea1c504a..54d5eade 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -170,7 +170,7 @@ module ifu ( assign InstrRawF = AllInstrRawF[31:0]; - if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN + if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .FinalWriteDataM(), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), diff --git a/pipelined/testbench/testbench-tim.sv b/pipelined/testbench/testbench-tim.sv index 63c96178..1a13e2b5 100644 --- a/pipelined/testbench/testbench-tim.sv +++ b/pipelined/testbench/testbench-tim.sv @@ -122,6 +122,7 @@ logic [3:0] dummy; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; "wally32i": tests = wally32i; // *** redo + "wally32e": tests = wally32e; "wally32priv": tests = wally32priv; // *** redo "imperas32periph": tests = imperas32periph; endcase diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 0fb39358..a41fd3de 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -123,7 +123,7 @@ logic [3:0] dummy; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; "wally32i": tests = wally32i; // *** redo - "wally32e": tests = wally32e; // *** redo + "wally32e": tests = wally32e; "wally32priv": tests = wally32priv; // *** redo "imperas32periph": tests = imperas32periph; endcase