From 721d0b5bcf59a48047512fc85091a3bbd8f11f55 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 10:25:40 -0800
Subject: [PATCH] Simplified shifter right input

---
 wally-pipelined/src/ieu/alu.sv     |  6 ++---
 wally-pipelined/src/ieu/shifter.sv | 42 +++++++++++++++---------------
 2 files changed, 23 insertions(+), 25 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index 0558cbe1..827aeb8a 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -33,7 +33,6 @@ module alu #(parameter WIDTH=32) (
   output logic [WIDTH-1:0] Sum);
 
   logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
-  logic        Right;
   logic        Carry, Neg;
   logic        LT, LTU;
   logic        Overflow;
@@ -51,9 +50,8 @@ module alu #(parameter WIDTH=32) (
   assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // Shifts
-  assign Right = Funct3[2]; // sra or srl
-  shifter sh(A, B[`LOG_XLEN-1:0], Right, SubArith, W64, Shift);
-  
+  shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
+
   // condition code flags based on add/subtract output
   // Overflow occurs when the numbers being added have the same sign 
   // and the result has the opposite sign
diff --git a/wally-pipelined/src/ieu/shifter.sv b/wally-pipelined/src/ieu/shifter.sv
index fc170e75..232f7241 100644
--- a/wally-pipelined/src/ieu/shifter.sv
+++ b/wally-pipelined/src/ieu/shifter.sv
@@ -26,10 +26,10 @@
 `include "wally-config.vh"
 
 module shifter (
-  input  logic [`XLEN-1:0] a,
-  input  logic [`LOG_XLEN-1:0]       amt,
-  input  logic             right, arith, w64,
-  output logic [`XLEN-1:0] y);
+  input  logic [`XLEN-1:0]     A,
+  input  logic [`LOG_XLEN-1:0] Amt,
+  input  logic                 Right, Arith, W64,
+  output logic [`XLEN-1:0]     Y);
 
   logic [2*`XLEN-2:0]      z, zshift;
   logic [`LOG_XLEN-1:0]    amttrunc, offset;
@@ -42,34 +42,34 @@ module shifter (
   generate
     if (`XLEN==32) begin:shifter // RV32
       always_comb  // funnel mux
-        if (right) 
-          if (arith) z = {{31{a[31]}}, a};
-          else       z = {31'b0, a};
-        else         z = {a, 31'b0};
-      assign amttrunc = amt; // shift amount
+        if (Right) 
+          if (Arith) z = {{31{A[31]}}, A};
+          else       z = {31'b0, A};
+        else         z = {A, 31'b0};
+      assign amttrunc = Amt; // shift amount
     end else begin:shifter  // RV64
       always_comb  // funnel mux
-        if (w64) begin // 32-bit shifts
-          if (right)
-            if (arith) z = {64'b0, {31{a[31]}}, a[31:0]};
-            else       z = {95'b0, a[31:0]};
-          else         z = {32'b0, a[31:0], 63'b0};
+        if (W64) begin // 32-bit shifts
+          if (Right)
+            if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]};
+            else       z = {95'b0, A[31:0]};
+          else         z = {32'b0, A[31:0], 63'b0};
         end else begin
-          if (right)
-            if (arith) z = {{63{a[63]}}, a};
-            else       z = {63'b0, a};
-          else         z = {a, 63'b0};         
+          if (Right)
+            if (Arith) z = {{63{A[63]}}, A};
+            else       z = {63'b0, A};
+          else         z = {A, 63'b0};         
         end
-      assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt; // 32 or 64-bit shift
+      assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
     end
   endgenerate
 
   // opposite offset for right shfits
-  assign offset = right ? amttrunc : ~amttrunc;
+  assign offset = Right ? amttrunc : ~amttrunc;
   
   // funnel operation
   assign zshift = z >> offset;
-  assign y = zshift[`XLEN-1:0];    
+  assign Y = zshift[`XLEN-1:0];    
 endmodule