From 7151befd04ea9b013949d8f40fe542388b869866 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 22 Aug 2022 13:29:54 -0700
Subject: [PATCH] Removed FStore2 and simplified HPTW

---
 pipelined/src/mmu/hptw.sv                 | 12 ++++++------
 pipelined/src/wally/wallypipelinedcore.sv |  6 ++----
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv
index f96d69f0..8967b49d 100644
--- a/pipelined/src/mmu/hptw.sv
+++ b/pipelined/src/mmu/hptw.sv
@@ -48,7 +48,7 @@ module hptw
    output logic [1:0]          PageType, // page type to TLBs
    (* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic [`PA_BITS-1:0] HPTWAdr,
-   output logic [1:0]          HPTWRW, // HPTW requesting to read memory
+   output logic [1:0]          HPTWRW, // HPTW requesting to write or read memory
    output logic [2:0]          HPTWSize // 32 or 64 bit access.
 );
 
@@ -114,13 +114,15 @@ module hptw
     logic [`PA_BITS-1:0]      HPTWWriteAdr;  
     logic                     SetDirty;
     logic                     Dirty, Accessed;
+	logic [`XLEN-1:0]		  AccessedPTE;
 
-    assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE; 
+	assign AccessedPTE = {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
+	mux2 #(`XLEN) NextPTEMux(HPTWReadPTE, AccessedPTE, UpdatePTE, NextPTE);
     flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
+	
     assign SaveHPTWAdr = WalkerState == L0_ADR;
     assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0];
     mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); 
-    
 
     assign {Dirty, Accessed} = PTE[7:6];
     assign WriteAccess = MemRWM[0] | (|AtomicM);
@@ -255,9 +257,7 @@ module hptw
            else                                  NextWalkerState = LEAF;
     LEAF: if (DAPageFault) NextWalkerState = UPDATE_PTE;
           else NextWalkerState = IDLE;
-      // *** TODO update PTE with dirty/access.  write to TLB and update memory.
-      // probably want to write the PTE in UPDATE_PTE then go to leaf and update TLB.
-    UPDATE_PTE: if(`HPTW_WRITES_SUPPORTED & DCacheStallM) NextWalkerState = UPDATE_PTE;
+     UPDATE_PTE: if(`HPTW_WRITES_SUPPORTED & DCacheStallM) NextWalkerState = UPDATE_PTE;
                 else NextWalkerState = LEAF;
 	default: begin
 		NextWalkerState = IDLE; // should never be reached
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 200789c4..78fdb303 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -93,7 +93,6 @@ module wallypipelinedcore (
   logic             FStallD;
   logic             FWriteIntE;
   logic [`XLEN-1:0]         FWriteDataE;
-  logic                     FStore2;
   logic [`FLEN-1:0]         FWriteDataM;
   logic [`XLEN-1:0]         FIntResM;  
   logic [`XLEN-1:0]         FCvtIntResW;  
@@ -258,7 +257,7 @@ module wallypipelinedcore (
   .CommittedM, .DCacheMiss, .DCacheAccess,
   .SquashSCW,            
   .FpLoadStoreM,
-  .FWriteDataM, .FStore2,
+  .FWriteDataM, 
   //.DataMisalignedM(DataMisalignedM),
   .IEUAdrE, .IEUAdrM, .WriteDataE,
   .ReadDataW, .FlushDCacheM,
@@ -397,8 +396,7 @@ module wallypipelinedcore (
          .STATUS_FS, // is floating-point enabled?
          .FRegWriteM, // FP register write enable
          .FpLoadStoreM,
-         .FStore2,
-         .FStallD, // Stall the decode stage
+        .FStallD, // Stall the decode stage
          .FWriteIntE, // integer register write enable
          .FWriteDataE, // Data to be written to memory
          .FWriteDataM, // Data to be written to memory