diff --git a/wally-pipelined/config/busybear/wally-constants.vh b/wally-pipelined/config/busybear/wally-constants.vh new file mode 100644 index 00000000..55fb4e94 --- /dev/null +++ b/wally-pipelined/config/busybear/wally-constants.vh @@ -0,0 +1,31 @@ +////////////////////////////////////////// +// wally-constants.vh +// +// Written: tfleming@hmc.edu 4 March 2021 +// Modified: +// +// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture. +// These macros should not be changed, except in the event of an +// update to the architecture or particularly special circumstances. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Virtual Memory Constants (sv39) +`define VPN_BITS 27 +`define PPN_BITS 44 +`define PA_BITS 56 diff --git a/wally-pipelined/config/coremark/wally-constants.vh b/wally-pipelined/config/coremark/wally-constants.vh new file mode 100644 index 00000000..55fb4e94 --- /dev/null +++ b/wally-pipelined/config/coremark/wally-constants.vh @@ -0,0 +1,31 @@ +////////////////////////////////////////// +// wally-constants.vh +// +// Written: tfleming@hmc.edu 4 March 2021 +// Modified: +// +// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture. +// These macros should not be changed, except in the event of an +// update to the architecture or particularly special circumstances. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Virtual Memory Constants (sv39) +`define VPN_BITS 27 +`define PPN_BITS 44 +`define PA_BITS 56 diff --git a/wally-pipelined/config/rv32ic/wally-constants.vh b/wally-pipelined/config/rv32ic/wally-constants.vh new file mode 100644 index 00000000..ffa26727 --- /dev/null +++ b/wally-pipelined/config/rv32ic/wally-constants.vh @@ -0,0 +1,31 @@ +////////////////////////////////////////// +// wally-constants.vh +// +// Written: tfleming@hmc.edu 4 March 2021 +// Modified: +// +// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture. +// These macros should not be changed, except in the event of an +// update to the architecture or particularly special circumstances. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Virtual Memory Constants (sv32) +`define VPN_BITS 20 +`define PPN_BITS 22 +`define PA_BITS 34 diff --git a/wally-pipelined/config/rv64ic/wally-constants.vh b/wally-pipelined/config/rv64ic/wally-constants.vh new file mode 100644 index 00000000..55fb4e94 --- /dev/null +++ b/wally-pipelined/config/rv64ic/wally-constants.vh @@ -0,0 +1,31 @@ +////////////////////////////////////////// +// wally-constants.vh +// +// Written: tfleming@hmc.edu 4 March 2021 +// Modified: +// +// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture. +// These macros should not be changed, except in the event of an +// update to the architecture or particularly special circumstances. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Virtual Memory Constants (sv39) +`define VPN_BITS 27 +`define PPN_BITS 44 +`define PA_BITS 56 diff --git a/wally-pipelined/config/rv64icfd/wally-constants.vh b/wally-pipelined/config/rv64icfd/wally-constants.vh new file mode 100644 index 00000000..55fb4e94 --- /dev/null +++ b/wally-pipelined/config/rv64icfd/wally-constants.vh @@ -0,0 +1,31 @@ +////////////////////////////////////////// +// wally-constants.vh +// +// Written: tfleming@hmc.edu 4 March 2021 +// Modified: +// +// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture. +// These macros should not be changed, except in the event of an +// update to the architecture or particularly special circumstances. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Virtual Memory Constants (sv39) +`define VPN_BITS 27 +`define PPN_BITS 44 +`define PA_BITS 56 diff --git a/wally-pipelined/regression/regression-wally.sh b/wally-pipelined/regression/regression-wally.sh new file mode 100755 index 00000000..39d82102 --- /dev/null +++ b/wally-pipelined/regression/regression-wally.sh @@ -0,0 +1,34 @@ +#!/usr/bin/env bash +check_test () { + output=$(timeout 2m ./"$1" 2>/dev/null) + found=$(echo $output | grep -c "$2") + echo "$found" +} +echo "-----------------------" +echo "starting all regression tests!" +echo "note: this could take up to 3 minutes to run" +echo "-----------------------" +echo "checking verilator" +verilator_out=$(cd ..; ./lint-wally 2>&1) +[[ -z $verilator_out ]] && echo "verilator passed" || echo "verilator failed" +echo "starting Imperas rv64ic" +sleep 1 +exec 3< <(check_test "sim-wally-batch" "All tests ran without failures.") +#echo "starting Imperas rv32ic" +#sleep 1 +#exec 5< <(check_test "sim-wally-rv32ic" "All tests ran without failures.") +#echo "starting busybear" +sleep 1 +exec 4< <(check_test "sim-busybear-batch" "loaded 100000 instructions") +echo "-----------------------" +echo "waiting for tests to finish..." +echo "-----------------------" +rv64_out=$(cat <&3) +[[ $rv64_out -eq 1 ]] && echo "rv64ic passed" || echo "rv64ic failed" +#rv32_out=$(cat <&5) +#[[ $rv32_out -eq 1 ]] && echo "rv32ic passed" || echo "rv32ic failed" +busybear_out=$(cat <&4) +[[ $busybear_out -eq 1 ]] && echo "busybear passed" || echo "busybear failed" + +[[ -z $verilator_out && $rv64_out -eq 1 && $busybear_out -eq 1 ]] && echo "all passed" || echo "not all passed" +#[[ -z $verilator_out && $rv32_out -eq 1 && $rv64_out -eq 1 && $busybear_out -eq 1 ]] && echo "all passed" || echo "not all passed" diff --git a/wally-pipelined/regression/sim-wally-rv32ic b/wally-pipelined/regression/sim-wally-rv32ic new file mode 100755 index 00000000..a254c824 --- /dev/null +++ b/wally-pipelined/regression/sim-wally-rv32ic @@ -0,0 +1,3 @@ +vsim -c <NextBusState->GrantData->HSIZE->HSELUART->HREADY - // This is because the peripherals assert HREADY on the same cycle - // When memory is working, also fix the peripherals to respond on the subsequent cycle - // and this path should be fixed. - + // bus outputs - assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE); + assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || + (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE); assign #1 HADDR = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0]; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign #1 HSIZE = GrantData ? {1'b0, MemSizeM} : ISize; @@ -125,9 +133,9 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise assign HMASTLOCK = 0; // no locking supported - assign HWRITE = (NextBusState == MEMWRITE); + assign HWRITE = (NextBusState == MEMWRITE) || (NextBusState == ATOMICWRITE); // delay write data by one cycle for - flop #(`XLEN) wdreg(HCLK, WriteDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); @@ -138,11 +146,26 @@ module ahblite ( assign InstrRData = HRDATA; assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 - assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD); + assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) || + ((BusState == ATOMICREAD) && (NextBusState == ATOMICWRITE)); + // *** check if this introduces an unnecessary cycle of latency in memory accesses flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read flopenr #(`XLEN) ReadDataWReg(clk, reset, ~StallW, ReadDataPreW, ReadDataW); + // Extract and sign-extend subwords if necessary subwordread swr(.*); -endmodule + // Handle AMO instructions if applicable + generate + if (`A_SUPPORTED) begin + logic [`XLEN-1:0] AMOResult; +// amoalu amoalu(.a(HRDATA), .b(WriteDataM), .funct(Funct7M), .width(MemSizeM), +// .result(AMOResult)); + amoalu amoalu(.srca(ReadDataPreW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM), + .result(AMOResult)); + mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicM[1], WriteData); + end else + assign WriteData = WriteDataM; + endgenerate +endmodule diff --git a/wally-pipelined/src/ebu/amoalu.sv b/wally-pipelined/src/ebu/amoalu.sv new file mode 100644 index 00000000..8acba98c --- /dev/null +++ b/wally-pipelined/src/ebu/amoalu.sv @@ -0,0 +1,78 @@ +/////////////////////////////////////////// +// amoalu.sv +// +// Written: David_Harris@hmc.edu 10 March 2021 +// Modified: +// +// Purpose: Performs AMO operations +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module amoalu ( + input logic [`XLEN-1:0] srca, srcb, + input logic [6:0] funct, + input logic [1:0] width, + output logic [`XLEN-1:0] result); + + logic [`XLEN-1:0] a, b, y; + + // *** can this be muxed into the regular ALU to avoid needing a second one? Only a good + // idea if the regular ALU is not the critical path + + // *** see how synthesis generates this and optimize more structurally if necessary to share hardware + // a single carry chain should be shared for + and the four min/max + // and the same mux can be used to select b for swap. + always_comb + case (funct[6:2]) + 5'b00001: y = b; // amoswap + 5'b00000: y = a + b; // amoadd + 5'b00100: y = a ^ b; // amoxor + 5'b01100: y = a & b; // amoand + 5'b01000: y = a | b; // amoor + 5'b10000: y = ($signed(a) < $signed(b)) ? a : b; // amomin + 5'b10100: y = ($signed(a) >= $signed(b)) ? a : b; // amomax + 5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b; // amominu + 5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu + default: y = 'bx; // undefined; *** could change to b for efficiency + endcase + + // sign extend if necessary + generate + if (`XLEN == 32) begin + assign a = srca; + assign b = srcb; + assign result = y; + end else begin // `XLEN = 64 + always_comb + if (width == 2'b10) begin // sign-extend word-length operations + // *** it would be more efficient to look at carry out of bit 31 to determine comparisons than do this big mux on and b + a = {{32{srca[31]}}, srca[31:0]}; + b = {{32{srcb[31]}}, srcb[31:0]}; + result = {{32{y[31]}}, y[31:0]}; + end else begin + a = srca; + b = srcb; + result = y; + end + end + endgenerate + +endmodule + diff --git a/wally-pipelined/src/ebu/pagetablewalker.sv_dev b/wally-pipelined/src/ebu/pagetablewalker.sv_dev new file mode 100644 index 00000000..eaed0948 --- /dev/null +++ b/wally-pipelined/src/ebu/pagetablewalker.sv_dev @@ -0,0 +1,106 @@ +/////////////////////////////////////////// +// pagetablewalker.sv +// +// Written: tfleming@hmc.edu 2 March 2021 +// Modified: +// +// Purpose: Page Table Walker +// Part of the Memory Management Unit (MMU) +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module pagetablewalker ( + input logic clk, reset, + + input logic [`XLEN-1:0] SATP_REGW, + + input logic ITLBMissF, DTLBMissM, + input logic [`XLEN-1:0] TranslationVAdr, + + input logic HCLK, HRESETn, + + input logic HREADY, + + output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM, + output logic ITLBWriteF, DTLBWriteM, + output logic TranslationComplete +); + + /* + generate + if (`XLEN == 32) begin + logic Sv_Mode = satp[31] + end else begin + logic Sv_Mode [3:0] = satp[63:60] + end + endgenerate + */ + + logic Sv_Mode = SATP_REGW[31]; + logic BasePageTablePPN [21:0] = SATP_REGW[21:0]; + + logic VPN1 [9:0] = TranslationVAdr[31:22]; + logic VPN0 [9:0] = TranslationVAdr[21:12]; // *** could optimize by not passing offset? + + logic TranslationPAdr [33:0]; + + typedef enum {IDLE, DATA_LEVEL1, DATA_LEVEL0, DATA_LEAF, DATA FAULT} statetype; + statetype WalkerState, NextWalkerState; + + always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) WalkerState <= #1 IDLE; + else WalkerState <= #1 NextWalkerState; + + always_comb begin + NextWalkerState = 'X; + case (WalkerState) + IDLE: if (TLBMissM) NextWalkerState = LEVEL1; + else NextWalkerState = IDLE; + LEVEL1: if (HREADY && ValidEntry) NextWalkerState = LEVEL0; + else if (HREADY) NextWalkerState = FAULT; + else NextWalkerState = LEVEL1; + LEVEL2: if (HREADY && ValidEntry) NextWalkerState = LEAF; + else if (HREADY) NextWalkerState = FAULT; + else NextWalkerState = LEVEL2; + LEAF: NextWalkerState = IDLE; + endcase + end + + always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) begin + TranslationPAdr <= '0; + PageTableEntryF <= '0; + TranslationComplete <= '0; + end else begin + // default values + case (NextWalkerState) + LEVEL1: TranslationPAdr <= {BasePageTablePPN, VPN1, 2'b00}; + LEVEL2: TranslationPAdr <= {CurrentPPN, VPN0, 2'b00}; + LEAF: begin + PageTableEntryF <= CurrentPageTableEntry; + TranslationComplete <= '1; + end + endcase + end + + assign #1 Translate = (NextWalkerState == LEVEL1); + + +endmodule \ No newline at end of file diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index dc4f16d5..a1be47ad 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -48,7 +48,7 @@ module controller( input logic StallM, FlushM, output logic [1:0] MemRWM, output logic CSRReadM, CSRWriteM, PrivilegedM, - output logic AtomicM, + output logic [1:0] AtomicM, output logic [2:0] Funct3M, output logic RegWriteM, // for Hazard Unit // Writeback stage control signals @@ -65,6 +65,8 @@ module controller( logic [6:0] Funct7D; logic [4:0] Rs1D; + `define CTRLW 23 + // pipelined control signals logic RegWriteD, RegWriteE; logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; @@ -77,11 +79,11 @@ module controller( logic TargetSrcD, W64D, MulDivD; logic CSRZeroSrcD; logic CSRReadD; - logic AtomicD, AtomicE; + logic [1:0] AtomicD, AtomicE; logic CSRWriteD, CSRWriteE; logic InstrValidE, InstrValidM; logic PrivilegedD, PrivilegedE; - logic [21:0] ControlsD; + logic [`CTRLW-1:0] ControlsD; logic aluc3D; logic subD, sraD, sltD, sltuD; logic BranchTakenE; @@ -100,48 +102,47 @@ module controller( generate always_comb case(OpD) - // *** Atomic p. 132 assembly encodings, defs 48 // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_TargetSrc_W64_CSRRead_Privileged_MulDiv_Atomic_Illegal - 7'b0000000: ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_1; // illegal instruction - 7'b0000011: ControlsD = 22'b1_000_01_10_001_0_00_0_0_0_0_0_0_0_0; // lw - 7'b0001111: ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_0; // fence = nop - 7'b0010011: ControlsD = 22'b1_000_01_00_000_0_10_0_0_0_0_0_0_0_0; // I-type ALU - 7'b0010111: ControlsD = 22'b1_100_11_00_000_0_00_0_0_0_0_0_0_0_0; // auipc + 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_00_1; // illegal instruction + 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_00_0_0_0_0_0_0_00_0; // lw + 7'b0001111: ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_00_0; // fence = nop + 7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_10_0_0_0_0_0_0_00_0; // I-type ALU + 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_00_0_0_0_0_0_0_00_0; // auipc 7'b0011011: if (`XLEN == 64) - ControlsD = 22'b1_000_01_00_000_0_10_0_0_1_0_0_0_0_0; // IW-type ALU for RV64i + ControlsD = `CTRLW'b1_000_01_00_000_0_10_0_0_1_0_0_0_00_0; // IW-type ALU for RV64i else - ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_1; // non-implemented instruction - 7'b0100011: ControlsD = 22'b0_001_01_01_000_0_00_0_0_0_0_0_0_0_0; // sw + ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_00_1; // non-implemented instruction + 7'b0100011: ControlsD = `CTRLW'b0_001_01_01_000_0_00_0_0_0_0_0_0_00_0; // sw 7'b0101111: if (`A_SUPPORTED) begin if (InstrD[31:27] == 5'b00010) - ControlsD = 22'b1_000_00_10_001_0_00_0_0_0_0_0_0_1_0; // lr + ControlsD = `CTRLW'b1_000_00_10_001_0_00_0_0_0_0_0_0_01_0; // lr else if (InstrD[31:27] == 5'b00011) - ControlsD = 22'b1_101_01_01_101_0_00_0_0_0_0_0_0_1_0; // sc + ControlsD = `CTRLW'b1_101_01_01_101_0_00_0_0_0_0_0_0_01_0; // sc else - ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_1_0; // other atomic; decode later + ControlsD = `CTRLW'b1_101_01_11_001_0_00_0_0_0_0_0_0_10_0;; // amo end else - ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_1; // non-implemented instruction + ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_00_1; // non-implemented instruction 7'b0110011: if (Funct7D == 7'b0000000 || Funct7D == 7'b0100000) - ControlsD = 22'b1_000_00_00_000_0_10_0_0_0_0_0_0_0_0; // R-type + ControlsD = `CTRLW'b1_000_00_00_000_0_10_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 && `M_SUPPORTED) - ControlsD = 22'b1_000_00_00_100_0_00_0_0_0_0_0_1_0_0; // Multiply/Divide + ControlsD = `CTRLW'b1_000_00_00_100_0_00_0_0_0_0_0_1_00_0; // Multiply/Divide else - ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_1; // non-implemented instruction - 7'b0110111: ControlsD = 22'b1_100_01_00_000_0_11_0_0_0_0_0_0_0_0; // lui + ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_00_1; // non-implemented instruction + 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_11_0_0_0_0_0_0_00_0; // lui 7'b0111011: if ((Funct7D == 7'b0000000 || Funct7D == 7'b0100000) && `XLEN == 64) - ControlsD = 22'b1_000_00_00_000_0_10_0_0_1_0_0_0_0_0; // R-type W instructions for RV64i + ControlsD = `CTRLW'b1_000_00_00_000_0_10_0_0_1_0_0_0_00_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 && `M_SUPPORTED && `XLEN == 64) - ControlsD = 22'b1_000_00_00_100_0_00_0_0_1_0_0_1_0_0; // W-type Multiply/Divide + ControlsD = `CTRLW'b1_000_00_00_100_0_00_0_0_1_0_0_1_00_0; // W-type Multiply/Divide else - ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_1; // non-implemented instruction - 7'b1100011: ControlsD = 22'b0_010_00_00_000_1_01_0_0_0_0_0_0_0_0; // beq - 7'b1100111: ControlsD = 22'b1_000_00_00_010_0_00_1_1_0_0_0_0_0_0; // jalr - 7'b1101111: ControlsD = 22'b1_011_00_00_010_0_00_1_0_0_0_0_0_0_0; // jal + ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_00_1; // non-implemented instruction + 7'b1100011: ControlsD = `CTRLW'b0_010_00_00_000_1_01_0_0_0_0_0_0_00_0; // beq + 7'b1100111: ControlsD = `CTRLW'b1_000_00_00_010_0_00_1_1_0_0_0_0_00_0; // jalr + 7'b1101111: ControlsD = `CTRLW'b1_011_00_00_010_0_00_1_0_0_0_0_0_00_0; // jal 7'b1110011: if (Funct3D == 3'b000) - ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_1_0_0_0; // privileged; decoded further in priveleged modules + ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_1_0_00_0; // privileged; decoded further in priveleged modules else - ControlsD = 22'b1_000_00_00_011_0_00_0_0_0_1_0_0_0_0; // csrs - default: ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_1; // non-implemented instruction + ControlsD = `CTRLW'b1_000_00_00_011_0_00_0_0_0_1_0_0_00_0; // csrs + default: ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_00_1; // non-implemented instruction endcase endgenerate @@ -173,7 +174,7 @@ module controller( endcase // Execute stage pipeline control register and logic - flopenrc #(26) controlregE(clk, reset, FlushE, ~StallE, + flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE, {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, 1'b1}, {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InstrValidE}); @@ -196,7 +197,7 @@ module controller( assign MemReadE = MemRWE[1]; // Memory stage pipeline control register - flopenrc #(14) controlregM(clk, reset, FlushM, ~StallM, + flopenrc #(15) controlregM(clk, reset, FlushM, ~StallM, {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, AtomicE, InstrValidE}, {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InstrValidM}); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index d021bca6..f408fbd9 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -43,7 +43,7 @@ module ieu ( input logic DataAccessFaultM, input logic SquashSCW, output logic [1:0] MemRWM, - output logic AtomicM, + output logic [1:0] AtomicM, output logic [`XLEN-1:0] MemAdrM, WriteDataM, output logic [`XLEN-1:0] SrcAM, output logic [2:0] Funct3M, diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 815ad840..68325aff 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -56,9 +56,8 @@ module ifu ( output logic [`XLEN-1:0] InstrMisalignedAdrM, // TLB management //input logic [`XLEN-1:0] PageTableEntryF, + input logic [`XLEN-1:0] SATP_REGW, //input logic ITLBWriteF, ITLBFlushF, - // *** satp value will come from CSRs - // input logic [`XLEN-1:0] SATP, output logic ITLBMissF, ITLBHitF, // bogus input logic [15:0] rd2 @@ -74,14 +73,11 @@ module ifu ( logic [31:0] InstrF, InstrRawD, InstrE, InstrW; logic [31:0] nop = 32'h00000013; // instruction for NOP - // *** temporary hack until we can figure out how to get actual satp value - // from priv unit -- Thomas F - logic [`XLEN-1:0] SATP = '0; // *** temporary hack until walker is hooked up -- Thomas F logic [`XLEN-1:0] PageTableEntryF = '0; logic ITLBFlushF = '0; logic ITLBWriteF = '0; - tlb #(3) itlb(clk, reset, SATP, PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF, + tlb #(3) itlb(clk, reset, SATP_REGW, PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF, InstrPAdrF, ITLBMissF, ITLBHitF); // branch predictor signals diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 7be0f0b7..4d4e46a3 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -25,6 +25,7 @@ /////////////////////////////////////////// `include "wally-config.vh" +`include "wally-constants.vh" /** * sv32 specs @@ -57,7 +58,7 @@ module tlb #(parameter ENTRY_BITS = 3) ( input clk, reset, // Current value of satp CSR (from privileged unit) - input [`XLEN-1:0] SATP, // *** How do we get this? + input [`XLEN-1:0] SATP_REGW, // Virtual address input input [`XLEN-1:0] VirtualAddress, @@ -75,32 +76,29 @@ module tlb #(parameter ENTRY_BITS = 3) ( output TLBHit ); + logic SvMode; + generate - if (`XLEN == 32) begin: ARCH - localparam VPN_BITS = 20; - localparam PPN_BITS = 22; - localparam PA_BITS = 34; - - logic SvMode; - assign SvMode = SATP[31]; // *** change to an enum somehow? - end else begin: ARCH - localparam VPN_BITS = 27; - localparam PPN_BITS = 44; - localparam PA_BITS = 56; - - logic SvMode; // currently just a boolean whether translation enabled - assign SvMode = SATP[63]; // *** change to an enum somehow? + if (`XLEN == 32) begin + assign SvMode = SATP_REGW[31]; // *** change to an enum somehow? + end else begin + assign SvMode = SATP_REGW[63]; // currently just a boolean whether translation enabled end endgenerate + // *** If we want to support multiple virtual memory modes (ie sv39 AND sv48), + // we could have some muxes that control which parameters are current. + // Although then some of the signals are not big enough. But that's a problem + // for much later. + // Index (currently random) to write the next TLB entry logic [ENTRY_BITS-1:0] WriteIndex; // Sections of the virtual and physical addresses - logic [ARCH.VPN_BITS-1:0] VirtualPageNumber; - logic [ARCH.PPN_BITS-1:0] PhysicalPageNumber; - logic [11:0] PageOffset; - logic [ARCH.PA_BITS-1:0] PhysicalAddressFull; + logic [`VPN_BITS-1:0] VirtualPageNumber; + logic [`PPN_BITS-1:0] PhysicalPageNumber; + logic [11:0] PageOffset; + logic [`PA_BITS-1:0] PhysicalAddressFull; // Pattern and pattern location in the CAM logic [ENTRY_BITS-1:0] VPNIndex; @@ -111,7 +109,7 @@ module tlb #(parameter ENTRY_BITS = 3) ( // Page table entry matching the virtual address logic [`XLEN-1:0] PageTableEntry; - assign VirtualPageNumber = VirtualAddress[ARCH.VPN_BITS+11:12]; + assign VirtualPageNumber = VirtualAddress[`VPN_BITS+11:12]; assign PageOffset = VirtualAddress[11:0]; // Choose a read or write location to the entry list @@ -121,28 +119,28 @@ module tlb #(parameter ENTRY_BITS = 3) ( tlb_rand rdm(.*); tlb_ram #(ENTRY_BITS) ram(.*); - tlb_cam #(ENTRY_BITS, ARCH.VPN_BITS) cam(.*); + tlb_cam #(ENTRY_BITS, `VPN_BITS) cam(.*); always_comb begin - assign PhysicalPageNumber = PageTableEntry[ARCH.PPN_BITS+9:10]; + assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10]; if (TLBHit) begin assign PhysicalAddressFull = {PhysicalPageNumber, PageOffset}; end else begin - assign PhysicalAddressFull = 8'b0; // *** Actual behavior; disabled until walker functioning + assign PhysicalAddressFull = '0; // *** Actual behavior; disabled until walker functioning //assign PhysicalAddressFull = {2'b0, VirtualPageNumber, PageOffset} // *** pass through should be removed as soon as walker ready end end generate if (`XLEN == 32) begin - mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], ARCH.SvMode, PhysicalAddress); + mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], SvMode, PhysicalAddress); end else begin - mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, ARCH.SvMode, PhysicalAddress); + mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, SvMode, PhysicalAddress); end endgenerate - assign TLBMiss = ~TLBHit & ~(TLBWrite | TLBFlush) & ARCH.SvMode; + assign TLBMiss = ~TLBHit & ~(TLBWrite | TLBFlush) & SvMode; endmodule module tlb_ram #(parameter ENTRY_BITS = 3) ( @@ -217,13 +215,13 @@ module tlb_cam #(parameter ENTRY_BITS = 3, initial begin for (int i = 0; i < NENTRIES; i++) - ram[i] <= '0; + ram[i] = '0; end endmodule module tlb_rand #(parameter ENTRY_BITS = 3) ( - input clk, reset, + input clk, reset, output [ENTRY_BITS-1:0] WriteIndex ); diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index f1f16ac9..5d3c24a4 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -40,6 +40,7 @@ module csr ( output logic STATUS_SPP, STATUS_TSR, output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, + output logic [`XLEN-1:0] SATP_REGW, output logic [11:0] MIP_REGW, MIE_REGW, output logic STATUS_MIE, STATUS_SIE, input logic [4:0] SetFflagsM, @@ -126,6 +127,7 @@ module csr ( assign MIDELEG_REGW = 0; assign SEDELEG_REGW = 0; assign SIDELEG_REGW = 0; + assign SATP_REGW = 0; assign MIP_REGW = 0; assign MIE_REGW = 0; assign STATUS_MIE = 0; diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index 19d533c8..8b851e07 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -48,6 +48,7 @@ module csrs #(parameter output logic [`XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW, output logic [31:0] SCOUNTEREN_REGW, output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW, + output logic [`XLEN-1:0] SATP_REGW, input logic [11:0] SIP_REGW, SIE_REGW, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM @@ -63,7 +64,7 @@ module csrs #(parameter logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; - logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW, SATP_REGW; + logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW; assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS); assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC); @@ -127,6 +128,7 @@ module csrs #(parameter assign SEDELEG_REGW = 0; assign SIDELEG_REGW = 0; assign SCOUNTEREN_REGW = 0; + assign SATP_REGW = 0; assign IllegalCSRSAccessM = 1; end endgenerate diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 71b90586..a01fa557 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -44,6 +44,7 @@ module privileged ( input logic TimerIntM, ExtIntM, SwIntM, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [4:0] SetFflagsM, + output logic [`XLEN-1:0] SATP_REGW, output logic [2:0] FRM_REGW, input logic FlushD, FlushE, FlushM, StallD, StallW ); diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index 42ae7fbc..5d3f47e3 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -59,7 +59,7 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( busycount <= 0; HREADYTim <= #1 0; end else if (~HREADYTim) begin - if (busycount == 2) begin // TIM latency, for testing purposes + if (busycount == 2) begin // TIM latency, for testing purposes. *** test with different values HREADYTim <= #1 1; end else begin busycount <= busycount + 1; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 3c8b25c3..bd69739c 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -60,7 +60,8 @@ module wallypipelinedhart ( // new signals that must connect through DP logic MulDivE, W64E; - logic CSRReadM, CSRWriteM, PrivilegedM, AtomicM; + logic CSRReadM, CSRWriteM, PrivilegedM; + logic [1:0] AtomicM; logic [`XLEN-1:0] SrcAE, SrcBE; logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; @@ -88,8 +89,12 @@ module wallypipelinedhart ( logic SquashSCW; // memory management unit signals + logic ITLBWriteF, DTLBWriteM; logic ITLBMissF, ITLBHitF; logic DTLBMissM, DTLBHitM; + logic [`XLEN-1:0] SATP_REGW; + + logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM; // bus interface to dmem logic MemReadM, MemWriteM; @@ -113,8 +118,11 @@ module wallypipelinedhart ( //.InstrReadF(1'b0), //.InstrRData(InstrF), // hook up InstrF later .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]), + .Funct7M(InstrM[31:25]), .*); + // walker walker(.*); *** // can send addresses to ahblite, send out pagetablestall + // *** can connect to hazard unit // changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed. // Would need to insertinstruction as InstrD, not InstrF /*ahblite ebu( diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index e4c9c9e3..ababf7e4 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -294,7 +294,7 @@ module testbench_busybear(); `CHECK_CSR(MTVEC) //`CHECK_CSR2(PMPADDR0, `CSRM) //`CHECK_CSR2(PMdut.PCFG0, `CSRM) - `CHECK_CSR2(SATP, `CSRS) + `CHECK_CSR(SATP) `CHECK_CSR2(SCAUSE, `CSRS) `CHECK_CSR(SCOUNTEREN) `CHECK_CSR(SEPC) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 275b4a9b..555ece82 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -43,6 +43,7 @@ module testbench(); //logic [31:0] InstrW; logic [`XLEN-1:0] meminit; string tests64a[] = '{ + "rv64a/WALLY-AMO", "2110", "rv64a/WALLY-LRSC", "2110" }; string tests64m[] = '{ @@ -195,6 +196,10 @@ string tests64iNOc[] = { "rv64i/WALLY-CSRRCI", "4000" }; + string tests32a[] = '{ + "rv64a/WALLY-AMO", "2110", + "rv64a/WALLY-LRSC", "2110" + }; string tests32m[] = '{ "rv32m/I-MUL-01", "2000", "rv32m/I-MULH-01", "2000", @@ -334,13 +339,14 @@ string tests32i[] = { if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; - if (`A_SUPPORTED) tests = {tests64a, tests}; + if (`A_SUPPORTED) tests = {tests, tests64a}; // tests = {tests64a, tests}; end else begin // RV32 tests = {tests32i}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; else tests = {tests, tests32iNOc}; if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; + if (`A_SUPPORTED) tests = {tests, tests32a}; end string signame, memfilename;