From 6e85f850a417a1733abfbef3805f6f9d3d5b74a8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 Aug 2022 14:45:01 -0500 Subject: [PATCH] Moved files. Encapsulated ahbinterface. --- pipelined/src/ebu/AHBBuscachefsm.sv | 163 +++++++++++++++++++++++++ pipelined/src/ebu/AHBBusfsm.sv | 86 +++++++++++++ pipelined/src/ebu/abhinterface.sv | 74 +++++++++++ pipelined/src/ebu/ahbcacheinterface.sv | 89 ++++++++++++++ pipelined/src/lsu/lsu.sv | 12 +- 5 files changed, 415 insertions(+), 9 deletions(-) create mode 100644 pipelined/src/ebu/AHBBuscachefsm.sv create mode 100644 pipelined/src/ebu/AHBBusfsm.sv create mode 100644 pipelined/src/ebu/abhinterface.sv create mode 100644 pipelined/src/ebu/ahbcacheinterface.sv diff --git a/pipelined/src/ebu/AHBBuscachefsm.sv b/pipelined/src/ebu/AHBBuscachefsm.sv new file mode 100644 index 00000000..d8f78653 --- /dev/null +++ b/pipelined/src/ebu/AHBBuscachefsm.sv @@ -0,0 +1,163 @@ +/////////////////////////////////////////// +// busfsm.sv +// +// Written: Ross Thompson ross1728@gmail.com December 29, 2021 +// Modified: +// +// Purpose: Load/Store Unit's interface to BUS for cacheless system +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// HCLK and clk must be the same clock! +module AHBBuscachefsm #(parameter integer WordCountThreshold, + parameter integer LOGWPL, parameter logic CACHE_ENABLED ) + (input logic HCLK, + input logic HRESETn, + + // IEU interface + input logic [1:0] RW, + input logic CPUBusy, + output logic BusCommitted, + output logic BusStall, + output logic CaptureEn, + + // cache interface + input logic [1:0] CacheRW, + output logic CacheBusAck, + + // lsu interface + output logic SelUncachedAdr, + output logic [LOGWPL-1:0] WordCount, WordCountDelayed, + output logic SelBusWord, + + // BUS interface + input logic HREADY, + output logic [1:0] HTRANS, + output logic HWRITE, + output logic [2:0] HBURST +); + + typedef enum logic [2:0] {STATE_READY, + STATE_CAPTURE, + STATE_DELAY, + STATE_CPU_BUSY, + STATE_CACHE_FETCH, + STATE_CACHE_EVICT} busstatetype; + + typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; + + (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; + + logic [LOGWPL-1:0] NextWordCount; + logic FinalWordCount; + logic [2:0] LocalBurstType; + logic WordCntEn; + logic WordCntReset; + logic CacheAccess; + + always_ff @(posedge HCLK) + if (~HRESETn) BusCurrState <= #1 STATE_READY; + else BusCurrState <= #1 BusNextState; + + always_comb begin + case(BusCurrState) + STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE; + else if (HREADY & CacheRW[0]) BusNextState = STATE_CACHE_EVICT; + else if (HREADY & CacheRW[1]) BusNextState = STATE_CACHE_FETCH; + else BusNextState = STATE_READY; + STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY; + else BusNextState = STATE_CAPTURE; + STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + STATE_CACHE_FETCH: if(HREADY & FinalWordCount) BusNextState = STATE_READY; + else BusNextState = STATE_CACHE_FETCH; + STATE_CACHE_EVICT: if(HREADY & FinalWordCount) BusNextState = STATE_READY; + else BusNextState = STATE_CACHE_EVICT; + default: BusNextState = STATE_READY; + endcase + end + + // IEU, LSU, and IFU controls + flopenr #(LOGWPL) + WordCountReg(.clk(HCLK), + .reset(~HRESETn | WordCntReset), + .en(WordCntEn), + .d(NextWordCount), + .q(WordCount)); + + // Used to store data from data phase of AHB. + flopenr #(LOGWPL) + WordCountDelayedReg(.clk(HCLK), + .reset(~HRESETn | WordCntReset), + .en(WordCntEn), + .d(WordCount), + .q(WordCountDelayed)); + assign NextWordCount = WordCount + 1'b1; + + assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0]; + assign WordCntEn = ((BusNextState == STATE_CACHE_EVICT | BusNextState == STATE_CACHE_FETCH) & HREADY) | + (BusNextState == STATE_READY & |CacheRW & HREADY); + assign WordCntReset = BusNextState == STATE_READY; + + assign CaptureEn = (BusCurrState == STATE_CAPTURE & RW[1]) | (BusCurrState == STATE_CACHE_FETCH & HREADY); + assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT; + + assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) | + (BusCurrState == STATE_CAPTURE) | + (BusCurrState == STATE_CACHE_FETCH) | + (BusCurrState == STATE_CACHE_EVICT); + assign BusCommitted = BusCurrState != STATE_READY; + assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) | + (BusCurrState == STATE_CAPTURE) | + (BusCurrState == STATE_DELAY); + + // AHB bus interface + assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) | + (BusCurrState == STATE_CAPTURE & ~HREADY) | + (CacheAccess & ~HREADY & ~|WordCount) ? AHB_NONSEQ : + (CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE; + + assign HWRITE = RW[0] | CacheRW[0]; + assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; + + always_comb begin + case(WordCountThreshold) + 0: LocalBurstType = 3'b000; + 3: LocalBurstType = 3'b011; // INCR4 + 7: LocalBurstType = 3'b101; // INCR8 + 15: LocalBurstType = 3'b111; // INCR16 + default: LocalBurstType = 3'b001; // INCR without end. + endcase + end + + // communication to cache + assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); + assign SelBusWord = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | + (BusCurrState == STATE_CAPTURE & RW[0]) | + (BusCurrState == STATE_CACHE_EVICT); + +endmodule diff --git a/pipelined/src/ebu/AHBBusfsm.sv b/pipelined/src/ebu/AHBBusfsm.sv new file mode 100644 index 00000000..b88d5ed4 --- /dev/null +++ b/pipelined/src/ebu/AHBBusfsm.sv @@ -0,0 +1,86 @@ +/////////////////////////////////////////// +// busfsm.sv +// +// Written: Ross Thompson ross1728@gmail.com December 29, 2021 +// Modified: +// +// Purpose: Load/Store Unit's interface to BUS for cacheless system +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// HCLK and clk must be the same clock! +module AHBBusfsm + (input logic HCLK, + input logic HRESETn, + + // IEU interface + input logic [1:0] RW, + input logic CPUBusy, + output logic BusCommitted, + output logic BusStall, + output logic CaptureEn, + input logic HREADY, + output logic [1:0] HTRANS, + output logic HWRITE +); + + typedef enum logic [2:0] {STATE_READY, + STATE_CAPTURE, + STATE_DELAY, + STATE_CPU_BUSY} busstatetype; + + typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; + + (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; + + always_ff @(posedge HCLK) + if (~HRESETn) BusCurrState <= #1 STATE_READY; + else BusCurrState <= #1 BusNextState; + + always_comb begin + case(BusCurrState) + STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE; + else BusNextState = STATE_READY; + STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY; + else BusNextState = STATE_CAPTURE; + STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + default: BusNextState = STATE_READY; + endcase + end + + assign BusStall = (BusCurrState == STATE_READY & |RW) | + (BusCurrState == STATE_CAPTURE); + + assign BusCommitted = BusCurrState != STATE_READY; + + assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) | + (BusCurrState == STATE_CAPTURE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE; + assign HWRITE = (BusCurrState == STATE_READY) & RW[0]; // *** might not be necessary, maybe just RW[0] + assign CaptureEn = BusCurrState == STATE_CAPTURE; + +endmodule diff --git a/pipelined/src/ebu/abhinterface.sv b/pipelined/src/ebu/abhinterface.sv new file mode 100644 index 00000000..d2d23703 --- /dev/null +++ b/pipelined/src/ebu/abhinterface.sv @@ -0,0 +1,74 @@ +/////////////////////////////////////////// +// ahbinterface.sv +// +// Written: Ross Thompson ross1728@gmail.com August 29, 2022 +// Modified: +// +// Purpose: Cache/Bus data path. +// Bus Side logic +// register the fetch data from the next level of memory. +// This register should be necessary for timing. There is no register in the uncore or +// ahblite controller between the memories and this cache. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ahbinterface #(parameter WRITEABLE = 0) + ( + input logic HCLK, HRESETn, + + // bus interface + input logic HREADY, + input logic [`XLEN-1:0] HRDATA, + output logic [1:0] HTRANS, + output logic HWRITE, + output logic [`XLEN-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, + + // lsu/ifu interface + input logic [1:0] RW, + input logic [`XLEN/8-1:0] ByteMask, + input logic [`XLEN-1:0] WriteData, + input logic CPUBusy, + output logic BusStall, + output logic BusCommitted, + output logic [`XLEN-1:0] ReadDataWordM); + + logic CaptureEn; + + flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM)); + + if(WRITEABLE) begin + // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA); + flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB); + end else begin + assign HWDATA = '0; + assign HWSTRB = '0; + end + + AHBBusfsm busfsm(.HCLK, .HRESETn, .RW, + .BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY, + .HTRANS, .HWRITE); +endmodule diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv new file mode 100644 index 00000000..758e2969 --- /dev/null +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -0,0 +1,89 @@ +/////////////////////////////////////////// +// ahbcacheinterface.sv +// +// Written: Ross Thompson ross1728@gmail.com August 29, 2022 +// Modified: +// +// Purpose: Cache/Bus data path. +// Bus Side logic +// register the fetch data from the next level of memory. +// This register should be necessary for timing. There is no register in the uncore or +// ahblite controller between the memories and this cache. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) + ( + input logic HCLK, HRESETn, + + // bus interface + input logic HREADY, + input logic [`XLEN-1:0] HRDATA, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [1:0] HTRANS, + output logic HWRITE, + output logic [`PA_BITS-1:0] HADDR, + output logic [LOGWPL-1:0] WordCount, + + // cache interface + input logic [`PA_BITS-1:0] CacheBusAdr, + input logic [1:0] CacheRW, + output logic CacheBusAck, + output logic [LINELEN-1:0] FetchBuffer, + output logic SelUncachedAdr, + + // lsu/ifu interface + input logic [`PA_BITS-1:0] PAdr, + input logic [1:0] RW, + input logic CPUBusy, + input logic [2:0] Funct3, + output logic SelBusWord, + output logic BusStall, + output logic BusCommitted); + + localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; + logic [`PA_BITS-1:0] LocalHADDR; + logic [LOGWPL-1:0] WordCountDelayed; + logic CaptureEn; + + genvar index; + for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer + logic [WORDSPERLINE-1:0] CaptureWord; + assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed); + flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); + end + + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR); + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; + + mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE)); + + AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( + .HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, + .CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed, + .HREADY, .HTRANS, .HWRITE, .HBURST); +endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index dfdaeb92..0e0b17d2 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -282,7 +282,6 @@ module lsu ( swbytemask #(`XLEN) busswbytemask(.Size(LSUHSIZE), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(BusByteMaskM)); flop #(`XLEN/8) HWSTRBReg(clk, BusByteMaskM[`XLEN/8-1:0], LSUHWSTRB); - end else begin : passthrough // just needs a register to hold the value from the bus logic CaptureEn; @@ -291,15 +290,10 @@ module lsu ( assign LSUHADDR = LSUPAdrM; assign LSUHSIZE = LSUFunct3M; - - flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM)); - flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN - flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB); - - AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, - .BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS), - .HWRITE(LSUHWRITE)); + ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), + .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), + .HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM); assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping assign LSUHBURST = 3'b0;