From 6c45da022b0c29ecea807f74494abfd5dbfff520 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 30 Dec 2021 15:51:07 -0600 Subject: [PATCH] Progress on non dcache mode working. --- wally-pipelined/src/ifu/ifu.sv | 2 +- wally-pipelined/src/lsu/busfsm.sv | 21 ++++++++++++--------- wally-pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index eda0490b..208056d3 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -218,7 +218,7 @@ module ifu ( assign LocalIfuBusAdr = SelUncachedAdr ? PCPFmmu : ICacheBusAdr; assign IfuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIfuBusAdr; - busfsm #(WordCountThreshold, LOGWPL) + busfsm #(WordCountThreshold, LOGWPL, `MEM_ICACHE) busfm(.clk, .reset, .IgnoreRequest, .LsuRWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), .LsuBusAck(IfuBusAck), diff --git a/wally-pipelined/src/lsu/busfsm.sv b/wally-pipelined/src/lsu/busfsm.sv index 31dc603c..cdfe9b10 100644 --- a/wally-pipelined/src/lsu/busfsm.sv +++ b/wally-pipelined/src/lsu/busfsm.sv @@ -27,7 +27,7 @@ module busfsm #(parameter integer WordCountThreshold, - parameter integer LOGWPL) + parameter integer LOGWPL, parameter integer CacheEnabled ) (input logic clk, input logic reset, @@ -55,7 +55,8 @@ module busfsm #(parameter integer WordCountThreshold, logic CntReset; logic WordCountFlag; logic [LOGWPL-1:0] NextWordCount; - + logic UnCachedAccess; + typedef enum {STATE_BUS_READY, STATE_BUS_FETCH, @@ -81,6 +82,8 @@ module busfsm #(parameter integer WordCountThreshold, assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); assign CntEn = PreCntEn & LsuBusAck; + assign UnCachedAccess = ~CacheableM | ~CacheEnabled; + always_ff @(posedge clk) if (reset) BusCurrState <= #1 STATE_BUS_READY; else BusCurrState <= #1 BusNextState; @@ -88,8 +91,8 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(BusCurrState) STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(LsuRWM[0] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(LsuRWM[1] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_READ; + else if(LsuRWM[0] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(LsuRWM[1] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_READ; else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; @@ -113,27 +116,27 @@ module busfsm #(parameter integer WordCountThreshold, assign CntReset = BusCurrState == STATE_BUS_READY; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; - assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (LsuRWM[0])) | + assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (LsuRWM[0])) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) | + assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (|LsuRWM[1])) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & ~CacheableM)) | + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & UnCachedAccess)) | (BusCurrState == STATE_BUS_UNCACHED_READ | BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) | - ~`MEM_DCACHE; // if no dcache always select uncachedadr. + ~CacheEnabled; // if no dcache always select uncachedadr. endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index d8421f2f..160fbe8c 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -384,7 +384,7 @@ module lsu else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011; endgenerate; - busfsm #(WordCountThreshold, LOGWPL) + busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE) busfsm(.clk, .reset, .IgnoreRequest, .LsuRWM, .DCacheFetchLine, .DCacheWriteLine, .LsuBusAck, .CPUBusy, .CacheableM, .BusStall, .LsuBusWrite, .LsuBusRead, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);