From 6a8e917e06c003d3e391fdfd9245fc00576675a9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 21 Dec 2021 15:59:56 -0600
Subject: [PATCH] It was possible for a load/store followed by tlb miss and
 update to have an exception and still commit its result to memory or
 register.

---
 wally-pipelined/src/cache/dcachefsm.sv | 18 +++++++-----------
 wally-pipelined/src/lsu/lsu.sv         |  4 +++-
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index eb191b9a..f11b3c3e 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -169,7 +169,7 @@ module dcachefsm
 		end
 
 		// Flush dcache to next level of memory
-		else if(FlushDCacheM  & ~(ExceptionM | PendingInterruptM)) begin
+		else if(FlushDCacheM) begin
 		  NextState = STATE_FLUSH;
 		  DCacheStall = 1'b1;
 		  SelAdrM = 2'b11;
@@ -178,7 +178,7 @@ module dcachefsm
 		end
 		
 		// amo hit
-		else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
+		else if(AtomicM[1] & (&MemRWM) & CacheableM & CacheHit) begin
 		  SelAdrM = 2'b10;
 		  DCacheStall = 1'b0;
 		  
@@ -194,7 +194,7 @@ module dcachefsm
 		  end
 		end
 		// read hit valid cached
-		else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
+		else if(MemRWM[1] & CacheableM & CacheHit) begin
 		  DCacheStall = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  
@@ -207,7 +207,7 @@ module dcachefsm
 	      end
 		end
 		// write hit valid cached
-		else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
+		else if (MemRWM[0] & CacheableM & CacheHit) begin
 		  SelAdrM = 2'b10;
 		  DCacheStall = 1'b0;
 		  SRAMWordWriteEnableM = 1'b1;
@@ -223,29 +223,25 @@ module dcachefsm
 		  end
 		end
 		// read or write miss valid cached
-		else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit) begin
+		else if((|MemRWM) & CacheableM & ~CacheHit) begin
 		  NextState = STATE_MISS_FETCH_WDV;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		end
 		// uncached write
-		else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
+		else if(MemRWM[0] & ~CacheableM) begin
 		  NextState = STATE_UNCACHED_WRITE;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		  AHBWrite = 1'b1;
 		end
 		// uncached read
-		else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
+		else if(MemRWM[1] & ~CacheableM) begin
 		  NextState = STATE_UNCACHED_READ;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		  AHBRead = 1'b1;	  
 		end
-		// fault
-		else if(AnyCPUReqM & (ExceptionM | PendingInterruptM)) begin
-		  NextState = STATE_READY;
-		end
 		else NextState = STATE_READY;
       end
       
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 738124a9..ed7a9fcb 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -198,7 +198,9 @@ module lsu
   assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY);
   assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
 				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
-  assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
+  assign IgnoreRequest = (CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) |
+						 ((CurrState == STATE_T0_REPLAY | CurrState == STATE_T0_FAULT_REPLAY)
+						  & (ExceptionM | PendingInterruptM));
   
   assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY;