diff --git a/sim/imperas.ic b/sim/imperas.ic
index 5e3357ea..8b4ef2d4 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -1,12 +1,14 @@
 #--showoverrides
 #--help --helpall
---traceregs
 
 --override cpu/show_c_prefix=T
 --override cpu/unaligned=F
 --override cpu/ignore_non_leaf_DAU=1
 --override cpu/wfi_is_nop=T
 
+# this should be 16 not 0
+--override cpu/PMP_registers=0
+
 # Enable the Imperas instruction coverage
 #-extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
 #-override  refRoot/cpu/cv/cover=basic
@@ -32,9 +34,6 @@
 # Store simulator output to logfile
 --output imperas.log
 
---override cpu/PMP_registers=0
-#--showoverrides
-#--mpdconsole
 
 # ignore settings of bits DAU for non leaf page table walks
 --override cpu/ignore_non_leaf_DAU=1
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 6daf48e9..bfe5c4b3 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -98,6 +98,37 @@ module wallyTracer(rvviTrace rvvi);
 	if(valid) begin 
 	  // machine CSRs
 	  // *** missing PMP and performance counters.
+	
+      // PMPCFG  space is 0-15 3a0 - 3af
+	  int i, i4, i8, csrid;
+      logic [`XLEN-1:0] pmp;
+      for (i=0; i<`PMP_ENTRIES; i+=8) begin
+        i4 = i / 4;
+        i8 = (i / 8) * 8;
+        pmp = 0;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+2] << 16;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+3] << 24;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+4] << 32;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+5] << 40;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
+        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
+        
+        csrid = 12'h3A0 + i4;
+        //if (CSRArray[csrid] != pmp) $display("Info: %m pmpcfg%0d [%03X] %016X -> %016X", i4, csrid, CSRArray[csrid], pmp);
+        CSRArray[csrid] = pmp;
+      end
+
+      // PMPADDR space is 0-63 3b0 - 3ef
+      for (i=0; i<`PMP_ENTRIES; i++) begin
+        pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
+        
+        csrid = 12'h3B0 + i;
+        //if (CSRArray[csrid] != pmp) $display("Info: %m Change pmpaddr%0d [%03X] %016X -> %016X", i, csrid, CSRArray[csrid], pmp);
+        CSRArray[csrid] = pmp;
+      end
+      
 	  CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
 	  CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW;
 	  CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index 442edec2..f5ad63bc 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -27,7 +27,7 @@
 
 `include "wally-config.vh"
 
-// This is set from the commsnd line script
+// This is set from the command line script
 // `define USE_IMPERAS_DV
 
 `ifdef USE_IMPERAS_DV
@@ -121,10 +121,11 @@ module testbench;
       
     end
 
-  rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
-  wallyTracer wallyTracer(rvvi);
-
 `ifdef USE_IMPERAS_DV
+
+    rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
+    wallyTracer wallyTracer(rvvi);
+
     trace2log idv_trace2log(rvvi);
     trace2cov idv_trace2cov(rvvi);
 
@@ -139,6 +140,7 @@ module testbench;
 
     int PRIV_RWX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE | RVVI_MEMORY_PRIVILEGE_EXEC;
     int PRIV_RW  = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE;
+    int PRIV_RX  = RVVI_MEMORY_PRIVILEGE_READ |                               RVVI_MEMORY_PRIVILEGE_EXEC;
     int PRIV_X   =                                                            RVVI_MEMORY_PRIVILEGE_EXEC;
 
     initial begin 
@@ -170,11 +172,12 @@ module testbench;
       // pending and taken
       void'(rvviRefCsrSetVolatile(0, 32'h344));   // MIP
       void'(rvviRefCsrSetVolatile(0, 32'h144));   // SIP
-      
+
+/*
       // Memory lo, hi, priv (RVVI_MEMORY_PRIVILEGE_{READ,WRITE,EXEC})
       void'(rvviRefMemorySetPrivilege(56'h0, 56'h7fffffffff, 0));
       if (`BOOTROM_SUPPORTED)
-          void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_X));
+          void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_RX));
       if (`UNCORE_RAM_SUPPORTED)
           void'(rvviRefMemorySetPrivilege(`UNCORE_RAM_BASE, (`UNCORE_RAM_BASE + `UNCORE_RAM_RANGE), PRIV_RWX));
       if (`EXT_MEM_SUPPORTED)
@@ -200,6 +203,7 @@ module testbench;
           void'(rvviRefMemorySetPrivilege(`SDC_BASE, (`SDC_BASE + `SDC_RANGE), PRIV_RW));
           void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE)));
       end
+*/
 
       if(`XLEN==32) begin
           void'(rvviRefCsrSetVolatile(0, 32'hC80));   // CYCLEH
@@ -210,15 +214,6 @@ module testbench;
 
       void'(rvviRefCsrSetVolatile(0, 32'h104));   // SIE - Temporary!!!!
       
-      // These should be done in the attached client
-//      // Enable the trace2log module
-//      if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin
-//        msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE));
-//      end
-//      
-//      if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin
-//        msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE));
-//      end
     end
 
     always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));