diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv
index 689806a6..f6b386f0 100644
--- a/pipelined/src/ebu/ahbinterface.sv
+++ b/pipelined/src/ebu/ahbinterface.sv
@@ -34,7 +34,7 @@
 
 `include "wally-config.vh"
 
-module ahbinterface #(parameter WRITEABLE = 0) // **** modify to use LSU/ifu parameter to control widths of buses
+module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter to control widths of buses
   (
   input logic                HCLK, HRESETn,
   
@@ -53,14 +53,16 @@ module ahbinterface #(parameter WRITEABLE = 0) // **** modify to use LSU/ifu par
   input logic                CPUBusy,
   output logic               BusStall,
   output logic               BusCommitted,
-  output logic [`XLEN-1:0]   ReadDataWord);
+  output logic [(LSU ? `XLEN : 32)-1:0]   ReadDataWord);
   
   logic                       CaptureEn;
 
   /// *** only 32 bit for IFU.
-  flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWord));
+  localparam                  LEN = (LSU ? `XLEN : 32);
+  
+  flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(ReadDataWord));
 
-  if(WRITEABLE) begin
+  if(LSU) begin
     // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN    
     flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA); 
     flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index ab84ac92..5cb27d43 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -181,8 +181,8 @@ module ifu (
   // Memory 
   ////////////////////////////////////////////////////////////////////////////////////////////////
 
-  logic [`XLEN-1:0] AllInstrRawF;
-  assign InstrRawF = AllInstrRawF[31:0];
+//  logic [`XLEN-1:0] InstrRawF;
+//  assign InstrRawF = InstrRawF[31:0];
 
   // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
   if (`IROM_SUPPORTED) begin : irom 
@@ -241,7 +241,7 @@ module ifu (
             .BusStall, .BusCommitted());
 
       mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
-        .s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
+        .s(SelUncachedAdr), .y(InstrRawF[31:0]));
     end else begin : passthrough
       assign IFUHADDR = PCPF;
       logic CaptureEn;
@@ -252,7 +252,7 @@ module ifu (
       ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), 
         .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
         .HWSTRB(), .RW, .ByteMask(), .WriteData('0),
-        .CPUBusy, .BusStall, .BusCommitted(), .ReadDataWord(AllInstrRawF[31:0]));
+        .CPUBusy, .BusStall, .BusCommitted(), .ReadDataWord(InstrRawF[31:0]));
 
       assign IFUHBURST = 3'b0;
       assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
@@ -261,7 +261,7 @@ module ifu (
   end else begin : nobus // block: bus
     assign BusStall = '0;   
     assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
-    assign AllInstrRawF = FinalInstrRawF;
+    assign InstrRawF = FinalInstrRawF;
   end
   
   assign IFUCacheBusStallF = ICacheStallF | BusStall;