From 69e531967572b27ea69d843eddedf2aff6a41c44 Mon Sep 17 00:00:00 2001
From: Noah Boorstin <nboorstin@hmc.edu>
Date: Tue, 23 Mar 2021 14:49:26 -0400
Subject: [PATCH] busybear: more progress

---
 wally-pipelined/regression/wally-busybear.do    |  2 ++
 wally-pipelined/testbench/testbench-busybear.sv | 15 +++++++++++----
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do
index b7e92ae3..71444cdb 100644
--- a/wally-pipelined/regression/wally-busybear.do
+++ b/wally-pipelined/regression/wally-busybear.do
@@ -49,6 +49,8 @@ add wave -hex /testbench_busybear/dut/hart/ifu/PCD
 add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
 add wave -hex /testbench_busybear/dut/hart/ifu/StallD
 add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
+add wave -hex /testbench_busybear/dut/hart/ifu/StallE
+add wave -hex /testbench_busybear/dut/hart/ifu/FlushE
 add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
 add wave /testbench_busybear/CheckInstrD
 add wave /testbench_busybear/lastCheckInstrD
diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index 385c45d5..254e672d 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -192,7 +192,7 @@ module testbench_busybear();
 
   always @(dut.HRDATA) begin
     #1;
-    if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin
+    if (dut.hart.MemRWM[1] && HADDR[31:3] != dut.PCF[31:3] && dut.HRDATA !== {64{1'bx}}) begin
       //$display("%0t", $time);
       if($feof(data_file_memR)) begin
         $display("no more memR data to read");
@@ -335,6 +335,13 @@ module testbench_busybear();
   `CHECK_CSR2(STVAL, `CSRS)
   `CHECK_CSR(STVEC)
 
+  initial begin //this is just fun to make causes easier to understand
+    #38;
+    force dut.hart.priv.csr.genblk1.csrm.NextCauseM = 0;
+    #16;
+    release dut.hart.priv.csr.genblk1.csrm.NextCauseM;
+  end
+
   initial begin //this is temporary until the bug can be fixed!!!
     #18909760;
     force dut.hart.ieu.dp.regf.rf[5] = 64'h0000000080000004;
@@ -382,10 +389,10 @@ module testbench_busybear();
   logic [31:0] InstrMask;
   logic forcedInstr;
   logic [63:0] lastPCD;
-  always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset) begin
+  always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin
     if(~HWRITE) begin
-      #3;
-      if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0) begin
+      #2;
+      if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin
         if (dut.hart.ifu.PCD !== lastPCD) begin
           lastCheckInstrD = CheckInstrD;
           lastPC <= dut.hart.ifu.PCD;