From 69be6d08738013adbd5b53e63a5dcd9326b56eb2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Aug 2022 11:16:36 -0700 Subject: [PATCH] Simplify IEU-FP datapath --- pipelined/src/ieu/datapath.sv | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 73e9e94e..57150131 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -87,8 +87,8 @@ module datapath ( // Writeback stage signals logic [`XLEN-1:0] SCResultW; logic [`XLEN-1:0] ResultW; - logic [`XLEN-1:0] IFResultW; - + logic [`XLEN-1:0] IFResultW, IFCvtResultW; + // Decode stage assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; @@ -123,16 +123,14 @@ module datapath ( flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW); flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW); - // floating point interactions: fcvt, fp stores + // floating point inputs: FIntResM comes from fclass, fcmp, fmv; FCvtIntResW comes from fcvt if (`F_SUPPORTED) begin:fpmux - logic [`XLEN-1:0] IFCvtResultW; mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW); - mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); end else begin:fpmux - assign IFResultM = IEUResultM; - mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); + assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW; end + mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); // handle Store Conditional result if atomic extension supported if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};