diff --git a/synthDC/madzscript.py b/synthDC/madzscript.py
new file mode 100755
index 00000000..83295df1
--- /dev/null
+++ b/synthDC/madzscript.py
@@ -0,0 +1,36 @@
+#!/usr/bin/python3
+# from msilib.schema import File
+import subprocess
+
+
+
+bashCommand = "find . | grep ppa_timing.rep"
+output = subprocess.check_output(['bash','-c', bashCommand])
+files = output.decode("utf-8").split('\n')
+print(files)
+
+widths = []
+areas = []
+delays = []
+
+for file in files:
+    widths += [pullNum('ports', file)/3]
+    areas += [pullNum('Total cell area', file)]
+    delays += [pullNum('delay', file)]
+
+
+def pullNum(keyText, file):
+    return
+
+# File_object = open("greppedareas","r")
+# content = File_object.readlines()
+# File_object.close()
+
+# LoT = []
+# for line in content:
+#     l = line.split(':')
+#     LoT += [float(l[2])]
+
+# avg = sum(LoT)/len(LoT)
+
+# print(avg)
\ No newline at end of file
diff --git a/synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/synth.out b/synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/synth.out
new file mode 100644
index 00000000..39f411ce
--- /dev/null
+++ b/synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/synth.out
@@ -0,0 +1,998 @@
+
+                           Design Compiler Graphical 
+                                 DC Ultra (TM)
+                                  DFTMAX (TM)
+                              Power Compiler (TM)
+                                 DesignWare (R)
+                                 DC Expert (TM)
+                               Design Vision (TM)
+                               HDL Compiler (TM)
+                               VHDL Compiler (TM)
+                                  DFT Compiler
+                               Design Compiler(R)
+
+               Version S-2021.06-SP4 for linux64 - Nov 23, 2021 
+
+                    Copyright (c) 1988 - 2021 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+   or distribution of this software is strictly prohibited.  Licensed Products
+     communicate with Synopsys servers for the purpose of providing software
+    updates, detecting software piracy and verifying that customers are using
+    Licensed Products in conformity with the applicable License Key for such
+  Licensed Products. Synopsys will use information gathered in connection with
+    this process to deliver software updates and pursue software pirates and
+                                   infringers.
+
+ Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
+            Inclusivity and Diversity" (Refer to article 000036315 at
+                        https://solvnetplus.synopsys.com)
+Initializing...
+#
+# Synthesis Synopsys Flow
+# james.stine@okstate.edu 27 Sep 2015
+#
+# Ignore unnecessary warnings:
+# intraassignment delays for nonblocking assignments are ignored
+suppress_message {VER-130} 
+# statements in initial blocks are ignored
+suppress_message {VER-281} 
+suppress_message {VER-173} 
+# Enable Multicore
+set_host_options -max_cores $::env(MAXCORES)
+1
+# get outputDir from environment (Makefile)
+set outputDir $::env(OUTPUTDIR)
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b
+set cfgName $::env(CONFIG)
+rv32e
+# Config
+set hdl_src "../pipelined/src"
+../pipelined/src
+set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
+../pipelined/src/../config/rv32e/wally-config.vh
+set saifpower $::env(SAIFPOWER)
+0
+set maxopt $::env(MAXOPT)
+0
+eval file copy -force ${cfg} {hdl/}
+eval file copy -force ${cfg} $outputDir
+eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
+eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
+eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
+# Enables name mapping
+if { $saifpower == 1 } {
+    saif_map -start
+}
+# Verilog files
+set my_verilog_files [glob hdl/*]
+hdl/gpio.sv hdl/cla64.sv hdl/cvtfp.sv hdl/flopenrc.sv hdl/csrm.sv hdl/adrdec.sv hdl/fpdiv.sv hdl/convert_inputs.sv hdl/forward.sv hdl/fpdiv_pipe.sv hdl/flopenl.sv hdl/unpacking.sv hdl/tlbcontrol.sv hdl/bpred.sv hdl/pmachecker.sv hdl/satCounter2.sv hdl/csr.sv hdl/fsm_fpdiv_pipe.sv hdl/prioritythermometer.sv hdl/mmu.sv hdl/csrn.sv hdl/ahblite.sv hdl/wally-config.vh hdl/wally-shared.vh hdl/cachereplacementpolicy.sv hdl/privileged.sv hdl/tlbmixer.sv hdl/privdec.sv hdl/or_rows.sv hdl/fctrl.sv hdl/sram1p1rw.sv hdl/unpack.sv hdl/decompress.sv hdl/extend.sv hdl/wally-constants.vh hdl/muldiv.sv hdl/tlbcamline.sv hdl/tlbramline.sv hdl/fcvtint.sv hdl/fcvtfp.sv hdl/regfile.sv hdl/sbtm_a0.sv hdl/subwordwrite.sv hdl/flopen.sv hdl/alu.sv hdl/cla12.sv hdl/dtim.sv hdl/csrsr.sv hdl/datapath.sv hdl/mux.sv hdl/adderparts.sv hdl/sbtm_a1.sv hdl/simpleram.sv hdl/sbtm_a3.sv hdl/busfsm.sv hdl/cachefsm.sv hdl/floprc.sv hdl/ieu.sv hdl/wallypipelinedcore.sv hdl/fsm_fpdiv.sv hdl/pmpadrdec.sv hdl/rounder_denorm.sv hdl/uncore.sv hdl/localHistoryPredictor.sv hdl/mul.sv hdl/clint.sv hdl/divconv_pipe.sv hdl/adder.sv hdl/tlb.sv hdl/uart.sv hdl/twoBitPredictor.sv hdl/sbtm_a2.sv hdl/csri.sv hdl/cacheway.sv hdl/amoalu.sv hdl/plic.sv hdl/interlockfsm.sv hdl/hptw.sv hdl/RAsPredictor.sv hdl/priorityonehot.sv hdl/fpudivsqrtrecur.sv hdl/synchronizer.sv hdl/faddcvt.sv hdl/fma16.sv hdl/intdivrestoringstep.sv hdl/ifu.sv hdl/redundantmul.sv hdl/pmpchecker.sv hdl/fclassify.sv hdl/tlbcam.sv hdl/fsgn.sv hdl/adrdecs.sv hdl/shifter.sv hdl/fma.sv hdl/wallypipelinedsoc.sv hdl/counter.sv hdl/rounder_div.sv hdl/trap.sv hdl/clockgater.sv hdl/SRAM2P1R1W.sv hdl/tlbram.sv hdl/neg.sv hdl/csrc.sv hdl/csru.sv hdl/lzd_denorm.sv hdl/comparator.sv hdl/fcvt.sv hdl/cla52.sv hdl/divconv.sv hdl/busdp.sv hdl/subcachelineread.sv hdl/subwordread.sv hdl/cache.sv hdl/exception_div.sv hdl/arrs.sv hdl/uartPC16550D.sv hdl/fhazard.sv hdl/fcmp.sv hdl/sbtm_div.sv hdl/decoder.sv hdl/controller.sv hdl/sbtm_sqrt.sv hdl/intdivrestoring.sv hdl/spillsupport.sv hdl/convert_inputs_div.sv hdl/swbytemask.sv hdl/flopr.sv hdl/lsuvirtmen.sv hdl/tlblru.sv hdl/onehotdecoder.sv hdl/fpudivsqrtrecurcore.sv hdl/flop.sv hdl/globalHistoryPredictor.sv hdl/fregfile.sv hdl/fpu.sv hdl/csrs.sv hdl/flopens.sv hdl/atomic.sv hdl/lsu.sv hdl/shifter_denorm.sv hdl/gsharePredictor.sv hdl/ram.sv hdl/hazard.sv hdl/BTBPredictor.sv hdl/flopenr.sv hdl/lrsc.sv hdl/exception.sv
+# Set toplevel
+set my_toplevel $::env(DESIGN)
+wallypipelinedcore
+# Set number of significant digits
+set report_default_significant_digits 6
+6
+# V(HDL) Unconnectoed Pins Output
+set verilogout_show_unconnected_pins "true"
+true
+set vhdlout_show_unconnected_pins "true"
+true
+# Due to parameterized Verilog must use analyze/elaborate and not 
+# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
+#
+define_design_lib WORK -path ./WORK
+1
+analyze -f sverilog -lib WORK $my_verilog_files
+Running PRESTO HDLC
+Compiling source file ./hdl/gpio.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/cla64.sv
+Compiling source file ./hdl/cvtfp.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/flopenrc.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/csrm.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/adrdec.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/fpdiv.sv
+Compiling source file ./hdl/convert_inputs.sv
+Compiling source file ./hdl/forward.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/fpdiv_pipe.sv
+Compiling source file ./hdl/flopenl.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/unpacking.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/tlbcontrol.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/bpred.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/pmachecker.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/satCounter2.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/csr.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/fsm_fpdiv_pipe.sv
+Compiling source file ./hdl/prioritythermometer.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/mmu.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/csrn.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/ahblite.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/cachereplacementpolicy.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/privileged.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/tlbmixer.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/privdec.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/or_rows.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/fctrl.sv
+Compiling source file ./hdl/sram1p1rw.sv
+Compiling source file ./hdl/unpack.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Compiling source file ./hdl/decompress.sv
+Opening include file ./hdl/wally-config.vh
+Opening include file ./hdl/wally-shared.vh
+Opening include file ./hdl/wally-constants.vh
+Error:  ./hdl/unpack.sv:100: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:101: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:102: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:104: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:105: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:106: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:108: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:109: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:110: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:112: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:113: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:114: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:116: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:117: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:118: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:121: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:122: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:123: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:132: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  ./hdl/unpack.sv:133: Procedural-continuous assignments are not supported by synthesis. (VER-966)
+Error:  Too many errors; can't continue. (VER-40)
+*** Presto compilation terminated with 21 errors. ***
+Loading db file '/cad/synopsys/SYN/libraries/syn/dw_foundation.sldb'
+0
+elaborate $my_toplevel -lib WORK 
+Loading db file '/cad/synopsys/SYN/libraries/syn/gtech.db'
+Loading db file '/cad/synopsys/SYN/libraries/syn/standard.sldb'
+  Loading link library 'gtech'
+Running PRESTO HDLC
+Presto compilation completed successfully. (wallypipelinedcore)
+Elaborated 1 design.
+Current design is now 'wallypipelinedcore'.
+Information: Building the design 'ifu'. (HDL-193)
+Presto compilation completed successfully. (ifu)
+Information: Building the design 'ieu'. (HDL-193)
+Presto compilation completed successfully. (ieu)
+Information: Building the design 'lsu'. (HDL-193)
+Presto compilation completed successfully. (lsu)
+Information: Building the design 'ahblite'. (HDL-193)
+Warning:  ./hdl/ahblite.sv:102: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
+
+Statistics for case statements in always block at line 101 in file
+	'./hdl/ahblite.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|           102            |    auto/auto     |
+===============================================
+Presto compilation completed successfully. (ahblite)
+Information: Building the design 'hazard'. (HDL-193)
+Presto compilation completed successfully. (hazard)
+Information: Building the design 'busdp' instantiated from design 'ifu' with
+	the parameters "1,32,1". (HDL-193)
+Presto compilation completed successfully. (busdp_WORDSPERLINE1_LINELEN32_LOGWPL1)
+Information: Building the design 'mux2' instantiated from design 'ifu' with
+	the parameters "32". (HDL-193)
+Presto compilation completed successfully. (mux2_WIDTH32)
+Information: Building the design 'flopenl' instantiated from design 'ifu' with
+	the parameters "32". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenl_WIDTH32 line 40 in file
+		'./hdl/flopenl.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenl_WIDTH32)
+Information: Building the design 'flopenrc' instantiated from design 'ifu' with
+	the parameters "32". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenrc_WIDTH32 line 39 in file
+		'./hdl/flopenrc.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenrc_WIDTH32)
+Information: Building the design 'decompress'. (HDL-193)
+Presto compilation completed successfully. (decompress)
+Information: Building the design 'flopenr' instantiated from design 'ifu' with
+	the parameters "1". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenr_WIDTH1 line 39 in file
+		'./hdl/flopenr.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenr_WIDTH1)
+Information: Building the design 'flopenr' instantiated from design 'ifu' with
+	the parameters "32". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenr_WIDTH32 line 39 in file
+		'./hdl/flopenr.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenr_WIDTH32)
+Information: Building the design 'controller'. (HDL-193)
+Warning:  ./hdl/controller.sv:145: Statement unreachable (Branch condition impossible to meet).  (VER-61)
+
+Statistics for case statements in always block at line 118 in file
+	'./hdl/controller.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|           119            |    auto/auto     |
+===============================================
+Presto compilation completed successfully. (controller)
+Information: Building the design 'datapath'. (HDL-193)
+Presto compilation completed successfully. (datapath)
+Information: Building the design 'forward'. (HDL-193)
+Presto compilation completed successfully. (forward)
+Information: Building the design 'busdp' instantiated from design 'lsu' with
+	the parameters "1,32,1,1". (HDL-193)
+Presto compilation completed successfully. (busdp_WORDSPERLINE1_LINELEN32_LOGWPL1_LSU1)
+Information: Building the design 'subwordread'. (HDL-193)
+
+Statistics for case statements in always block at line 91 in file
+	'./hdl/subwordread.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|            92            |    auto/auto     |
+===============================================
+
+Statistics for case statements in always block at line 100 in file
+	'./hdl/subwordread.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|           101            |    auto/auto     |
+===============================================
+
+Statistics for case statements in always block at line 107 in file
+	'./hdl/subwordread.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|           108            |    auto/auto     |
+===============================================
+Presto compilation completed successfully. (subwordread)
+Information: Building the design 'flopenl' instantiated from design 'ahblite' with
+	the parameters "TYPE="enum(24%array(0%1%0%logic)%4%ahblite:_Pr0QaORKb_%cons(4%IDLE%00%cons(4%MEMREAD%01%cons(4%MEMWRITE%10%cons(4%INSTRREAD%11%null)))))%FpfRxH&"". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenl_370242 line 40 in file
+		'./hdl/flopenl.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenl_370242)
+Information: Building the design 'flop' instantiated from design 'ahblite' with
+	the parameters "32". (HDL-193)
+
+Inferred memory devices in process
+	in routine flop_WIDTH32 line 39 in file
+		'./hdl/flop.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flop_WIDTH32)
+Information: Building the design 'flop' instantiated from design 'ahblite' with
+	the parameters "3". (HDL-193)
+
+Inferred memory devices in process
+	in routine flop_WIDTH3 line 39 in file
+		'./hdl/flop.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flop_WIDTH3)
+Information: Building the design 'flop' instantiated from design 'ahblite' with
+	the parameters "4". (HDL-193)
+
+Inferred memory devices in process
+	in routine flop_WIDTH4 line 39 in file
+		'./hdl/flop.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flop_WIDTH4)
+Information: Building the design 'flop' instantiated from design 'ahblite' with
+	the parameters "1". (HDL-193)
+
+Inferred memory devices in process
+	in routine flop_WIDTH1 line 39 in file
+		'./hdl/flop.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flop_WIDTH1)
+Information: Building the design 'flopen' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
+	the parameters "32". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopen_WIDTH32 line 39 in file
+		'./hdl/flopen.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopen_WIDTH32)
+Information: Building the design 'mux2' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
+	the parameters "34". (HDL-193)
+Presto compilation completed successfully. (mux2_WIDTH34)
+Information: Building the design 'mux2' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
+	the parameters "3". (HDL-193)
+Presto compilation completed successfully. (mux2_WIDTH3)
+Information: Building the design 'busfsm' instantiated from design 'busdp_WORDSPERLINE1_LINELEN32_LOGWPL1' with
+	the parameters "0,1,1'h0". (HDL-193)
+Warning:  ./hdl/busfsm.sv:98: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
+
+Statistics for case statements in always block at line 97 in file
+	'./hdl/busfsm.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|            98            |    auto/auto     |
+===============================================
+
+Inferred memory devices in process
+	in routine busfsm_0_1_0 line 93 in file
+		'./hdl/busfsm.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|  BusCurrState_reg   | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (busfsm_0_1_0)
+Information: Building the design 'flopenrc' instantiated from design 'controller' with
+	the parameters "1". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenrc_WIDTH1 line 39 in file
+		'./hdl/flopenrc.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenrc_WIDTH1)
+Information: Building the design 'flopenrc' instantiated from design 'controller' with
+	the parameters "27". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenrc_WIDTH27 line 39 in file
+		'./hdl/flopenrc.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenrc_WIDTH27)
+Information: Building the design 'mux4' instantiated from design 'controller' with
+	the parameters "1". (HDL-193)
+Presto compilation completed successfully. (mux4_WIDTH1)
+Information: Building the design 'flopenrc' instantiated from design 'controller' with
+	the parameters "18". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenrc_WIDTH18 line 39 in file
+		'./hdl/flopenrc.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |  18   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenrc_WIDTH18)
+Information: Building the design 'flopenrc' instantiated from design 'controller' with
+	the parameters "4". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenrc_WIDTH4 line 39 in file
+		'./hdl/flopenrc.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenrc_WIDTH4)
+Information: Building the design 'regfile'. (HDL-193)
+
+Inferred memory devices in process
+	in routine regfile line 54 in file
+		'./hdl/regfile.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|       rf_reg        | Flip-flop |  480  |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Statistics for MUX_OPs
+======================================================
+| block name/line  | Inputs | Outputs | # sel inputs |
+======================================================
+|    regfile/58    |   16   |   32    |      4       |
+|    regfile/59    |   16   |   32    |      4       |
+======================================================
+Presto compilation completed successfully. (regfile)
+Information: Building the design 'extend'. (HDL-193)
+
+Statistics for case statements in always block at line 40 in file
+	'./hdl/extend.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|            41            |    auto/auto     |
+===============================================
+Presto compilation completed successfully. (extend)
+Information: Building the design 'flopenrc' instantiated from design 'datapath' with
+	the parameters "5". (HDL-193)
+
+Inferred memory devices in process
+	in routine flopenrc_WIDTH5 line 39 in file
+		'./hdl/flopenrc.sv'.
+===============================================================================
+|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
+===============================================================================
+|        q_reg        | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
+===============================================================================
+Presto compilation completed successfully. (flopenrc_WIDTH5)
+Information: Building the design 'mux3' instantiated from design 'datapath' with
+	the parameters "32". (HDL-193)
+Presto compilation completed successfully. (mux3_WIDTH32)
+Information: Building the design 'comparator' instantiated from design 'datapath' with
+	the parameters "32". (HDL-193)
+Presto compilation completed successfully. (comparator_WIDTH32)
+Information: Building the design 'alu' instantiated from design 'datapath' with
+	the parameters "32". (HDL-193)
+
+Statistics for case statements in always block at line 74 in file
+	'./hdl/alu.sv'
+===============================================
+|           Line           |  full/ parallel  |
+===============================================
+|            75            |    auto/auto     |
+===============================================
+Presto compilation completed successfully. (alu_WIDTH32)
+Information: Building the design 'mux5' instantiated from design 'datapath' with
+	the parameters "32". (HDL-193)
+Presto compilation completed successfully. (mux5_WIDTH32)
+Information: Building the design 'shifter'. (HDL-193)
+Presto compilation completed successfully. (shifter)
+1
+# Set the current_design 
+current_design $my_toplevel
+Current design is 'wallypipelinedcore'.
+{wallypipelinedcore}
+link
+
+  Linking design 'wallypipelinedcore'
+  Using the following designs and libraries:
+  --------------------------------------------------------------------------
+  dw_foundation.sldb (library) /cad/synopsys/SYN/libraries/syn/dw_foundation.sldb
+
+1
+# Reset all constraints 
+reset_design
+1
+# Power Dissipation Analysis
+######### OPTIONAL !!!!!!!!!!!!!!!!
+if { $saifpower == 1 } {
+    read_saif -input power.saif -instance_name testbench/dut/core -auto_map_names -verbose
+}
+# Set reset false path
+set_false_path -from [get_ports reset]
+1
+# Set Frequency in [MHz] or period in [ns]
+set my_clock_pin clk
+clk
+set my_uncertainty 0.0
+0.0
+set my_clk_freq_MHz $::env(FREQ)
+500
+set my_period [expr 1000.0 / $my_clk_freq_MHz]
+2.0
+# Create clock object 
+set find_clock [ find port [list $my_clock_pin] ]
+{clk}
+if {  $find_clock != [list] } {
+    echo "Found clock!"
+    set my_clk $my_clock_pin
+    create_clock -period $my_period $my_clk
+    set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
+} else {
+    echo "Did not find clock! Design is probably combinational!"
+    set my_clk vclk
+    create_clock -period $my_period -name $my_clk
+}
+Found clock!
+1
+# Optimize paths that are close to critical
+set_critical_range [expr $my_period*0.05] $current_design
+1
+# Partitioning - flatten or hierarchically synthesize
+if { $maxopt == 1 } {
+    ungroup -all -flatten -simple_names
+}
+# Set input pins except clock
+set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
+{reset TimerIntM ExtIntM SwIntM MTIME_CLINT[63] MTIME_CLINT[62] MTIME_CLINT[61] MTIME_CLINT[60] MTIME_CLINT[59] MTIME_CLINT[58] MTIME_CLINT[57] MTIME_CLINT[56] MTIME_CLINT[55] MTIME_CLINT[54] MTIME_CLINT[53] MTIME_CLINT[52] MTIME_CLINT[51] MTIME_CLINT[50] MTIME_CLINT[49] MTIME_CLINT[48] MTIME_CLINT[47] MTIME_CLINT[46] MTIME_CLINT[45] MTIME_CLINT[44] MTIME_CLINT[43] MTIME_CLINT[42] MTIME_CLINT[41] MTIME_CLINT[40] MTIME_CLINT[39] MTIME_CLINT[38] MTIME_CLINT[37] MTIME_CLINT[36] MTIME_CLINT[35] MTIME_CLINT[34] MTIME_CLINT[33] MTIME_CLINT[32] MTIME_CLINT[31] MTIME_CLINT[30] MTIME_CLINT[29] MTIME_CLINT[28] MTIME_CLINT[27] MTIME_CLINT[26] MTIME_CLINT[25] MTIME_CLINT[24] MTIME_CLINT[23] MTIME_CLINT[22] MTIME_CLINT[21] MTIME_CLINT[20] MTIME_CLINT[19] MTIME_CLINT[18] MTIME_CLINT[17] MTIME_CLINT[16] MTIME_CLINT[15] MTIME_CLINT[14] MTIME_CLINT[13] MTIME_CLINT[12] MTIME_CLINT[11] MTIME_CLINT[10] MTIME_CLINT[9] MTIME_CLINT[8] MTIME_CLINT[7] MTIME_CLINT[6] MTIME_CLINT[5] MTIME_CLINT[4] MTIME_CLINT[3] MTIME_CLINT[2] MTIME_CLINT[1] MTIME_CLINT[0] HRDATA[31] HRDATA[30] HRDATA[29] HRDATA[28] HRDATA[27] HRDATA[26] HRDATA[25] HRDATA[24] HRDATA[23] HRDATA[22] HRDATA[21] HRDATA[20] HRDATA[19] HRDATA[18] HRDATA[17] HRDATA[16] HRDATA[15] HRDATA[14] HRDATA[13] HRDATA[12] HRDATA[11] HRDATA[10] HRDATA[9] HRDATA[8] HRDATA[7] HRDATA[6] HRDATA[5] HRDATA[4] HRDATA[3] HRDATA[2] HRDATA[1] HRDATA[0] ...}
+# Specifies delays be propagated through the clock network
+# This is getting optimized poorly in the current flow, causing a lot of clock skew 
+# and unrealistic bad timing results.
+# set_propagated_clock [get_clocks $my_clk]
+# Setting constraints on input ports 
+if {$tech == "sky130"} {
+    set_driving_cell  -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
+} elseif {$tech == "sky90"} {
+    set_driving_cell  -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
+}
+# Set input/output delay
+set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk
+1
+set_output_delay 0.1 -max -clock $my_clk [all_outputs]
+1
+# Setting load constraint on output ports 
+if {$tech == "sky130"} {
+    set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
+} elseif {$tech == "sky90"} {
+    set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
+}
+# Set the wire load model 
+set_wire_load_mode "top"
+1
+# Attempt Area Recovery - if looking for minimal area
+# set_max_area 2000
+# Set fanout
+set_max_fanout 6 $all_in_ex_clk
+1
+# Fix hold time violations (DH: this doesn't seem to be working right now)
+#set_fix_hold [all_clocks]
+# Deal with constants and buffers to isolate ports
+set_fix_multiple_port_nets -all -buffer_constants
+1
+# setting up the group paths to find out the required timings
+# group_path -name OUTPUTS -to [all_outputs]
+# group_path -name INPUTS -from [all_inputs] 
+# group_path -name COMBO -from [all_inputs] -to [all_outputs]
+# Save Unmapped Design
+#set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"]
+#write_file -format ddc -hierarchy -o $filename
+# Compile statements
+if { $maxopt == 1 } {
+    compile_ultra -retime
+    optimize_registers
+} else {
+    compile_ultra -no_seq_output_inversion -no_boundary_optimization
+}
+Information: Auto ungrouping of the design is disabled because the '-no_boundary_optimization' is used. (OPT-1316)
+Warning: The value of variable 'compile_preserve_subdesign_interfaces' has been changed to true because '-no_boundary_optimization' is used. (OPT-133)
+Information: Starting from 2013.12 release, constant propagation is enabled even when boundary optimization is disabled. (OPT-1318)
+Information: Performing power optimization. (PWR-850)
+Error: No target library found. (OPT-1312)
+0
+# Eliminate need for assign statements (yuck!)
+set verilogout_no_tri true
+true
+set verilogout_equation false
+false
+# setting to generate output files
+set write_v    1        ;# generates structual netlist
+1
+set write_sdc  1	;# generates synopsys design constraint file for p&r
+1
+set write_ddc  1	;# compiler file in ddc format
+1
+set write_sdf  1	;# sdf file for backannotated timing sim
+1
+set write_pow  1 	;# genrates estimated power report
+1
+set write_rep  1	;# generates estimated area and timing report
+1
+set write_cst  1        ;# generate report of constraints
+1
+set write_hier 1        ;# generate hierarchy report
+1
+# Report Constraint Violators
+set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint_all_violators.rpt"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint_all_violators.rpt
+redirect $filename {report_constraint -all_violators}
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint_all_violators.rpt" (CMD-015)
+# Check design
+redirect $outputDir/reports/check_design.rpt { check_design }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/check_design.rpt" (CMD-015)
+# Report Final Netlist (Hierarchical)
+set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sv
+write_file -f verilog -hierarchy -output $filename
+Error: Can't open export file '/home/mmasser-frye/riscv-wally/synthDC/runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sv'. (EXPT-4)
+Error: Write command failed. (UID-25)
+0
+set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdc
+write_sdc $filename
+Error: Cannot write the 'runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdc' script file. (UID-270)
+0
+set filename [format "%s%s%s%s" $outputDir  "/mapped/" $my_toplevel ".ddc"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.ddc
+write_file -format ddc -hierarchy -o $filename
+Error: Unable to open DDC file 'runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.ddc' for writing. (DDC-1)
+Error: Write command failed. (UID-25)
+0
+set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdf
+write_sdf $filename
+Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
+Error: Cannot write the '/home/mmasser-frye/riscv-wally/synthDC/runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/mapped/wallypipelinedcore.sdf' file. (UID-29)
+0
+# QoR
+set filename [format "%s%s%s%s"  $outputDir "/reports/" $my_toplevel "_qor.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_qor.rep
+redirect $filename { report_qor }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_qor.rep" (CMD-015)
+# Report Timing
+set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_reportpath.rep
+#redirect $filename { report_path_group }
+set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_report_clock.rep
+# redirect $filename { report_clock }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_timing.rep
+redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mindelay.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mindelay.rep
+redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mindelay.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_per_module_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/*} -nworst 1 } 
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through lsu ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/*} -nworst 1 } 
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through ebu (ahblite) ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ebu/*} -nworst 1 } 
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through mdu ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } 
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through hzu ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {hzu/*} -nworst 1 } 
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through priv ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/*} -nworst 1 } 
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_per_module_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mdu_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through redundant multiplier ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/bigmul/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through ProdM (mul output) ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.ProdM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through PP0E (mul partial product) ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/PP0E} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through divide unit ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through QuotM (div output) ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.QuotM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through RemM (div output) ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.RemM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through div/WNextE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/WNextE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through div/XQNextE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/XQNextE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mdu_timing.rep" (CMD-015)
+# set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_fpu_timing.rep"]
+# redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
+# redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
+# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_ifu_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ifu_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_stall_flush_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_stall_flush_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_ieu_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_ieu_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_fpu_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through FMAResM ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through FDivResM ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through FResE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through fma/SumE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through fma/ProdExpE ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_fpu_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mmu_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_mmu_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_priv_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep
+redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
+redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_priv_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_min_timing.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_min_timing.rep
+redirect $filename { report_timing -delay min }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_min_timing.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_area.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_area.rep
+redirect $filename { report_area -hierarchy -nosplit -physical -designware}
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_area.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_cell.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_cell.rep
+# redirect $filename { report_cell [get_cells -hier *] }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_power.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_power.rep
+redirect $filename { report_power -hierarchy -levels 1 }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_power.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_constraint.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint.rep
+redirect $filename { report_constraint }
+Error: could not open output redirect file "runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_constraint.rep" (CMD-015)
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_hier.rep"]
+runs/wallypipelinedcore_rv32e_sky90 nm_500_MHz_2022-03-22-20-43_2947df5b/reports/wallypipelinedcore_hier.rep
+# redirect $filename { report_hierarchy }
+quit 
+
+Memory usage for this session 101 Mbytes.
+Memory usage for this session including child processes 101 Mbytes.
+CPU usage for this session 7 seconds ( 0.00 hours ).
+Elapsed time for this session 9 seconds ( 0.00 hours ).
+
+Thank you...
diff --git a/synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/wally-config.vh b/synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/wally-config.vh
new file mode 100644
index 00000000..ccbcb728
--- /dev/null
+++ b/synthDC/nm_500_MHz_2022-03-22-20-43_2947df5b/wally-config.vh
@@ -0,0 +1,135 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// E
+`define MISA (32'h00000010) 
+`define ZICSR_SUPPORTED 0
+`define ZIFENCEI_SUPPORTED 0
+`define COUNTERS 0
+`define ZICOUNTERS_SUPPORTED 0
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+// *** replace with MEM_BUS
+`define DMEM `MEM_NONE
+`define IMEM `MEM_NONE
+`define DBUS 1
+`define IBUS 1
+`define VIRTMEM_SUPPORTED 0
+`define VECTORED_INTERRUPTS_SUPPORTED 0 
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 0
+`define DTLB_ENTRIES 0
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 256
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 256
+
+// Integer Divider Configuration
+// DIV_BITSPERCYCLE must be 1, 2, or 4
+`define DIV_BITSPERCYCLE 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 0
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       34'h80000000
+`define RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b0
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b0
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b0
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b0
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10 
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
+`define BPRED_ENABLED 0
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+
+`define REPLAY 0
+`define HPTW_WRITES_SUPPORTED 0