diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 6248d3a3..19b46a0b 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -90,7 +90,7 @@ module ifu (
   logic                        BranchMisalignedFaultE;
   logic                        IllegalCompInstrD;
   logic [`XLEN-1:0]            PCPlus2or4F, PCLinkD;
-  logic [`XLEN-1:2]            PCPlusUpperF;
+  logic [`XLEN-1:2]            PCPlus4F;
   logic                        CompressedF;
   logic [31:0]                 InstrRawD, InstrRawF, IROMInstrF, ICacheInstrF;
   logic [31:0]                 FinalInstrRawF;
@@ -131,7 +131,7 @@ module ifu (
 
   if(`C_SUPPORTED) begin : SpillSupport
 
-    spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM), .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRawF),
+    spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF),
       .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
       .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpillSupport
@@ -295,13 +295,13 @@ module ifu (
 
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
-  assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC
+  assign PCPlus4F = PCF[`XLEN-1:2] + 1; // add 4 to PC
   // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
   // Speeds up critical path as compared to selecting adder input based on CompressedF
-  // *** consider gating PCPlusUpperF to provide the reset.
+  // *** consider gating PCPlus4F to provide the reset.
   assign PCPlus2or4F[0] = '0;
   assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]);
-  assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF;
+  assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlus4F;
 /* -----\/----- EXCLUDED -----\/-----
   assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0];
  -----/\----- EXCLUDED -----/\----- */
@@ -313,9 +313,9 @@ module ifu (
   always_comb
     if(reset) PCPlus2or4F = '0;
     else if (CompressedF) // add 2
-      if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00}; 
+      if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; 
       else        PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
-    else          PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
+    else          PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
  -----/\----- EXCLUDED -----/\----- */
 
 
diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv
index 8c8c2ead..55de81f4 100644
--- a/pipelined/src/ifu/spillsupport.sv
+++ b/pipelined/src/ifu/spillsupport.sv
@@ -37,7 +37,7 @@ module spillsupport #(parameter CACHE_ENABLED)
    input logic              reset,
    input logic              StallF, Flush,
    input logic [`XLEN-1:0]  PCF,
-   input logic [`XLEN-1:2]  PCPlusUpperF,
+   input logic [`XLEN-1:2]  PCPlus4F,
    input logic [`XLEN-1:0]  PCNextF,
    input logic [31:0]       InstrRawF,
    input logic              IFUCacheBusStallF,
@@ -60,7 +60,7 @@ module spillsupport #(parameter CACHE_ENABLED)
   (* mark_debug = "true" *)  statetype CurrState, NextState;
 
   // compute PCF+2
-  mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
+  mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
   // select between PCNextF and PCF+2
   mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill));
   // select between PCF and PCF+2