From f458deaf00f5a1c21c17a5cff49b61966274a8db Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Tue, 28 Jun 2022 02:23:29 +0000 Subject: [PATCH 1/5] make clean rm extra files --- synthDC/Makefile | 6 ++++-- synthDC/runAllSynths.sh | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 53faa452..611dcfef 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -5,8 +5,8 @@ NAME := synth # defaults export DESIGN ?= wallypipelinedcore -export FREQ ?= 4000 -export CONFIG ?= rv64gc +export FREQ ?= 3402 +export CONFIG ?= rv32e # sky130 and sky90 presently supported export TECH ?= tsmc28 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient @@ -126,6 +126,8 @@ clean: rm -f command.log rm -f filenames*.log rm -f power.saif + rm -f Synopsys_stack_trace_*.txt + rm -f crte_*.txt diff --git a/synthDC/runAllSynths.sh b/synthDC/runAllSynths.sh index 1b81a6cd..6944552d 100755 --- a/synthDC/runAllSynths.sh +++ b/synthDC/runAllSynths.sh @@ -1,5 +1,6 @@ #!/usr/bin/bash +make clean mv runs runArchive/$(date +"%Y_%m_%d_%I_%M_%p") mv newRuns runs mkdir newRuns From aa253748fc08992e1aa984d5d18bb4e36a73a48d Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Tue, 28 Jun 2022 02:28:13 +0000 Subject: [PATCH 2/5] update wally synth analysis --- synthDC/extractSummary.py | 49 ++++++++++++++++++++++----------------- synthDC/wallySynth.py | 12 ++++++---- 2 files changed, 35 insertions(+), 26 deletions(-) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 4469d4be..a2f6a9b5 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -7,6 +7,7 @@ import subprocess from matplotlib.cbook import flatten import matplotlib.pyplot as plt import matplotlib.lines as lines +from wallySynth import testFreq def synthsintocsv(): @@ -26,7 +27,7 @@ def synthsintocsv(): writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area']) for oneSynth in allSynths: - descrip = specReg.findall(oneSynth) + descrip = specReg.findall(oneSynth) #[30:] width = descrip[2][:4] config = descrip[2][4:] if descrip[3][-2:] == 'nm': @@ -46,7 +47,7 @@ def synthsintocsv(): nums = [float(m) for m in nums] metrics += nums except: - print(config + tech + freq + " doesn't have reports") + print(width + config + tech + '_' + freq + " doesn't have reports") if metrics == []: pass else: @@ -56,7 +57,7 @@ def synthsintocsv(): file.close() def synthsfromcsv(filename): - Synth = namedtuple("Synth", " width config special tech freq delay area") + Synth = namedtuple("Synth", "width config special tech freq delay area") with open(filename, newline='') as csvfile: csvreader = csv.reader(csvfile) global allSynths @@ -110,23 +111,26 @@ def freqPlot(tech, width, config): plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png') # plt.show() -def areaDelay(width, tech, freq, config=None, special=None): +def areaDelay(tech, freq, width=None, config=None, special=None): delays, areas, labels = ([] for i in range(3)) for oneSynth in allSynths: - if (width == oneSynth.width) & (tech == oneSynth.tech) & (freq == oneSynth.freq): - if (special != None) & (oneSynth.special == special): - delays += [oneSynth.delay] - areas += [oneSynth.area] - labels += [oneSynth.config] - elif (config != None) & (oneSynth.config == config): - delays += [oneSynth.delay] - areas += [oneSynth.area] - labels += [oneSynth.special] - else: - delays += [oneSynth.delay] - areas += [oneSynth.area] - labels += [oneSynth.config + '_' + oneSynth.special] + if (width==None) or (width == oneSynth.width): + if (tech == oneSynth.tech) & (freq == oneSynth.freq): + if (special != None) & (oneSynth.special == special): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.width + oneSynth.config] + elif (config != None) & (oneSynth.config == config): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.special] + # else: + # delays += [oneSynth.delay] + # areas += [oneSynth.area] + # labels += [oneSynth.config + '_' + oneSynth.special] + if width == None: + width = '' f, (ax1) = plt.subplots(1, 1) plt.scatter(delays, areas) @@ -154,8 +158,11 @@ def areaDelay(width, tech, freq, config=None, special=None): # ending freq in 42 means fpu was turned off manually if __name__ == '__main__': - synthsintocsv() + # synthsintocsv() synthsfromcsv('Summary.csv') - freqPlot('tsmc28', 'rv64', 'gc') - areaDelay('rv32', 'tsmc28', 4200, config='gc') - areaDelay('rv32', 'tsmc28', 3042, special='') \ No newline at end of file + freqPlot('tsmc28', 'rv32', 'e') + freqPlot('sky90', 'rv32', 'e') + areaDelay('tsmc28', testFreq[1], width= 'rv64', config='gc') + areaDelay('tsmc28', testFreq[1], special='') + areaDelay('sky90', testFreq[0], width='rv64', config='gc') + areaDelay('sky90', testFreq[0], special='') \ No newline at end of file diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index bf32b6f9..99d70e81 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -8,20 +8,22 @@ def runCommand(config, tech, freq): command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT=0 MAXCORES=1".format(config, tech, freq) subprocess.Popen(command, shell=True) +testFreq = [3000, 10000] + if __name__ == '__main__': techs = ['sky90', 'tsmc28'] - bestAchieved = [750, 3000] + sweepCenter = [870, 3000] synthsToRun = [] - arr = [-8, -6, -4, -2, 0, 2, 4, 6, 8] for i in [0, 1]: tech = techs[i] - f = bestAchieved[i] - for freq in [round(f+f*x/100) for x in arr]: # rv32e freq sweep + sc = sweepCenter[i] + f = testFreq[i] + for freq in [round(sc+sc*x/100) for x in arr]: # rv32e freq sweep synthsToRun += [['rv32e', tech, freq]] - for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64i', 'rv64ic']: # configs + for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64i', 'rv64ic', 'rv32e']: # configs synthsToRun += [[config, tech, f]] for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations config = 'rv64gc_' + mod From 478a2e2a4b91e4a22865ada376758660d9c474da Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Tue, 28 Jun 2022 18:01:11 +0000 Subject: [PATCH 3/5] removed an adder out of early termination --- addins/riscv-arch-test | 2 +- pipelined/srt/srt-radix4.sv | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b2..be67c99b 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/srt/srt-radix4.sv b/pipelined/srt/srt-radix4.sv index 179fbf45..39432c9e 100644 --- a/pipelined/srt/srt-radix4.sv +++ b/pipelined/srt/srt-radix4.sv @@ -143,12 +143,13 @@ module earlytermination( logic [$clog2(`DIVLEN/2+3)-1:0] Count; logic WZero; + logic [`DIVLEN+3:0] W; - assign WZero = (WS+WC == 0)|XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE; //*** temporary - // *** rather than Counting should just be able to check if one of the two msbs of the quotent is 1 then stop??? + assign WZero = ((WS^WC)=={WS[`DIVLEN+2:0]|WC[`DIVLEN+2:0], 1'b0})|XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE; assign DivDone = (DivStickyE | WZero); assign DivStickyE = ~|Count; - assign DivNegStickyE = $signed(WS+WC) < 0; + assign W = WC+WS; + assign DivNegStickyE = W[`DIVLEN+3]; //*** is there a better way to do this??? assign EarlyTermShiftDiv2E = Count; // +1 for setup // `DIVLEN/2 to get required number of bits From 6baded9121a570b3660fd86325258dd3c6b1b5e3 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Tue, 28 Jun 2022 21:33:31 +0000 Subject: [PATCH 4/5] added rv32 double precision stores - untested --- pipelined/src/cache/cache.sv | 13 ++++++++++--- pipelined/src/cache/cacheway.sv | 11 +++++++++-- pipelined/src/fpu/fctrl.sv | 6 +++--- pipelined/src/fpu/fpu.sv | 23 ++++++++++++++++++----- pipelined/src/ieu/datapath.sv | 10 ++++++++-- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 8 +++++--- pipelined/src/lsu/subwordread.sv | 14 +++++++------- pipelined/src/wally/wallypipelinedcore.sv | 11 ++++++++--- 9 files changed, 69 insertions(+), 29 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 2374b493..d380bfc8 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -43,6 +43,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER input logic [`PA_BITS-1:0] PAdr, // physical address input logic [(`XLEN-1)/8:0] ByteMask, input logic [`XLEN-1:0] FinalWriteData, + input logic [`FLEN-1:0] FWriteDataM, + input logic FLoad2, + input logic FpLoadStoreM, output logic CacheCommitted, output logic CacheStall, // to performance counters to cpu @@ -120,7 +123,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) - CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, + CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, .FLoad2, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Invalidate(InvalidateCacheM)); @@ -159,8 +162,12 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), - .d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData)); + if (`LLEN>`XLEN) + mux3 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), + .d1({WORDSPERLINE/2{FWriteDataM}}), .d2(CacheBusWriteData), .s({SetValid,FpLoadStoreM&~SetValid}), .y(CacheWriteData)); + else + mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), + .d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData)); mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index d9a47861..ac1e26e8 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -38,6 +38,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [`PA_BITS-1:0] PAdr, input logic [LINELEN-1:0] CacheWriteData, + input logic FLoad2, input logic SetValidWay, input logic ClearValidWay, input logic SetDirtyWay, @@ -74,8 +75,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// - onehotdecoder #(LOGWPL) adrdec( - .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); + if(`LLEN>`XLEN)begin + logic [2**LOGWPL-1:0] MemPAdrDecodedtmp; + onehotdecoder #(LOGWPL) adrdec( + .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedtmp)); + assign MemPAdrDecoded = MemPAdrDecodedtmp|{MemPAdrDecodedtmp[2**LOGWPL-2:0]&{2**LOGWPL-1{FLoad2}}, 1'b0}; + end else + onehotdecoder #(LOGWPL) adrdec( + .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND assign FinalByteMask = SetValidWay ? '1 : ByteMask; // OR diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 60d26002..f6ed650a 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -33,8 +33,8 @@ module fctrl ( default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b0100111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsw - 3'b011: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsd + 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsw + 3'b011: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsd default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0; // fmadd @@ -121,7 +121,7 @@ module fctrl ( assign FmtD = 0; else if (`FPSIZES == 2)begin logic [1:0] FmtTmp; - assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; + assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0]; assign FmtD = (`FMT == FmtTmp); end else if (`FPSIZES == 3|`FPSIZES == 4) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index aba1a8f4..25b39d69 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -41,10 +41,12 @@ module fpu ( input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) input logic [1:0] STATUS_FS, // Is floating-point enabled? output logic FRegWriteM, // FP register write enable - output logic FpLoadM, // Fp load instruction? + output logic FpLoadStoreM, // Fp load instruction? + output logic FLoad2, output logic FStallD, // Stall the decode stage output logic FWriteIntE, // integer register write enables output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory + output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory output logic [`XLEN-1:0] FIntResM, // data to be written to integer register output logic [`XLEN-1:0] FCvtIntResW, // data to be written to integer register output logic [1:0] FResSelW, @@ -292,8 +294,19 @@ module fpu ( // data to be stored in memory - to IEU // - FP uses NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s - if (`FLEN>`XLEN) assign FWriteDataE = FSrcYE[`XLEN-1:0]; - else assign FWriteDataE = {{`XLEN-`FLEN{FSrcYE[`FLEN-1]}}, FSrcYE}; + if (`LLEN==`XLEN) begin + assign FWriteDataE = FSrcYE[`XLEN-1:0]; + end else begin + logic [`FLEN-1:0] FWriteDataE; + if(`FMTBITS == 2) assign FLoad2 = FmtM == `FMT; + else assign FLoad2 = FmtM; + + if (`FPSIZES==1) assign FWriteDataE = FSrcYE; + else if (`FPSIZES==2) assign FWriteDataE = FmtE ? FSrcYE : {2{FSrcYE[`LEN1-1:0]}}; + else assign FWriteDataE = FmtE == `FMT ? FSrcYE : {2{FSrcYE[`LEN1-1:0]}}; + + flopenrc #(`FLEN) EMWriteDataReg (clk, reset, FlushM, ~StallM, FWriteDataE, FWriteDataM); + end // NaN Block SrcA generate @@ -311,7 +324,7 @@ module fpu ( assign PreNVE = CmpNVE&(FOpCtrlE[2]|FWriteIntE); // select the result that may be written to the integer register - to IEU - if (`FLEN>`XLEN) + if (`FLEN>`XLEN) assign IntSrcXE = FSrcXE[`XLEN-1:0]; else assign IntSrcXE = {{`XLEN-`FLEN{FSrcXE[`FLEN-1:0]}}, FSrcXE}; @@ -356,7 +369,7 @@ module fpu ( // ||| ||| ////////////////////////////////////////////////////////////////////////////////////////// - assign FpLoadM = FResSelM[1]; + assign FpLoadStoreM = FResSelM[1]; postprocess postprocess(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .ProdExpM, .EarlyTermShiftDiv2M, .AddendStickyM, .KillProdM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .Quot, diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index b7a6a964..df711695 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -124,12 +124,18 @@ module datapath ( flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW); // floating point interactions: fcvt, fp stores - if (`F_SUPPORTED) begin:fpmux + if (`F_SUPPORTED&(`LLEN>`XLEN)) begin:fpmux + logic [`XLEN-1:0] IFCvtResultW; + mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); + assign WriteDataE = ForwardedSrcBE; + mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW); + mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); + end else if (`F_SUPPORTED) begin:fpmux logic [`XLEN-1:0] IFCvtResultW; mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW); - mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); + mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); end else begin:fpmux assign IFResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE; mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 29d07cc2..02e748f3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -227,7 +227,7 @@ module ifu ( icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0), .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), - .CacheFetchLine(ICacheFetchLine), + .CacheFetchLine(ICacheFetchLine), .FWriteDataM(), .FpLoadStoreM(), .FLoad2(), .CacheWriteLine(), .ReadDataWord(FinalInstrRawF), .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 7234a7ca..5c56b135 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -57,7 +57,9 @@ module lsu ( input logic BigEndianM, input logic sfencevmaM, // fpu - input logic FpLoadM, + input logic [`FLEN-1:0] FWriteDataM, + input logic FLoad2, + input logic FpLoadStoreM, // faults output logic LoadPageFaultM, StoreAmoPageFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM, @@ -235,7 +237,7 @@ module lsu ( .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .ByteMask(ByteMaskM), .WordCount, + .ByteMask(ByteMaskM), .WordCount, .FpLoadStoreM, .FWriteDataM, .FLoad2, .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM), @@ -269,7 +271,7 @@ module lsu ( subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM); subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), - .FpLoadM, .Funct3M(LSUFunct3M), .ReadDataM); + .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); ///////////////////////////////////////////////////////////////////////////////////////////// // MW Pipeline Register diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index 4a6d99bf..d38595d4 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -35,7 +35,7 @@ module subwordread input logic [`LLEN-1:0] ReadDataWordMuxM, input logic [2:0] LSUPAdrM, input logic [2:0] Funct3M, - input logic FpLoadM, + input logic FpLoadStoreM, output logic [`LLEN-1:0] ReadDataM ); @@ -83,16 +83,16 @@ module subwordread case(Funct3M) 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb 3'b001: if(`ZFH_SUPPORTED) - ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadM}}, HalfwordM[15:0]}; // lh/flh + ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh 3'b010: if(`F_SUPPORTED) - ReadDataM = {{`LLEN-32{WordM[31]|FpLoadM}}, WordM[31:0]}; // lw/flw + ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw else ReadDataM = {{`LLEN-32{WordM[31]}}, WordM[31:0]}; // lw 3'b011: if(`D_SUPPORTED) - ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadM}}, DblWordM[63:0]}; // ld/fld + ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld else ReadDataM = {{`LLEN-64{DblWordM[63]}}, DblWordM[63:0]}; // ld/fld 3'b100: if(`Q_SUPPORTED) - ReadDataM = FpLoadM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq + ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq else ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu 3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu @@ -122,10 +122,10 @@ module subwordread case(Funct3M) 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb 3'b001: if(`ZFH_SUPPORTED) - ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadM}}, HalfwordM[15:0]}; // lh/flh + ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh 3'b010: if(`F_SUPPORTED) - ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadM}}, ReadDataWordMuxM[31:0]}; // lw/flw + ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw else ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; // lw 3'b011: ReadDataM = ReadDataWordMuxM; // fld 3'b100: ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index b3f11680..8ef8ec18 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -92,13 +92,15 @@ module wallypipelinedcore ( logic FStallD; logic FWriteIntE; logic [`XLEN-1:0] FWriteDataE; + logic FLoad2; + logic [`FLEN-1:0] FWriteDataM; logic [`XLEN-1:0] FIntResM; logic [`XLEN-1:0] FCvtIntResW; logic FDivBusyE; logic IllegalFPUInstrD, IllegalFPUInstrE; logic FRegWriteM; logic FPUStallD; - logic FpLoadM; + logic FpLoadStoreM; logic [1:0] FResSelW; logic [4:0] SetFflagsM; @@ -253,7 +255,8 @@ module wallypipelinedcore ( .AtomicM, .TrapM, .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, - .FpLoadM, + .FpLoadStoreM, + .FWriteDataM, .FLoad2, //.DataMisalignedM(DataMisalignedM), .IEUAdrE, .IEUAdrM, .WriteDataE, .ReadDataW, .FlushDCacheM, @@ -391,10 +394,12 @@ module wallypipelinedcore ( .RdM, .RdW, // which FP register to write to (from IEU) .STATUS_FS, // is floating-point enabled? .FRegWriteM, // FP register write enable - .FpLoadM, + .FpLoadStoreM, + .FLoad2, .FStallD, // Stall the decode stage .FWriteIntE, // integer register write enable .FWriteDataE, // Data to be written to memory + .FWriteDataM, // Data to be written to memory .FIntResM, // data to be written to integer register .FCvtIntResW, // fp -> int conversion result to be stored in int register .FResSelW, // fpu result selection From 50b9b4557c923cc06d21a4b038f824f125da3596 Mon Sep 17 00:00:00 2001 From: Daniel Torres Date: Wed, 29 Jun 2022 12:23:40 -0700 Subject: [PATCH 5/5] added changes to testbench, tests and riscof for additional riscof compatability --- pipelined/testbench/testbench.sv | 6 +- pipelined/testbench/tests.vh | 119 ++++++++++----------- tests/riscof/Makefile | 32 ++++-- tests/riscof/sail_cSim/riscof_sail_cSim.py | 2 +- tests/riscof/spike/spike_rv32imc_isa.yaml | 9 +- 5 files changed, 94 insertions(+), 74 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 4a6874c4..1f4f70a0 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -68,6 +68,7 @@ logic [3:0] dummy; integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; logic DCacheFlushDone, DCacheFlushStart; + logic riscofTest; flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); @@ -174,6 +175,8 @@ logic [3:0] dummy; totalerrors = 0; testadr = 0; testadrNoBase = 0; + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests + riscofTest = tests[0] == "1"; // | tests[0] == "2"; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not // guarantee the initialized reads. For example a strcmp can read 6 byte @@ -250,8 +253,7 @@ logic [3:0] dummy; for(i=0; i config$(XLEN).ini + +build_arch: riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser - rm -rf work/rv$(XLEN)i_m - mv -f $(work_dir)/rv$(XLEN)i_m work/ + rm -rf $(arch_workdir)/rv$(XLEN)i_m + mv -f $(work_dir)/rv$(XLEN)i_m $(arch_workdir)/ + +build_wally: + riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run + rm -rf $(wally_workdir)/rv$(XLEN)i_m + mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/ + +memfile: + find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done + find $(work) -type f -name "*.elf" | grep "rv32i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done + find $(work) -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done clean: rm -f config64.ini rm -f config32.ini rm -rf $(work_dir) - rm -rf work \ No newline at end of file + rm -rf $(wally_workdir) + rm -rf $(arch_workdir) \ No newline at end of file diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 7a7d16af..b86f62b5 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -101,7 +101,7 @@ class sail_cSim(pluginTemplate): execute += self.objdump_cmd.format(elf, self.xlen, 'Ref.elf.objdump') sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") - execute += self.sail_exe[self.xlen] + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + execute += self.sail_exe[self.xlen] + ' -z268435455 --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) cov_str = ' ' for label in testentry['coverage_labels']: diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index 644e9731..5a76fd97 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV32IMFCZicsr_Zifencei + ISA: RV32IMAFCZicsr_Zifencei physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001124 + reset-val: 0x40001125 rv32: accessible: true mxl: @@ -23,7 +23,6 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x0001124, 0x0000000] + - extensions[25:0] bitmask [0x0001125, 0x0000000] wr_illegal: - - Unchanged - + - Unchanged \ No newline at end of file