From 67ef46ea92571c5427ac73d52c8d808225581602 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 16:11:39 -0600 Subject: [PATCH] Partially working byte write enables. Works for cache, but not dtim or bus only. --- pipelined/src/cache/cacheway.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 5 +++-- pipelined/src/uncore/uncore.sv | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 4a0694e7..30f42039 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -78,8 +78,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND - //assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR - assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR + assign FinalByteWEN = SetValidWay ? '1 : ByteWEN; // OR + //assign FinalByteWEN = '1;//SetValidWay ? '1 : ByteWEN; // OR ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 71cea191..1b44e803 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -253,10 +253,11 @@ module lsu ( end end - if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS. Only produces byte write enable + if(1) begin // *** always, not just with no MEM_BUS. Only produces byte write enable logic [`XLEN-1:0] ReadDataWordMaskedM; // ** there is definitely a sww bug with memory mapped i/o. check wally64priv. - assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate + //assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate + assign ReadDataWordMaskedM = '0; // AND-gate // *** consider moving this AND gate into the sww. //assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address. subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 5968898b..776850e6 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -91,7 +91,7 @@ module uncore ( assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; // subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache. - if(`DMEM == `MEM_BUS) + if(0) subwordwrite sww( .HRDATA, .HADDRD, .HSIZED,