From 30df1cdd255db54ac8e62bd7c7f60f16fb8dced8 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Sun, 14 Feb 2021 10:47:01 -0600
Subject: [PATCH 01/13] The top level of the branch predictor built and
 compiles. Does not yet function.  Missing the BTB, RAS, and direction
 prediction tables.

---
 wally-pipelined/src/ifu/bpred.sv       | 170 +++++++++++++++++++++++++
 wally-pipelined/src/ifu/satCounter2.sv |  58 +++++++++
 2 files changed, 228 insertions(+)
 create mode 100644 wally-pipelined/src/ifu/bpred.sv
 create mode 100644 wally-pipelined/src/ifu/satCounter2.sv

diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
new file mode 100644
index 00000000..69f9ef99
--- /dev/null
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -0,0 +1,170 @@
+///////////////////////////////////////////
+// bpred.sv
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 12, 2021
+// Modified: 
+//
+// Purpose: Branch prediction unit
+//          Produces a branch prediction based on branch history.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module bpred 
+  (input logic clk, reset,
+   input logic 	      StallF, StallD, StallE, FlushF, FlushD, FlushE,
+   // Fetch stage
+   // the prediction
+   input [`XLEN-1:0]  PCNextF, // *** forgot to include this one on the I/O list
+   output [`XLEN-1:0] BPPredPCF,
+   output 	      SelBPPredF,
+   input [31:0]       InstrF, // we are going to use the opcode to indicate what type instruction this is.
+   // if this is too slow we will have to predict the type of instruction.
+   // Execute state
+   // Update Predictor
+   input [`XLEN-1:0]  PCE, // The address of the currently executing instruction
+   // 1 hot encoding
+   // return, jump register, jump, branch
+   // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
+   // *** the specifics of how this is encode is subject to change.
+   input 	      PCSrcE, // AKA Branch Taken
+   // Signals required to check the branch prediction accuracy.
+   input [`XLEN-1:0]  PCTargetE, // The branch destination if the branch is taken.
+   input [`XLEN-1:0]  PCD, // The address the branch predictor took.
+   input [`XLEN-1:0]  PCLinkE, // The address following the branch instruction. (AKA Fall through address)
+   // Report branch prediction status
+   output 	      BPPredWrongE
+   );
+
+  logic 	      BTBValidF;
+  logic [1:0] 	      BPPredF, BPPredD, BPPredE, UpdateBPPredE;
+
+  logic [3:0] 	      InstrClassD, InstrClassF, InstrClassE;
+  logic [`XLEN-1:0]   BTBPredPCF, RASPCF;
+  logic 	      TargetWrongE;
+  logic 	      FallThroughWrongE;
+  logic 	      PredictionDirWrongE;
+  logic 	      PredictionPCWrongE;
+  
+
+  // Part 1 decode the instruction class.
+  // *** for now I'm skiping the compressed instructions
+  assign InstrClassF[3] = InstrF[5:0] == 7'h67 && InstrF[19:15] == 5'h01; // return
+  // This is probably too much logic. 
+  // *** This also encourages me to switch to predicting the class.
+
+  assign InstrClassF[2] = InstrF[5:0] == 7'h67 && InstrF[19:15] == 5'h01; // jump register, but not return
+  assign InstrClassF[1] = InstrF[5:0] == 7'h6F; // jump
+  assign InstrClassF[0] = InstrF[5:0] == 7'h63; // branch
+  
+  // Part 2 branch direction prediction
+
+  twoBitPredictor predictor(.LookUpPC(PCNextF),
+			    .Prediction(BPPredF),
+			    // update
+			    .UpdatePC(PCE),
+			    .UpdateEN(InstrClassE[0]),
+			    .UpdatePrediction(UpdateBPPredE));
+
+  // this predictor will have two pieces of data,
+  // 1) A direction (1 = Taken, 0 = Not Taken)
+  // 2) Any information which is necessary for the predictor to built it's next state.
+  // For a 2 bit table this is the prediction count.
+
+  assign SelBPPredF = ((InstrClassF[0] & BPPredF[1]) | 
+		       InstrClassF[3] |
+		       (InstrClassF[2]) | 
+		       InstrClassF[1]) & BTBValidF;
+
+
+  // Part 3 Branch target address prediction
+  // *** For now the BTB will house the direct and indirect targets
+
+  BTBPredictor targetPredictor(.LookUpPC(PCNextF),
+			       .TargetPC(BTBPredPCF),
+			       .Valid(BTBValidF),
+			       // update
+			       .UpdateEN(InstrClassE[2] | InstrClassE[1] | InstrClassE[0]),
+			       .UpdatePC(PCE),
+			       .UpdateTarget(PCTargetE));
+
+
+  // Part 4 RAS
+
+  RASPredictor RASPredictor(.pop(InstrClassF[3]),
+			    .popPC(RASPCF),
+			    .push(InstrClassE[3]),
+			    .pushPC(PCLinkE));
+
+  assign BPPredPCF = InstrClassF[3] ? RASPCF : BTBPredPCF;
+  
+  
+
+  // The prediction and its results need to be passed through the pipeline
+  // *** for other predictors will will be different.
+  
+  flopenrc #(2) BPPredRegD(.clk(clk),
+			   .reset(reset),
+			   .en(~StallF),
+			   .clear(FlushF),
+			   .d(BPPredF),
+			   .Q(BPPredD));
+
+  flopenrc #(2) BPPredRegE(.clk(clk),
+			   .reset(reset),
+			   .en(~StallD),
+			   .clear(FlushD),
+			   .d(BPPredD),
+			   .Q(BPPredE));
+
+  // pipeline the class
+  flopenrc #(4) InstrClassRegD(.clk(clk),
+			       .reset(reset),
+			       .en(~StallF),
+			       .clear(FlushF),
+			       .d(InstrClassF),
+			       .q(InstrClassD));
+
+  flopenr #(4) InstrClassRegE(.clk(clk),
+			      .reset(reset),
+			      .en(~StallD),
+			      .clear(flushD),
+			      .d(InstrClassD),
+			      .q(InstrClassE));
+
+  // Check the prediction makes execution.
+  assign TargetWrongE = PCTargetE != PCD;
+  assign FallThroughWrongE = PCLinkE != PCD;
+  assign PredictionDirWrongE = BPPredE ^ PCSrcE;
+  assign PredictionPCWrongE = PCSrcE ? TargetWrongE : FallThroughWrongE;
+  assign BPPredWrongE = PredictionPCWrongE | PredictionDirWrongE;
+
+  // Update predictors
+
+  satCounter2 BPDirUpdate(.BrDir(~PredictionDirWrongE),
+			  .OldState(BPPredE),
+			  .NewState(UpdateBPPredE));
+  
+  
+  
+  
+
+  
diff --git a/wally-pipelined/src/ifu/satCounter2.sv b/wally-pipelined/src/ifu/satCounter2.sv
new file mode 100644
index 00000000..91e47b04
--- /dev/null
+++ b/wally-pipelined/src/ifu/satCounter2.sv
@@ -0,0 +1,58 @@
+///////////////////////////////////////////
+// satCounter2.sv
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 13, 2021
+// Modified: 
+//
+// Purpose: 2 bit starting counter
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module satCounter2
+  (input logic BrDir,
+   input logic Decr,
+   input logic [1:0] OldState,
+   output logic [1:0] NewState
+   );
+
+  always_comb begin
+    case(OldState)
+      2'b00: begin
+	if(BrDir) NewState = 2'b01;
+	else NewState = 2'b00;
+      end
+      2'b01: begin
+	if(BrDir) NewState = 2'b10;
+	else NewState = 2'b00;
+      end
+      2'b10: begin
+	if(BrDir) NewState = 2'b11;
+	else NewState = 2'b01;
+      end
+      2'b11: begin
+	if(BrDir) NewState = 2'b11;
+	else NewState = 2'b10;
+      end
+    endcase
+  end
+
+endmodule

From 3ec1f668fc3f676f0b64e10e07a837413499cd86 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Sun, 14 Feb 2021 15:06:53 -0600
Subject: [PATCH 02/13] added branch predictor 2 bit table + SRAM model. The
 SRAM model is only approximate, but it does correctly model the read and
 write pipelined behavior.

---
 wally-pipelined/src/ifu/SramModel.sv       | 96 ++++++++++++++++++++++
 wally-pipelined/src/ifu/bpred.sv           | 10 +--
 wally-pipelined/src/ifu/twoBitPredictor.sv | 53 ++++++++++++
 3 files changed, 152 insertions(+), 7 deletions(-)
 create mode 100644 wally-pipelined/src/ifu/SramModel.sv
 create mode 100644 wally-pipelined/src/ifu/twoBitPredictor.sv

diff --git a/wally-pipelined/src/ifu/SramModel.sv b/wally-pipelined/src/ifu/SramModel.sv
new file mode 100644
index 00000000..926af02f
--- /dev/null
+++ b/wally-pipelined/src/ifu/SramModel.sv
@@ -0,0 +1,96 @@
+///////////////////////////////////////////
+// SRAM2P1R1W
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 14, 2021
+// Modified: 
+//
+// Purpose: Hacky two port SRAM model.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module SRAM2P1R1W
+  #(parameter int Depth = 10,
+    parameter int Width = 2
+    ) 
+  (input clk,
+    
+   // port 1 is read only
+   input logic [Depth-1:0]  RA1,
+   output logic [Width-1:0] RD1,
+   input logic 		    REN1,
+  
+   // port 2 is write only
+   input logic [Depth-1:0]  WA1,
+   input logic [Width-1:0]  WD1,
+   input logic 		    WEN1
+   );
+  
+  
+
+
+
+  logic [Depth-1:0] 	    RA1Q, WA1Q;
+  logic 		    WEN1Q;
+  logic [Width-1:0] 	    WD1Q;
+
+  logic [2**Depth-1:0] [Width-1:0] memory;
+  
+  
+  // SRAMs address busses are always registered first.
+
+  flopenr #(Depth) RA1Reg(.clk(clk),
+			  .reset(1'b0),
+			  .en(REN1),
+			  .d(RA1),
+			  .q(RA1Q));
+  
+
+  flopenr #(Depth) WA1Reg(.clk(clk),
+			  .reset(1'b0),
+			  .en(REN1),
+			  .d(WA1),
+			  .q(WA1Q));
+
+  flopenr #(1) WEN1Reg(.clk(clk),
+		       .reset(1'b0),
+		       .en(1'b1),
+		       .d(WEN1),
+		       .q(WEN1Q));
+  
+  flopenr #(Width) WD1Reg(.clk(clk),
+			  .reset(1'b0),
+			  .en(REN1),
+			  .d(WD1),
+			  .q(WD1Q));
+  // read port
+  assign RD1 = memory[RA1Q];
+  
+  // write port
+  always_ff @ (posedge clk) begin
+    if (WEN1Q) begin
+      memory[WA1Q] = WD1Q;
+    end
+  end
+
+endmodule  
+
+
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index 69f9ef99..e9294bac 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -91,8 +91,8 @@ module bpred
 
   assign SelBPPredF = ((InstrClassF[0] & BPPredF[1]) | 
 		       InstrClassF[3] |
-		       (InstrClassF[2]) | 
-		       InstrClassF[1]) & BTBValidF;
+		       (InstrClassF[2] & BTBValidF) | 
+		       InstrClassF[1]) ;
 
 
   // Part 3 Branch target address prediction
@@ -162,9 +162,5 @@ module bpred
   satCounter2 BPDirUpdate(.BrDir(~PredictionDirWrongE),
 			  .OldState(BPPredE),
 			  .NewState(UpdateBPPredE));
-  
-  
-  
-  
 
-  
+endmodule
diff --git a/wally-pipelined/src/ifu/twoBitPredictor.sv b/wally-pipelined/src/ifu/twoBitPredictor.sv
new file mode 100644
index 00000000..6aa8f0b1
--- /dev/null
+++ b/wally-pipelined/src/ifu/twoBitPredictor.sv
@@ -0,0 +1,53 @@
+///////////////////////////////////////////
+// twoBitPredictor.sv
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 14, 2021
+// Modified: 
+//
+// Purpose: 2 bit saturating counter predictor with parameterized table depth.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module twoBitPredictor
+  #(parameter int Depth = 10
+    )
+  (input clk,
+   input [`XLEN-1:0] LookUpPC,
+   output [1:0]      Prediction,
+   // update
+   input [`XLEN-1:0] UpdatePC,
+   input 	     UpdateEN,
+   input [1:0] 	     UpdatePrediction
+   );
+
+  SRAM2P1R1W #(Depth, 2) memory(.clk(clk),
+				.RA1(LookUpPC),
+				.RD1(PredictionMemory),
+				.REN1(1'b1),
+				.WA1(UpdatePC),
+				.WD1(UpdatePrediction),
+				.WEN1(UpdateEN));
+
+  // need to forward when updating to the same address as reading.
+  assign Prediction = (UpdatePC == LookUpPC) ? UpdatePrediction : PredictionMemory;
+  
+endmodule

From 78db3654c6b090f35fbc79e1556ae35d949215de Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Mon, 15 Feb 2021 14:51:39 -0600
Subject: [PATCH 03/13] We now have a solid rough draft of the 2 bit sat
 counter branch predictor with BTB and RAS. This is not yet tested but the
 system verilog does compile.

---
 wally-pipelined/src/ifu/BTBPredictor.sv    | 81 ++++++++++++++++++++++
 wally-pipelined/src/ifu/RAsPredictor.sv    | 75 ++++++++++++++++++++
 wally-pipelined/src/ifu/SramModel.sv       | 17 +++--
 wally-pipelined/src/ifu/bpred.sv           | 67 ++++++++++--------
 wally-pipelined/src/ifu/satCounter2.sv     |  1 -
 wally-pipelined/src/ifu/twoBitPredictor.sv | 25 +++++--
 6 files changed, 224 insertions(+), 42 deletions(-)
 create mode 100644 wally-pipelined/src/ifu/BTBPredictor.sv
 create mode 100644 wally-pipelined/src/ifu/RAsPredictor.sv

diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv
new file mode 100644
index 00000000..86ff3778
--- /dev/null
+++ b/wally-pipelined/src/ifu/BTBPredictor.sv
@@ -0,0 +1,81 @@
+///////////////////////////////////////////
+// SRAM2P1R1W
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 15, 2021
+// Modified: 
+//
+// Purpose: BTB model.  Outputs type of instruction (currently 1 hot encoded. Probably want 
+// to encode to reduce storage), valid, target PC.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module BTBPredictor
+  #(parameter int Depth = 10
+    )
+  (input  logic clk,
+   input  logic reset,
+   input  logic [`XLEN-1:0] LookUpPC,
+   output logic [`XLEN-1:0] TargetPC,
+   output logic Valid,
+   // update
+   input  logic UpdateEN,
+   input  logic [`XLEN-1:0] UpdatePC,
+   input  logic [`XLEN-1:0] UpdateTarget
+   );
+
+  localparam TotalDepth = 2 ** Depth;
+  logic [TotalDepth-1:0]    ValidBits;
+  logic [Depth-1:0] 	    LookUpPCIndex, UpdatePCIndex;
+
+  // hashing function for indexing the PC
+  // We have Depth bits to index, but XLEN bits as the input.
+  // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
+  // using compressed instructions.  XOR bit 1 with the MSB of index.
+  assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
+  assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};  
+  
+  
+  // The valid bit must be resetable.
+  always_ff @ (posedge clk) begin
+    if (reset) begin
+      ValidBits <= #1 {TotalDepth{1'b0}};
+    end else if (UpdateEN) begin
+      ValidBits[UpdatePCIndex] <= #1 1'b1;
+    end
+  end
+
+  // the BTB contains the target address.
+  // *** future version may contain the instruction class, a tag or partial tag,
+  // and other indirection branch data.
+  // Another optimization may be using a PC relative address.
+
+  SRAM2P1R1W #(Depth, `XLEN) memory(.clk(clk),
+				.RA1(LookUpPCIndex),
+				.RD1(TargetPC),
+				.REN1(1'b1),
+				.WA1(UpdatePCindex),
+				.WD1(UpdateTarget),
+				.WEN1(UpdateEN),
+				.BitWEN1({XLEN{1'b1}}));
+
+
+endmodule
diff --git a/wally-pipelined/src/ifu/RAsPredictor.sv b/wally-pipelined/src/ifu/RAsPredictor.sv
new file mode 100644
index 00000000..d985209b
--- /dev/null
+++ b/wally-pipelined/src/ifu/RAsPredictor.sv
@@ -0,0 +1,75 @@
+///////////////////////////////////////////
+// RASPredictor.sv
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 15, 2021
+// Modified: 
+//
+// Purpose: 2 bit saturating counter predictor with parameterized table depth.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module RASPredictor
+  #(parameter int StackSize = 16
+    )
+  (input logic clk,
+   input logic 		    reset,
+   input logic 		    pop,
+   output logic [`XLEN-1:0] popPC,
+   input logic 		    push,
+   input logic 		    incr,
+   input logic [`XLEN-1:0]  pushPC
+   );
+
+  logic 		    CounterEn;
+  localparam Depth = $clog2(StackSize);
+
+  logic [StackSize-1:0]     PtrD, PtrQ, PtrP1, PtrM1;
+  logic [StackSize-1:0] [`XLEN-1:0] memory;
+  
+  assign CounterEn = pop | push | incr;
+
+  assign PtrD = pop ? PtrM1 : PtrP1;
+
+  assign PtrM1 = PtrQ - 1'b1;
+  assign PtrP1 = PtrQ + 1'b1;
+  // may have to handle a push and an incr at the same time.
+  // *** what happens if jal is executing and there is a return being flushed in Decode?
+
+  flopenr #(StackSize) PTR(.clk(clk),
+			   .reset(reset),
+			   .en(CounterEn),
+			   .d(PtrD),
+			   .q(PtrQ));
+
+  always_ff @ (posedge clk) begin
+    if(push) begin
+      memory[PtrP1] <= #1 pushPC;
+    end
+  end
+
+  assign popPC = memory[PtrQ];
+  
+  
+endmodule
+
+
+
diff --git a/wally-pipelined/src/ifu/SramModel.sv b/wally-pipelined/src/ifu/SramModel.sv
index 926af02f..d715d826 100644
--- a/wally-pipelined/src/ifu/SramModel.sv
+++ b/wally-pipelined/src/ifu/SramModel.sv
@@ -41,7 +41,8 @@ module SRAM2P1R1W
    // port 2 is write only
    input logic [Depth-1:0]  WA1,
    input logic [Width-1:0]  WD1,
-   input logic 		    WEN1
+   input logic 		    WEN1,
+   input logic [Width-1:0]  BitWEN1
    );
   
   
@@ -83,13 +84,19 @@ module SRAM2P1R1W
 			  .q(WD1Q));
   // read port
   assign RD1 = memory[RA1Q];
+
+  genvar 			   index;
   
   // write port
-  always_ff @ (posedge clk) begin
-    if (WEN1Q) begin
-      memory[WA1Q] = WD1Q;
+  generate
+    for (index = 0; index < Width; index = index + 1) begin    
+      always_ff @ (posedge clk) begin
+	if (WEN1Q & BitWEN1[index]) begin
+	  memory[WA1Q][index] = WD1Q[index];
+	end
+      end
     end
-  end
+  endgenerate
 
 endmodule  
 
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index e9294bac..d1c0bfb7 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -30,40 +30,40 @@
 
 module bpred 
   (input logic clk, reset,
-   input logic 	      StallF, StallD, StallE, FlushF, FlushD, FlushE,
+   input logic 		    StallF, StallD, StallE, FlushF, FlushD, FlushE,
    // Fetch stage
    // the prediction
-   input [`XLEN-1:0]  PCNextF, // *** forgot to include this one on the I/O list
-   output [`XLEN-1:0] BPPredPCF,
-   output 	      SelBPPredF,
-   input [31:0]       InstrF, // we are going to use the opcode to indicate what type instruction this is.
+   input logic [`XLEN-1:0]  PCNextF, // *** forgot to include this one on the I/O list
+   output logic [`XLEN-1:0] BPPredPCF,
+   output logic 	    SelBPPredF,
+   input logic [31:0] 	    InstrF, // we are going to use the opcode to indicate what type instruction this is.
    // if this is too slow we will have to predict the type of instruction.
    // Execute state
    // Update Predictor
-   input [`XLEN-1:0]  PCE, // The address of the currently executing instruction
+   input logic [`XLEN-1:0]  PCE, // The address of the currently executing instruction
    // 1 hot encoding
    // return, jump register, jump, branch
    // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
    // *** the specifics of how this is encode is subject to change.
-   input 	      PCSrcE, // AKA Branch Taken
+   input logic 		    PCSrcE, // AKA Branch Taken
    // Signals required to check the branch prediction accuracy.
-   input [`XLEN-1:0]  PCTargetE, // The branch destination if the branch is taken.
-   input [`XLEN-1:0]  PCD, // The address the branch predictor took.
-   input [`XLEN-1:0]  PCLinkE, // The address following the branch instruction. (AKA Fall through address)
+   input logic [`XLEN-1:0]  PCTargetE, // The branch destination if the branch is taken.
+   input logic [`XLEN-1:0]  PCD, // The address the branch predictor took.
+   input logic [`XLEN-1:0]  PCLinkE, // The address following the branch instruction. (AKA Fall through address)
    // Report branch prediction status
-   output 	      BPPredWrongE
+   output logic 	    BPPredWrongE
    );
 
-  logic 	      BTBValidF;
-  logic [1:0] 	      BPPredF, BPPredD, BPPredE, UpdateBPPredE;
+  logic 		    BTBValidF;
+  logic [1:0] 		    BPPredF, BPPredD, BPPredE, UpdateBPPredE;
 
-  logic [3:0] 	      InstrClassD, InstrClassF, InstrClassE;
-  logic [`XLEN-1:0]   BTBPredPCF, RASPCF;
-  logic 	      TargetWrongE;
-  logic 	      FallThroughWrongE;
-  logic 	      PredictionDirWrongE;
-  logic 	      PredictionPCWrongE;
-  
+  logic [3:0] 		    InstrClassD, InstrClassF, InstrClassE;
+  logic [`XLEN-1:0] 	    BTBPredPCF, RASPCF;
+  logic 		    TargetWrongE;
+  logic 		    FallThroughWrongE;
+  logic 		    PredictionDirWrongE;
+  logic 		    PredictionPCWrongE;
+  logic [`XLEN-1:0] 	    CorrectPCE;
 
   // Part 1 decode the instruction class.
   // *** for now I'm skiping the compressed instructions
@@ -77,7 +77,8 @@ module bpred
   
   // Part 2 branch direction prediction
 
-  twoBitPredictor predictor(.LookUpPC(PCNextF),
+  twoBitPredictor predictor(.clk(clk),
+			    .LookUpPC(PCNextF),
 			    .Prediction(BPPredF),
 			    // update
 			    .UpdatePC(PCE),
@@ -89,29 +90,37 @@ module bpred
   // 2) Any information which is necessary for the predictor to built it's next state.
   // For a 2 bit table this is the prediction count.
 
-  assign SelBPPredF = ((InstrClassF[0] & BPPredF[1]) | 
+  assign SelBPPredF = ((InstrClassF[0] & BPPredF[1] & BTBValidF) | 
 		       InstrClassF[3] |
 		       (InstrClassF[2] & BTBValidF) | 
-		       InstrClassF[1]) ;
+		       InstrClassF[1] & BTBValidF) ;
 
 
   // Part 3 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
 
-  BTBPredictor targetPredictor(.LookUpPC(PCNextF),
-			       .TargetPC(BTBPredPCF),
+  BTBPredictor targetPredictor(.clk(clk),
+			       .reset(reset),
+			       .LookUpPC(PCNextF),
+			       .TargetPC(BTBPredPCMemoryF),
 			       .Valid(BTBValidF),
 			       // update
 			       .UpdateEN(InstrClassE[2] | InstrClassE[1] | InstrClassE[0]),
 			       .UpdatePC(PCE),
 			       .UpdateTarget(PCTargetE));
 
+  // need to forward when updating to the same address as reading.
+  assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
+  assign TargetPC = (UpdatePC == LookUpPC) ? CorrectPCE : BTBPredPCMemoryF;
 
   // Part 4 RAS
-
-  RASPredictor RASPredictor(.pop(InstrClassF[3]),
+  // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
+  RASPredictor RASPredictor(.clk(clk),
+			    .reset(reset),
+			    .pop(InstrClassF[3]),
 			    .popPC(RASPCF),
 			    .push(InstrClassE[3]),
+			    .incr(1'b0),
 			    .pushPC(PCLinkE));
 
   assign BPPredPCF = InstrClassF[3] ? RASPCF : BTBPredPCF;
@@ -126,14 +135,14 @@ module bpred
 			   .en(~StallF),
 			   .clear(FlushF),
 			   .d(BPPredF),
-			   .Q(BPPredD));
+			   .q(BPPredD));
 
   flopenrc #(2) BPPredRegE(.clk(clk),
 			   .reset(reset),
 			   .en(~StallD),
 			   .clear(FlushD),
 			   .d(BPPredD),
-			   .Q(BPPredE));
+			   .q(BPPredE));
 
   // pipeline the class
   flopenrc #(4) InstrClassRegD(.clk(clk),
diff --git a/wally-pipelined/src/ifu/satCounter2.sv b/wally-pipelined/src/ifu/satCounter2.sv
index 91e47b04..33a842dc 100644
--- a/wally-pipelined/src/ifu/satCounter2.sv
+++ b/wally-pipelined/src/ifu/satCounter2.sv
@@ -29,7 +29,6 @@
 
 module satCounter2
   (input logic BrDir,
-   input logic Decr,
    input logic [1:0] OldState,
    output logic [1:0] NewState
    );
diff --git a/wally-pipelined/src/ifu/twoBitPredictor.sv b/wally-pipelined/src/ifu/twoBitPredictor.sv
index 6aa8f0b1..703312f5 100644
--- a/wally-pipelined/src/ifu/twoBitPredictor.sv
+++ b/wally-pipelined/src/ifu/twoBitPredictor.sv
@@ -30,22 +30,33 @@
 module twoBitPredictor
   #(parameter int Depth = 10
     )
-  (input clk,
-   input [`XLEN-1:0] LookUpPC,
-   output [1:0]      Prediction,
+  (input logic clk,
+   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0] 	   Prediction,
    // update
-   input [`XLEN-1:0] UpdatePC,
-   input 	     UpdateEN,
-   input [1:0] 	     UpdatePrediction
+   input logic [`XLEN-1:0] UpdatePC,
+   input logic 		   UpdateEN,
+   input logic [1:0] 	   UpdatePrediction
    );
 
+  logic [Depth-1:0] 	   LookUpPCIndex, UpdatePCIndex;
+
+  // hashing function for indexing the PC
+  // We have Depth bits to index, but XLEN bits as the input.
+  // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
+  // using compressed instructions.  XOR bit 1 with the MSB of index.
+  assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
+  assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};  
+
+
   SRAM2P1R1W #(Depth, 2) memory(.clk(clk),
 				.RA1(LookUpPC),
 				.RD1(PredictionMemory),
 				.REN1(1'b1),
 				.WA1(UpdatePC),
 				.WD1(UpdatePrediction),
-				.WEN1(UpdateEN));
+				.WEN1(UpdateEN),
+				.BitWEN1(2'b11));
 
   // need to forward when updating to the same address as reading.
   assign Prediction = (UpdatePC == LookUpPC) ? UpdatePrediction : PredictionMemory;

From 5df7e959f351ae6c433df12bf059490d78308640 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Wed, 17 Feb 2021 22:19:17 -0600
Subject: [PATCH 04/13] Integrated the branch predictor into the hardward.  Not
 yet working.

---
 wally-pipelined/regression/wally-pipelined.do |  5 ++
 wally-pipelined/src/hazard/hazard.sv          |  5 +-
 wally-pipelined/src/ifu/BTBPredictor.sv       |  4 +-
 wally-pipelined/src/ifu/SramModel.sv          | 22 ++++--
 wally-pipelined/src/ifu/bpred.sv              | 38 +++++-----
 wally-pipelined/src/ifu/ifu.sv                | 73 +++++++++++++++----
 wally-pipelined/src/ifu/twoBitPredictor.sv    |  6 +-
 .../src/wally/wallypipelinedhart.sv           |  4 +-
 8 files changed, 109 insertions(+), 48 deletions(-)

diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do
index b7f41535..60046294 100644
--- a/wally-pipelined/regression/wally-pipelined.do
+++ b/wally-pipelined/regression/wally-pipelined.do
@@ -38,6 +38,11 @@ switch $argc {
 vopt +acc work.testbench -o workopt 
 vsim workopt
 
+# load the branch predictors with known data. The value of the data is not important for function, but
+# is important for perventing pessimistic x propagation.
+mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
+mem load -infile BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
+
 view wave
 
 -- display input and output signals as hexidecimal values
diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv
index 2fe0541a..7eb116eb 100644
--- a/wally-pipelined/src/hazard/hazard.sv
+++ b/wally-pipelined/src/hazard/hazard.sv
@@ -30,7 +30,7 @@ module hazard(
 //  input  logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
 //  input  logic       MemReadE, 
 //  input  logic       RegWriteM, RegWriteW, 
-  input  logic       PCSrcE, CSRWritePendingDEM, RetM, TrapM,
+  input  logic       BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
   input  logic       LoadStallD,
   input  logic       InstrStall, DataStall,
   // Stall outputs
@@ -52,7 +52,7 @@ module hazard(
   // A stage must stall if the next stage is stalled
   // If any stages are stalled, the first stage that isn't stalled must flush.
 
-  assign BranchFlushDE = PCSrcE | RetM | TrapM;
+  assign BranchFlushDE = BPPredWrongE | RetM | TrapM;
 
   assign StallDCause = LoadStallD;
   assign StallFCause = InstrStall | CSRWritePendingDEM;
@@ -60,6 +60,7 @@ module hazard(
 
   assign StallD = StallDCause;
   assign StallF = StallD | StallFCause;
+  assign FlushF = BPPredWrongE;
   assign FlushD = BranchFlushDE | StallFCause; //  PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
   assign FlushE = StallD | BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM;
   assign FlushM = RetM | TrapM;
diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv
index 86ff3778..8e9723ec 100644
--- a/wally-pipelined/src/ifu/BTBPredictor.sv
+++ b/wally-pipelined/src/ifu/BTBPredictor.sv
@@ -72,10 +72,10 @@ module BTBPredictor
 				.RA1(LookUpPCIndex),
 				.RD1(TargetPC),
 				.REN1(1'b1),
-				.WA1(UpdatePCindex),
+				.WA1(UpdatePCIndex),
 				.WD1(UpdateTarget),
 				.WEN1(UpdateEN),
-				.BitWEN1({XLEN{1'b1}}));
+				.BitWEN1({`XLEN{1'b1}}));
 
 
 endmodule
diff --git a/wally-pipelined/src/ifu/SramModel.sv b/wally-pipelined/src/ifu/SramModel.sv
index d715d826..15d5699e 100644
--- a/wally-pipelined/src/ifu/SramModel.sv
+++ b/wally-pipelined/src/ifu/SramModel.sv
@@ -6,8 +6,16 @@
 // Created: February 14, 2021
 // Modified: 
 //
-// Purpose: Hacky two port SRAM model.
+// Purpose: Behavioral model of two port SRAM.  While this is synthesizable it will produce a flip flop based memory whi
+//          behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm.
+//          
 // 
+// to preload this memory we can use the following command
+// in modelsim's do file.
+// mem load -infile <relative path to the text file > -format <bin|hex> <hierarchy to the memory.>
+// example
+// mem laod -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
+//
 // A component of the Wally configurable RISC-V project.
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
@@ -30,7 +38,8 @@
 module SRAM2P1R1W
   #(parameter int Depth = 10,
     parameter int Width = 2
-    ) 
+    )
+
   (input clk,
     
    // port 1 is read only
@@ -45,16 +54,13 @@ module SRAM2P1R1W
    input logic [Width-1:0]  BitWEN1
    );
   
-  
-
-
 
   logic [Depth-1:0] 	    RA1Q, WA1Q;
   logic 		    WEN1Q;
   logic [Width-1:0] 	    WD1Q;
 
-  logic [2**Depth-1:0] [Width-1:0] memory;
-  
+  logic [Width-1:0] memory [2**Depth-1:0];
+
   
   // SRAMs address busses are always registered first.
 
@@ -92,7 +98,7 @@ module SRAM2P1R1W
     for (index = 0; index < Width; index = index + 1) begin    
       always_ff @ (posedge clk) begin
 	if (WEN1Q & BitWEN1[index]) begin
-	  memory[WA1Q][index] = WD1Q[index];
+	  memory[WA1Q][index] <= WD1Q[index];
 	end
       end
     end
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index d1c0bfb7..d0a44d88 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -58,7 +58,7 @@ module bpred
   logic [1:0] 		    BPPredF, BPPredD, BPPredE, UpdateBPPredE;
 
   logic [3:0] 		    InstrClassD, InstrClassF, InstrClassE;
-  logic [`XLEN-1:0] 	    BTBPredPCF, RASPCF;
+  logic [`XLEN-1:0] 	    BTBPredPCF, RASPCF, BTBPredPCMemoryF;
   logic 		    TargetWrongE;
   logic 		    FallThroughWrongE;
   logic 		    PredictionDirWrongE;
@@ -71,19 +71,19 @@ module bpred
   // This is probably too much logic. 
   // *** This also encourages me to switch to predicting the class.
 
-  assign InstrClassF[2] = InstrF[5:0] == 7'h67 && InstrF[19:15] == 5'h01; // jump register, but not return
-  assign InstrClassF[1] = InstrF[5:0] == 7'h6F; // jump
-  assign InstrClassF[0] = InstrF[5:0] == 7'h63; // branch
+  assign InstrClassF[2] = InstrF[6:0] == 7'h67 && InstrF[19:15] == 5'h01; // jump register, but not return
+  assign InstrClassF[1] = InstrF[6:0] == 7'h6F; // jump
+  assign InstrClassF[0] = InstrF[6:0] == 7'h63; // branch
   
   // Part 2 branch direction prediction
 
-  twoBitPredictor predictor(.clk(clk),
-			    .LookUpPC(PCNextF),
-			    .Prediction(BPPredF),
-			    // update
-			    .UpdatePC(PCE),
-			    .UpdateEN(InstrClassE[0]),
-			    .UpdatePrediction(UpdateBPPredE));
+  twoBitPredictor DirPredictor(.clk(clk),
+			       .LookUpPC(PCNextF),
+			       .Prediction(BPPredF),
+			       // update
+			       .UpdatePC(PCE),
+			       .UpdateEN(InstrClassE[0]),
+			       .UpdatePrediction(UpdateBPPredE));
 
   // this predictor will have two pieces of data,
   // 1) A direction (1 = Taken, 0 = Not Taken)
@@ -99,7 +99,7 @@ module bpred
   // Part 3 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
 
-  BTBPredictor targetPredictor(.clk(clk),
+  BTBPredictor TargetPredictor(.clk(clk),
 			       .reset(reset),
 			       .LookUpPC(PCNextF),
 			       .TargetPC(BTBPredPCMemoryF),
@@ -111,7 +111,7 @@ module bpred
 
   // need to forward when updating to the same address as reading.
   assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
-  assign TargetPC = (UpdatePC == LookUpPC) ? CorrectPCE : BTBPredPCMemoryF;
+  assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCMemoryF;
 
   // Part 4 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
@@ -152,12 +152,12 @@ module bpred
 			       .d(InstrClassF),
 			       .q(InstrClassD));
 
-  flopenr #(4) InstrClassRegE(.clk(clk),
-			      .reset(reset),
-			      .en(~StallD),
-			      .clear(flushD),
-			      .d(InstrClassD),
-			      .q(InstrClassE));
+  flopenrc #(4) InstrClassRegE(.clk(clk),
+			       .reset(reset),
+			       .en(~StallD),
+			       .clear(flushD),
+			       .d(InstrClassD),
+			       .q(InstrClassE));
 
   // Check the prediction makes execution.
   assign TargetWrongE = PCTargetE != PCD;
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 3a12b330..2824efb5 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -27,29 +27,30 @@
 `include "wally-config.vh"
 
 module ifu (
-  input  logic             clk, reset,
-  input  logic             StallF, StallD, FlushD, FlushE, FlushM, FlushW,
+  input logic 		   clk, reset,
+  input logic 		   StallF, StallD, FlushF, FlushD, FlushE, FlushM, FlushW,
   // Fetch
-  input  logic [31:0]      InstrF,
+  input logic [31:0] 	   InstrF,
   output logic [`XLEN-1:0] PCF, 
   output logic [`XLEN-1:0] InstrPAdrF,
   // Decode  
-  output logic             InstrStall,
+  output logic 		   InstrStall,
   // Execute
-  input  logic             PCSrcE, 
-  input  logic [`XLEN-1:0] PCTargetE,
-  output logic [`XLEN-1:0] PCE, 
+  input logic 		   PCSrcE, 
+  input logic [`XLEN-1:0]  PCTargetE,
+  output logic [`XLEN-1:0] PCE,
+  output logic BPPredWrongE,		   
   // Mem
-  input  logic             RetM, TrapM, 
-  input  logic [`XLEN-1:0] PrivilegedNextPCM, 
-  output logic [31:0]      InstrD, InstrM,
+  input logic 		   RetM, TrapM, 
+  input logic [`XLEN-1:0]  PrivilegedNextPCM, 
+  output logic [31:0] 	   InstrD, InstrM,
   output logic [`XLEN-1:0] PCM, 
   // Writeback
   output logic [`XLEN-1:0] PCLinkW,
   // Faults
-  input  logic             IllegalBaseInstrFaultD,
-  output logic             IllegalIEUInstrFaultD,
-  output logic             InstrMisalignedFaultM,
+  input logic 		   IllegalBaseInstrFaultD,
+  output logic 		   IllegalIEUInstrFaultD,
+  output logic 		   InstrMisalignedFaultM,
   output logic [`XLEN-1:0] InstrMisalignedAdrM
 );
 
@@ -62,6 +63,11 @@ module ifu (
   logic [31:0]     InstrRawD, InstrE;
   logic [31:0]     nop = 32'h00000013; // instruction for NOP
 
+  // branch predictor signals
+  logic 	   SelBPPredF;
+  logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F;
+  
+
   // *** put memory interface on here, InstrF becomes output
   assign InstrStall = 0; // ***
   assign InstrPAdrF = PCF; // *** no MMU
@@ -70,10 +76,49 @@ module ifu (
 
   assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
 
-  mux3    #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
+  //mux3    #(`XLEN) pcmux(PCPlus2or4F, PCCorrectE, PrivilegedNextPCM, {PrivilegedChangePCM, BPPredWrongE}, UnalignedPCNextF);
+  mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
+		       .d1(BPPredPCF),
+		       .s(SelBPPredF),
+		       .y(PCNext0F));
+
+  mux2 #(`XLEN) pcmux1(.d0(PCNext0F),
+		       .d1(PCCorrectE),
+		       .s(BPPredWrongE),
+		       .y(PCNext1F));
+
+  mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
+		       .d1(PrivilegedNextPCM),
+		       .s(PrivilegedChangePCM),
+		       .y(UnalignedPCNextF));
+  
   assign  PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
   flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);
 
+  // branch and jump predictor
+  // I am making the port connection explicit for now as I want to see them and they will be changing.
+  bpred bpred(.clk(clk),
+	      .reset(reset),
+	      .StallF(StallF),
+	      .StallD(StallD),
+	      .StallE(1'b0),   // *** may need this eventually
+	      .FlushF(FlushF),
+	      .FlushD(FlushD),
+	      .FlushE(FlushE),
+	      .PCNextF(PCNextF),
+	      .BPPredPCF(BPPredPCF),
+	      .SelBPPredF(SelBPPredF),
+	      .InstrF(InstrF), // *** this is flushed internally. The logic is redundant with some out here.
+	      // Also I believe this port will be removed.
+	      .PCE(PCE),
+	      .PCSrcE(PCSrcE),
+	      .PCTargetE(PCTargetE),
+	      .PCD(PCD),
+	      .PCLinkE(PCLinkE),
+	      .BPPredWrongE(BPPredWrongE));
+  // The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE.
+  assign PCCorrectE =  PCSrcE ? PCTargetE : PCLinkE;
+
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
   assign CompressedF = (InstrF[1:0] != 2'b11); // is it a 16-bit compressed instruction?
diff --git a/wally-pipelined/src/ifu/twoBitPredictor.sv b/wally-pipelined/src/ifu/twoBitPredictor.sv
index 703312f5..34e46b60 100644
--- a/wally-pipelined/src/ifu/twoBitPredictor.sv
+++ b/wally-pipelined/src/ifu/twoBitPredictor.sv
@@ -40,6 +40,8 @@ module twoBitPredictor
    );
 
   logic [Depth-1:0] 	   LookUpPCIndex, UpdatePCIndex;
+  logic [1:0] 		   PredictionMemory;
+  
 
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
@@ -50,10 +52,10 @@ module twoBitPredictor
 
 
   SRAM2P1R1W #(Depth, 2) memory(.clk(clk),
-				.RA1(LookUpPC),
+				.RA1(LookUpPCIndex),
 				.RD1(PredictionMemory),
 				.REN1(1'b1),
-				.WA1(UpdatePC),
+				.WA1(UpdatePCIndex),
 				.WD1(UpdatePrediction),
 				.WEN1(UpdateEN),
 				.BitWEN1(2'b11));
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 408045e2..3753c3b1 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -49,7 +49,7 @@ module wallypipelinedhart (
 );
 
   logic [1:0]  ForwardAE, ForwardBE;
-  logic        StallF, StallD, FlushD, FlushE, FlushM, FlushW;
+  logic        StallF, StallD, FlushF, FlushD, FlushE, FlushM, FlushW;
   logic        RetM, TrapM;
 
   // new signals that must connect through DP
@@ -86,6 +86,8 @@ module wallypipelinedhart (
   logic [`XLEN-1:0] InstrPAdrF;
   logic             DataStall, InstrStall;
   logic             InstrAckD, MemAckW;
+  logic 	    BPPredWrongE;
+  
            
   ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
 

From de9e383bc6f9a85d060e3ab110e2b43555f3f151 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Wed, 17 Feb 2021 22:20:28 -0600
Subject: [PATCH 05/13] Wrote a bash script to generate custom modelsim radix
 which maps instruction addresses into human readable lables. Once combined
 with some simulation verilog this will display the current function in
 modelsim.

---
 wally-pipelined/bin/extractFunctionRadix.sh   |   32 +
 wally-pipelined/regression/BTBPredictor.txt   | 1024 +++++++++++++++++
 .../regression/twoBitPredictor.txt            | 1024 +++++++++++++++++
 .../regression/wally-pipelined-ross.do        |   52 +
 wally-pipelined/regression/wave.do            |   42 +
 5 files changed, 2174 insertions(+)
 create mode 100755 wally-pipelined/bin/extractFunctionRadix.sh
 create mode 100644 wally-pipelined/regression/BTBPredictor.txt
 create mode 100644 wally-pipelined/regression/twoBitPredictor.txt
 create mode 100644 wally-pipelined/regression/wally-pipelined-ross.do
 create mode 100644 wally-pipelined/regression/wave.do

diff --git a/wally-pipelined/bin/extractFunctionRadix.sh b/wally-pipelined/bin/extractFunctionRadix.sh
new file mode 100755
index 00000000..1a8ca7f6
--- /dev/null
+++ b/wally-pipelined/bin/extractFunctionRadix.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+
+for objDumpFile in "$@";
+do
+
+    # get the lines with named labels from the obj files.
+    listOfAddr=`egrep -i '^[0-9]{8} <[0-9a-zA-Z_]+>' $objDumpFile`
+
+    # parse out the addresses and the labels
+    addresses=`echo "$listOfAddr" | awk '{print $1}'`
+    labels=`echo "$listOfAddr" | awk '{print  "\""$2"\"", "-color \"SpringGreen\","}' | tr -d '<>:'`
+
+    echo "$addresses" > $objDumpFile.addr
+
+    # need to add some formatting to each line
+    numLines=`echo "$listOfAddr" | wc -l`
+    prefix=`yes "    16#" | head -n  $numLines`
+    midfix=`yes "# " | head -n $numLines`
+
+    # paste echos each of the 4 parts on a per line basis.
+    #-d'\0' sets no delimiter
+    temp=`paste -d'\0' <(echo "$prefix") <(echo "$addresses") <(echo "$midfix") <(echo "$labels")`
+
+    # remove the last comma
+    temp2=${temp::-1}
+
+    echo "radix define Functions {" > $objDumpFile.do
+    echo "$temp2" >> $objDumpFile.do
+    echo "    -default hex -color green" >> $objDumpFile.do
+    echo "}" >> $objDumpFile.do
+
+done
diff --git a/wally-pipelined/regression/BTBPredictor.txt b/wally-pipelined/regression/BTBPredictor.txt
new file mode 100644
index 00000000..fdc80244
--- /dev/null
+++ b/wally-pipelined/regression/BTBPredictor.txt
@@ -0,0 +1,1024 @@
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diff --git a/wally-pipelined/regression/wally-pipelined-ross.do b/wally-pipelined/regression/wally-pipelined-ross.do
new file mode 100644
index 00000000..f6ca26b3
--- /dev/null
+++ b/wally-pipelined/regression/wally-pipelined-ross.do
@@ -0,0 +1,52 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
+# do wally-pipelined.do ../config/rv32ic
+switch $argc {
+    0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+}
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+vopt +acc work.testbench -o workopt 
+vsim workopt
+
+# load the branch predictors with known data. The value of the data is not important for function, but
+# is important for perventing pessimistic x propagation.
+mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
+mem load -infile BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
+
+do wave.do
+add log /* -recursive
+
+-- Run the Simulation 
+#run 1000
+run -all
+#quit
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
new file mode 100644
index 00000000..3e8db24d
--- /dev/null
+++ b/wally-pipelined/regression/wave.do
@@ -0,0 +1,42 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/reset
+add wave -noupdate -divider <NULL>
+add wave -noupdate /testbench/dut/hart/ebu/IReadF
+add wave -noupdate -group HDU /testbench/dut/hart/DataStall
+add wave -noupdate -group HDU /testbench/dut/hart/InstrStall
+add wave -noupdate -group HDU /testbench/dut/hart/StallF
+add wave -noupdate -group HDU /testbench/dut/hart/StallD
+add wave -noupdate -group HDU /testbench/dut/hart/FlushD
+add wave -noupdate -group HDU /testbench/dut/hart/FlushE
+add wave -noupdate -group HDU /testbench/dut/hart/FlushM
+add wave -noupdate -group HDU /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
+add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
+add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
+add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePCIndex
+add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePrediction
+add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
+add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassF
+add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassD
+add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassE
+add wave -noupdate /testbench/dut/hart/ifu/bpred/InstrF
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {72 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 185
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {329 ns}

From c6ebe7733b1ffecfe2c0c51bbbcfc09847876a8d Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Thu, 18 Feb 2021 21:32:15 -0600
Subject: [PATCH 06/13] Hacked the sram memory models to reset their internal
 registers.  This allows the simulation to run but is only temporary. About
 149307ns of simulation run.

---
 wally-pipelined/regression/wave.do            | 45 ++++++++++++++-----
 wally-pipelined/src/ifu/BTBPredictor.sv       | 45 ++++++++++++-------
 wally-pipelined/src/ifu/SramModel.sv          | 18 ++++----
 wally-pipelined/src/ifu/bpred.sv              |  6 +--
 wally-pipelined/src/ifu/twoBitPredictor.sv    |  2 +
 .../testbench/testbench-imperas.sv            |  2 +-
 6 files changed, 81 insertions(+), 37 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 3e8db24d..abd55f5a 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -4,14 +4,15 @@ add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate -divider <NULL>
 add wave -noupdate /testbench/dut/hart/ebu/IReadF
-add wave -noupdate -group HDU /testbench/dut/hart/DataStall
-add wave -noupdate -group HDU /testbench/dut/hart/InstrStall
-add wave -noupdate -group HDU /testbench/dut/hart/StallF
-add wave -noupdate -group HDU /testbench/dut/hart/StallD
-add wave -noupdate -group HDU /testbench/dut/hart/FlushD
-add wave -noupdate -group HDU /testbench/dut/hart/FlushE
-add wave -noupdate -group HDU /testbench/dut/hart/FlushM
-add wave -noupdate -group HDU /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU /testbench/dut/hart/DataStall
+add wave -noupdate -expand -group HDU /testbench/dut/hart/InstrStall
+add wave -noupdate -expand -group HDU /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -expand -group HDU /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU /testbench/dut/hart/StallD
+add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushD
+add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushE
+add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushM
+add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushW
 add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
 add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
 add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
@@ -22,8 +23,32 @@ add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/Instr
 add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassD
 add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassE
 add wave -noupdate /testbench/dut/hart/ifu/bpred/InstrF
+add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredWrongE
+add wave -noupdate /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate /testbench/dut/hart/ifu/PCF
+add wave -noupdate /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBValidF
+add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredF
+add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/ValidBits
+add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPCIndexQ
+add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
+add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPC
+add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
+add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
+add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
+add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
+add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
+add wave -noupdate -expand -group BTB -divider Update
+add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {72 ns} 0}
+WaveRestoreCursors {{Cursor 1} {66 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 185
@@ -39,4 +64,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {329 ns}
+WaveRestoreZoom {21 ns} {105 ns}
diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv
index 8e9723ec..041f2b64 100644
--- a/wally-pipelined/src/ifu/BTBPredictor.sv
+++ b/wally-pipelined/src/ifu/BTBPredictor.sv
@@ -32,19 +32,19 @@ module BTBPredictor
   #(parameter int Depth = 10
     )
   (input  logic clk,
-   input  logic reset,
-   input  logic [`XLEN-1:0] LookUpPC,
+   input logic 		    reset,
+   input logic [`XLEN-1:0]  LookUpPC,
    output logic [`XLEN-1:0] TargetPC,
-   output logic Valid,
+   output logic 	    Valid,
    // update
-   input  logic UpdateEN,
-   input  logic [`XLEN-1:0] UpdatePC,
-   input  logic [`XLEN-1:0] UpdateTarget
+   input logic 		    UpdateEN,
+   input logic [`XLEN-1:0]  UpdatePC,
+   input logic [`XLEN-1:0]  UpdateTarget
    );
 
   localparam TotalDepth = 2 ** Depth;
   logic [TotalDepth-1:0]    ValidBits;
-  logic [Depth-1:0] 	    LookUpPCIndex, UpdatePCIndex;
+  logic [Depth-1:0] 	    LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
 
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
@@ -53,29 +53,44 @@ module BTBPredictor
   assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
   assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};  
   
+
+  flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
+				    .reset(reset),
+				    .en(1'b1),
+				    .d(UpdatePCIndex),
+				    .q(UpdatePCIndexQ));
   
   // The valid bit must be resetable.
   always_ff @ (posedge clk) begin
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
     end else if (UpdateEN) begin
-      ValidBits[UpdatePCIndex] <= #1 1'b1;
+      ValidBits[UpdatePCIndexQ] <= #1 1'b1;
     end
   end
 
+  flopenr #(Depth) LookupPCIndexReg(.clk(clk),
+				    .reset(reset),
+				    .en(1'b1),
+				    .d(LookUpPCIndex),
+				    .q(LookUpPCIndexQ));
+
+  assign Valid = ValidBits[LookUpPCIndexQ];
+
   // the BTB contains the target address.
   // *** future version may contain the instruction class, a tag or partial tag,
   // and other indirection branch data.
   // Another optimization may be using a PC relative address.
 
   SRAM2P1R1W #(Depth, `XLEN) memory(.clk(clk),
-				.RA1(LookUpPCIndex),
-				.RD1(TargetPC),
-				.REN1(1'b1),
-				.WA1(UpdatePCIndex),
-				.WD1(UpdateTarget),
-				.WEN1(UpdateEN),
-				.BitWEN1({`XLEN{1'b1}}));
+				    .reset(reset),
+				    .RA1(LookUpPCIndex),
+				    .RD1(TargetPC),
+				    .REN1(1'b1),
+				    .WA1(UpdatePCIndex),
+				    .WD1(UpdateTarget),
+				    .WEN1(UpdateEN),
+				    .BitWEN1({`XLEN{1'b1}}));
 
 
 endmodule
diff --git a/wally-pipelined/src/ifu/SramModel.sv b/wally-pipelined/src/ifu/SramModel.sv
index 15d5699e..1ecdfd31 100644
--- a/wally-pipelined/src/ifu/SramModel.sv
+++ b/wally-pipelined/src/ifu/SramModel.sv
@@ -40,8 +40,10 @@ module SRAM2P1R1W
     parameter int Width = 2
     )
 
-  (input clk,
-    
+  (input logic clk,
+   // *** have to remove reset eventually
+   input logic 		    reset,
+  
    // port 1 is read only
    input logic [Depth-1:0]  RA1,
    output logic [Width-1:0] RD1,
@@ -59,39 +61,39 @@ module SRAM2P1R1W
   logic 		    WEN1Q;
   logic [Width-1:0] 	    WD1Q;
 
-  logic [Width-1:0] memory [2**Depth-1:0];
+  logic [Width-1:0] 	    memory [2**Depth-1:0];
 
   
   // SRAMs address busses are always registered first.
 
   flopenr #(Depth) RA1Reg(.clk(clk),
-			  .reset(1'b0),
+			  .reset(reset),
 			  .en(REN1),
 			  .d(RA1),
 			  .q(RA1Q));
   
 
   flopenr #(Depth) WA1Reg(.clk(clk),
-			  .reset(1'b0),
+			  .reset(reset),
 			  .en(REN1),
 			  .d(WA1),
 			  .q(WA1Q));
 
   flopenr #(1) WEN1Reg(.clk(clk),
-		       .reset(1'b0),
+		       .reset(reset),
 		       .en(1'b1),
 		       .d(WEN1),
 		       .q(WEN1Q));
   
   flopenr #(Width) WD1Reg(.clk(clk),
-			  .reset(1'b0),
+			  .reset(reset),
 			  .en(REN1),
 			  .d(WD1),
 			  .q(WD1Q));
   // read port
   assign RD1 = memory[RA1Q];
 
-  genvar 			   index;
+  genvar 		    index;
   
   // write port
   generate
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index d0a44d88..9d676ca8 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -162,13 +162,13 @@ module bpred
   // Check the prediction makes execution.
   assign TargetWrongE = PCTargetE != PCD;
   assign FallThroughWrongE = PCLinkE != PCD;
-  assign PredictionDirWrongE = BPPredE ^ PCSrcE;
+  assign PredictionDirWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
   assign PredictionPCWrongE = PCSrcE ? TargetWrongE : FallThroughWrongE;
-  assign BPPredWrongE = PredictionPCWrongE | PredictionDirWrongE;
+  assign BPPredWrongE = (PredictionPCWrongE | PredictionDirWrongE) & (|InstrClassE);
 
   // Update predictors
 
-  satCounter2 BPDirUpdate(.BrDir(~PredictionDirWrongE),
+  satCounter2 BPDirUpdate(.BrDir(PCSrcE),
 			  .OldState(BPPredE),
 			  .NewState(UpdateBPPredE));
 
diff --git a/wally-pipelined/src/ifu/twoBitPredictor.sv b/wally-pipelined/src/ifu/twoBitPredictor.sv
index 34e46b60..704d7fb0 100644
--- a/wally-pipelined/src/ifu/twoBitPredictor.sv
+++ b/wally-pipelined/src/ifu/twoBitPredictor.sv
@@ -31,6 +31,7 @@ module twoBitPredictor
   #(parameter int Depth = 10
     )
   (input logic clk,
+   input logic reset,
    input logic [`XLEN-1:0] LookUpPC,
    output logic [1:0] 	   Prediction,
    // update
@@ -52,6 +53,7 @@ module twoBitPredictor
 
 
   SRAM2P1R1W #(Depth, 2) memory(.clk(clk),
+				.reset(reset),
 				.RA1(LookUpPCIndex),
 				.RD1(PredictionMemory),
 				.REN1(1'b1),
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 9e3aba4c..91e32059 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -329,7 +329,7 @@ string tests32i[] = {
       memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
       $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.uncore.dtim.RAM);
-      reset = 1; # 22; reset = 0;
+      reset = 1; # 42; reset = 0;
     end
 
   // generate clock to sequence tests

From f25de68b7d8502a38df716e07e940e477aed11f6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Fri, 19 Feb 2021 09:08:13 -0600
Subject: [PATCH 07/13] minor change to wave file.

---
 wally-pipelined/regression/wave.do | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index abd55f5a..134275b9 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -2,17 +2,18 @@ onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
+add wave -noupdate -radix ascii /testbench/memfilename
 add wave -noupdate -divider <NULL>
 add wave -noupdate /testbench/dut/hart/ebu/IReadF
 add wave -noupdate -expand -group HDU /testbench/dut/hart/DataStall
 add wave -noupdate -expand -group HDU /testbench/dut/hart/InstrStall
-add wave -noupdate -expand -group HDU /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU -color Orange /testbench/dut/hart/StallD
 add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
 add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
 add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
@@ -48,7 +49,7 @@ add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredic
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {66 ns} 0}
+WaveRestoreCursors {{Cursor 1} {137177 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 185
@@ -64,4 +65,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {21 ns} {105 ns}
+WaveRestoreZoom {136946 ns} {137442 ns}

From 00de91cc87a8e4d08c300c5e8626588981bece0f Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Fri, 19 Feb 2021 16:36:51 -0600
Subject: [PATCH 08/13] Added FlushF to hazard unit. Fixed some typos with the
 names of signals in the branch predictor.  They were causing signals to be
 not set.  Note there is a modelsim flag which prevents it from compiling if a
 logic is undefined. I will look this up and add it to the compiler.

---
 .../regression/wally-pipelined-ross.do        |    2 +-
 wally-pipelined/regression/wave-all.do        | 1622 +++++++++++++++++
 wally-pipelined/regression/wave.do            |   91 +-
 wally-pipelined/src/hazard/hazard.sv          |    2 +-
 wally-pipelined/src/ifu/bpred.sv              |   10 +-
 wally-pipelined/src/ifu/ifu.sv                |    2 +-
 6 files changed, 1694 insertions(+), 35 deletions(-)
 create mode 100644 wally-pipelined/regression/wave-all.do

diff --git a/wally-pipelined/regression/wally-pipelined-ross.do b/wally-pipelined/regression/wally-pipelined-ross.do
index f6ca26b3..7d3b4f3c 100644
--- a/wally-pipelined/regression/wally-pipelined-ross.do
+++ b/wally-pipelined/regression/wally-pipelined-ross.do
@@ -44,7 +44,7 @@ mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/Di
 mem load -infile BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
 
 do wave.do
-add log /* -recursive
+add log -r /*
 
 -- Run the Simulation 
 #run 1000
diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do
new file mode 100644
index 00000000..a6a0747b
--- /dev/null
+++ b/wally-pipelined/regression/wave-all.do
@@ -0,0 +1,1622 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/reset
+add wave -noupdate /testbench/memfilename
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -divider <NULL>
+add wave -noupdate /testbench/dut/hart/ebu/IReadF
+add wave -noupdate /testbench/dut/hart/DataStall
+add wave -noupdate /testbench/dut/hart/InstrStall
+add wave -noupdate /testbench/dut/hart/StallF
+add wave -noupdate /testbench/dut/hart/StallD
+add wave -noupdate /testbench/dut/hart/FlushD
+add wave -noupdate /testbench/dut/hart/FlushE
+add wave -noupdate /testbench/dut/hart/FlushM
+add wave -noupdate /testbench/dut/hart/FlushW
+add wave -noupdate -divider <NULL>
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrF
+add wave -noupdate /testbench/InstrFName
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrD
+add wave -noupdate /testbench/InstrDName
+add wave -noupdate -divider <NULL>
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/InstrD
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
+add wave -noupdate /testbench/dut/hart/ieu/dp/PCSrcE
+add wave -noupdate -divider <NULL>
+add wave -noupdate /testbench/InstrMName
+add wave -noupdate /testbench/dut/uncore/dtim/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA
+add wave -noupdate -divider <NULL>
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW
+add wave -noupdate /testbench/InstrWName
+add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdW
+add wave -noupdate -divider <NULL>
+add wave -noupdate -radix hexadecimal /testbench/clk
+add wave -noupdate -radix hexadecimal /testbench/reset
+add wave -noupdate -radix hexadecimal /testbench/test
+add wave -noupdate -radix hexadecimal /testbench/i
+add wave -noupdate -radix hexadecimal /testbench/errors
+add wave -noupdate -radix hexadecimal /testbench/totalerrors
+add wave -noupdate -radix hexadecimal /testbench/testadr
+add wave -noupdate -radix hexadecimal /testbench/InstrW
+add wave -noupdate -radix hexadecimal /testbench/meminit
+add wave -noupdate -radix hexadecimal /testbench/HRDATAEXT
+add wave -noupdate -radix hexadecimal /testbench/HREADYEXT
+add wave -noupdate -radix hexadecimal /testbench/HRESPEXT
+add wave -noupdate -radix hexadecimal /testbench/HADDR
+add wave -noupdate -radix hexadecimal /testbench/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/HBURST
+add wave -noupdate -radix hexadecimal /testbench/HPROT
+add wave -noupdate -radix hexadecimal /testbench/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/HCLK
+add wave -noupdate -radix hexadecimal /testbench/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/UARTSin
+add wave -noupdate -radix hexadecimal /testbench/UARTSout
+add wave -noupdate -radix hexadecimal /testbench/dut/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/HRDATAEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/HREADYEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/HRESPEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/dut/UARTSin
+add wave -noupdate -radix hexadecimal /testbench/dut/UARTSout
+add wave -noupdate -radix hexadecimal /testbench/dut/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/StallF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/StoreMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/StoreAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/zero
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/FloatRegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/MemRWAlignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ReadDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrPAdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/DataStall
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrStall
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrAckD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/MemAckW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/StallF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrPAdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrStall
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/UnalignedPCNextF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/misaligned
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/BranchMisalignedFaultE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/BranchMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/TrapMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/StallExceptResolveBranchesF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/IllegalCompInstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlusUpperF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/CompressedF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrRawD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/nop
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcmux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/pcreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrDReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrDReg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrDReg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrDReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrDReg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrDReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCDReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCDReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCDReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCDReg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCDReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCDReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/InstrRawD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/IllegalCompInstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/instr16
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/rds1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/rs2
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/rs1p
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/rs2p
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/rds1p
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/rdp
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCILSP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCILSPD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCSS
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCSSD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCL
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCLD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCI
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCS
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCSD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCB
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCIASP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCIW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCJ
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immCILUI
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/immSH
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/decomp/op
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalginedReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalginedReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalginedReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalginedReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalignedAdrReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalignedAdrReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalignedAdrReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMisalignedAdrReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPDReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPDReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPDReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPDReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/FlagsE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ALUControlE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ALUSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ALUSrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ResultSrcW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/TargetSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/Rs1D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/Rs2D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/Rs1E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/Rs2E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/RdE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/RdM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/RdW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/RegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/MemReadE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/OpD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/Funct3D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/Funct7b5D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/FlagsE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ALUControlE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ALUSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ALUSrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/TargetSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/MemReadE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ResultSrcW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ResultSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ResultSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ResultSrcM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/MemRWD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/MemRWE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/JumpD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/JumpE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/BranchD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/BranchE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ALUOpD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ALUControlD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ALUSrcAD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ALUSrcBD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/TargetSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/W64D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/CSRWriteD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/CSRWriteE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/Funct3E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/PrivilegedD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/PrivilegedE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ControlsD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/aluc3D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/subD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/sraD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/sltD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/sltuD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/BranchTakenE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/zeroE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ltE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ltuE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregE/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregE/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregE/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregE/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregE/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregM/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregM/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregM/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregM/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregM/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregW/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregW/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregW/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregW/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/controlregW/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUControlE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUSrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/TargetSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/FlagsE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultSrcW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs1D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs2D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs1E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs2E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/PreSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/TargetBaseE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/we3
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/a1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/a2
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/a3
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/rd1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/rd2
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/i
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ext/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ext/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ext/ExtImmD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmEReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs1EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs1EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs1EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs1EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs1EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs2EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs2EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs2EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs2EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/Rs2EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdEReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/faemux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/faemux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/faemux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/faemux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/faemux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/fbemux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/fbemux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/fbemux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/fbemux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/fbemux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcamux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcamux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcamux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcamux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/a
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/b
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/result
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/condinvb
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/presum
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sum
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/shift
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/slt
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sltu
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/bor
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/right
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/arith
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/w64
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/carry
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/zero
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/neg
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/lt
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/ltu
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/overflow
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/a
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/amt
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/right
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/arith
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/w64
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/genblk1/z
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/genblk1/zshift
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/genblk1/ylower
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/genblk1/yupper
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/genblk1/offset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/genblk1/amt6
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/targetsrcmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/targetsrcmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/targetsrcmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/targetsrcmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAMReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultMReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataMReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdMEg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdMEg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdMEg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdMEg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdMEg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultWReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdWEg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdWEg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdWEg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdWEg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdWEg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/resultmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/resultmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/resultmux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/resultmux/d3
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/resultmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/resultmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/Rs1D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/Rs2D
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/Rs1E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/Rs2E
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/RdE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/RdM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/RdW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/MemReadE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/RegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/fw/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/DataStall
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/ReadDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/MemRWAlignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/MemAckW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/StoreMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/StoreAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/ReadDataWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/ReadDataWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/ReadDataWReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/ReadDataWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/dmem/ReadDataWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/UnsignedLoadM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/InstrPAdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/IReadF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/IRData
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/DReadM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/DWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/DSizeM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/DRData
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/InstrAckD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/MemAckW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/GrantData
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/ISize
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/HRDATAMasked
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/IReady
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/DReady
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/UnsignedLoadM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/HRDATAMasked
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/ByteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/HalfwordM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ebu/swr/genblk1/WordM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/InstrStall
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/DataStall
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/StallF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/BranchFlushDE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/StallDCause
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/StallFCause
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/hzu/StallWCause
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/FloatRegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/StoreMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/StoreAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/CauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/NextFaultMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/SEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/SIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/ecallM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/ebreakM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/wfiM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/sfencevmaM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/IllegalCSRAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/IllegalIEUInstrFaultE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/IllegalIEUInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrAccessFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrAccessFaultE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/IllegalInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/BreakpointFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/EcallFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/LoadPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/StorePageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/STATUS_MPP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/STATUS_SPP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/md
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/sd
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/privmodereg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/privmodereg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/privmodereg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/IllegalIEUInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/IllegalCSRAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/IllegalInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/ecallM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/ebreakM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/wfiM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/sfencevmaM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/pmd/IllegalPrivilegedInstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/FloatRegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/NextFaultMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/STATUS_MPP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/STATUS_SPP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/IllegalCSRAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRMReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRSReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRUReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRNReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRCReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRSrcM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRRSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRRCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/WriteMSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/WriteSSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/WriteUSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRSWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRUWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/UnalignedNextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/CSRAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/UIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/UIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/IllegalCSRCAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/IllegalCSRMAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/IllegalCSRSAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/IllegalCSRUAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/IllegalCSRNAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/InsufficientCSRPrivilegeM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/CSRSWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/CSRAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/IntInM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/IP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/IE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_WRITE_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_WRITE_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/WriteMIPM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/WriteMIEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/WriteSIPM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/WriteSIEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/WriteMSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/WriteSSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/WriteUSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/FloatRegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/MSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/SSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/USTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_MPP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_SPP
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_SD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_TW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_TVM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_MXR
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_SUM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_SUM_INT
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_MPRV
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_MPRV_INT
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_SXL
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_UXL
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_XS
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_FS
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_FS_INT
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_MPP_NEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_MPIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_SPIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_UPIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_UIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/CSRAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/SCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/CSRCReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/IllegalCSRCAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/CYCLE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/CYCLEPlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRETPlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3PlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4PlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/NextCYCLEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/NextINSTRETM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER3M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER4M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/WriteCYCLEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/WriteINSTRETM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER3M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER4M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/CounterNumM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/CSRAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/CSRMReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/IllegalCSRMAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG01_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG23_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR0_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/zero
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/allones
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMTVECM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMIDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMSCRATCHM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMCAUSEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMTVALM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMCOUNTERENM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMCOUNTINHIBITM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WritePMPCFG0M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WritePMPCFG2M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/WritePMPADDR0M
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISAbits
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVECreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVECreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVECreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVECreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVECreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVECreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCHreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCHreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCHreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCHreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCHreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPCreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPCreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPCreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPCreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPCreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSEreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSEreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSEreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSEreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSEreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVALreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVALreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVALreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVALreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVALreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTERENreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTERENreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTERENreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTERENreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTERENreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTERENreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR0reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR0reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR0reg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR0reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR0reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/CSRSWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/CSRAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/CSRSReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/WriteSSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/IllegalCSRSAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/zero
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/allones
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSTVECM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSEDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSIDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSSCRATCHM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSCAUSEM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSTVALM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSATPM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/WriteSCOUNTERENM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SSCRATCH_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVAL_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SATP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVECreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVECreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVECreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVECreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVECreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVECreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SEPCreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SEPCreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SEPCreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SEPCreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SEPCreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVALreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVALreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVALreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVALreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/STVALreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SATPreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SATPreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SATPreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SATPreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SATPreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/CSRNWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/CSRAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/USTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/CSRNReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/WriteUSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/IllegalCSRNAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/CSRUWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/CSRAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/CSRUReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/IllegalCSRUAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FFLAGS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/WriteFFLAGSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/WriteFRMM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/WriteFCSRM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/NextFRMM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/NextFFLAGSM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FRMreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FRMreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FRMreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FRMreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FRMreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FFLAGSreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FFLAGSreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FFLAGSreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/genblk1/FFLAGSreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/CSRValWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/CSRValWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/CSRValWReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/CSRValWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/CSRValWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregD/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregD/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregD/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregD/en
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregD/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregD/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregE/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregE/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregE/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregE/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregE/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregM/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregM/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregM/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregM/d
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/faultregM/q
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/CauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/NextFaultMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/MIntGlobalEnM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/SIntGlobalEnM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/PendingIntsM
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/AdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/adrbits
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATAIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRDATAEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTSin
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTSout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/PreHSELUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRW
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWtim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWclint
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWgpio
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWuart
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTIntr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HWDATAIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/ByteM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HalfwordM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/WriteDataSubwordDuplicated
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/ByteMaskM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/MemRWtim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HSELTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HREADTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HRESPTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HREADYTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/entry
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/memread
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/busycount
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MemRWclint
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HREADCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HRESPCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HREADYCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MTIMECMP
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MTIME
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MSIP
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/entry
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/memread
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/MemRWgpio
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HREADGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HRESPGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HREADYGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/INPUT_VAL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/INPUT_EN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/OUTPUT_EN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/OUTPUT_VAL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/entry
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/memread
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MemRWuart
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HREADUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HRESPUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HREADYUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/SIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/DSRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/DCDb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/CTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/RIb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/SOUT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/RTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/DTRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/OUT1b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/OUT2b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/INTR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/TXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/RXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/A
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MEMRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MEMWb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/Din
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/Dout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/BAUDOUTb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/A
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/Din
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/Dout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MEMRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MEMWb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/INTR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/TXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/BAUDOUTb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SOUT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DTRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/OUT1b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/OUT2b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RBR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/FCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/LCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/LSR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DLL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DLM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/IER
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MSR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SINd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SINsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SOUTbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/loop
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DLAB
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/baudpulse
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbaudpulse
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbaudpulse
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/baudcount
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxoversampledcnt
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txoversampledcnt
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbitsreceived
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbitssent
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxstate
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txstate
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxshiftreg
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifohead
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotail
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifohead
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifotail
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotriggerlevel
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifoentries
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifoentries
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbitsexpected
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbitsexpected
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RXBR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxtimeoutcnt
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxcentered
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparity
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparitybit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxstopbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparityerr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxoverrunerr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxframingerr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbreak
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifohaserr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdataready
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifoempty
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotriggered
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotimeout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifodmaready
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdata9
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdata
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxerrbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfullbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/TXHR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txdata
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/nexttxdata
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txsr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txnextbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txhrfull
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txsrfull
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txparity
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifoempty
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifofull
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifodmaready
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/fifoenabled
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/fifodmamodesel
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/evenparitysel
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxlinestatusintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdataavailintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txhremptyintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/modemstatusintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/intrpending
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/intrid
+add wave -noupdate -radix hexadecimal /testbench/it/clk
+add wave -noupdate -radix hexadecimal /testbench/it/reset
+add wave -noupdate -radix hexadecimal /testbench/it/FlushE
+add wave -noupdate -radix hexadecimal /testbench/it/InstrD
+add wave -noupdate -radix hexadecimal /testbench/it/InstrE
+add wave -noupdate -radix hexadecimal /testbench/it/InstrM
+add wave -noupdate -radix hexadecimal /testbench/it/InstrW
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/d
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/q
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/op
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/imm
+add wave -noupdate -radix hexadecimal /testbench/it/edec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/edec/op
+add wave -noupdate -radix hexadecimal /testbench/it/edec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/edec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/edec/imm
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/op
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/imm
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/op
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/imm
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 2} {330314 ns} 0} {{Cursor 3} {330384 ns} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 168
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {330283 ns} {330427 ns}
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 134275b9..a669ce8d 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -3,17 +3,25 @@ quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate -radix ascii /testbench/memfilename
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
 add wave -noupdate -divider <NULL>
 add wave -noupdate /testbench/dut/hart/ebu/IReadF
-add wave -noupdate -expand -group HDU /testbench/dut/hart/DataStall
-add wave -noupdate -expand -group HDU /testbench/dut/hart/InstrStall
-add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/InstrStall
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
 add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
 add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
 add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
@@ -23,17 +31,23 @@ add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/
 add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassF
 add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassD
 add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassE
-add wave -noupdate /testbench/dut/hart/ifu/bpred/InstrF
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
 add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredWrongE
-add wave -noupdate /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate /testbench/dut/hart/ifu/PCF
-add wave -noupdate /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBValidF
-add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/ValidBits
+add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredF
+add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBValidF
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPCIndexQ
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPC
@@ -42,15 +56,38 @@ add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallT
 add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
 add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
 add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
-add wave -noupdate -expand -group BTB -divider Update
-add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
+add wave -noupdate -group BTB -divider Update
+add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group BTB -divider Lookup
+add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
+add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBPredPCF
+add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
+add wave -noupdate /testbench/dut/hart/ifu/bpred/CorrectPCE
+add wave -noupdate /testbench/dut/hart/ifu/bpred/FlushF
+add wave -noupdate /testbench/dut/hart/FlushF
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate /testbench/dut/hart/ieu/c/RegWriteE
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -group {Decode Stage} /testbench/InstrDName
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
+add wave -noupdate /testbench/InstrFName
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {137177 ns} 0}
-quietly wave cursor active 1
+WaveRestoreCursors {{Cursor 2} {332469 ns} 0} {{Cursor 3} {333566 ns} 0} {{Cursor 4} {675 ns} 0}
+quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 185
 configure wave -justifyvalue left
@@ -65,4 +102,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {136946 ns} {137442 ns}
+WaveRestoreZoom {333505 ns} {333689 ns}
diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv
index 7eb116eb..232173ce 100644
--- a/wally-pipelined/src/hazard/hazard.sv
+++ b/wally-pipelined/src/hazard/hazard.sv
@@ -34,7 +34,7 @@ module hazard(
   input  logic       LoadStallD,
   input  logic       InstrStall, DataStall,
   // Stall outputs
-  output logic       StallF, StallD, FlushD, FlushE, FlushM, FlushW
+  output logic       StallF, StallD, FlushF, FlushD, FlushE, FlushM, FlushW
 );
 
   logic BranchFlushDE;
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index 9d676ca8..36fbab68 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -58,7 +58,7 @@ module bpred
   logic [1:0] 		    BPPredF, BPPredD, BPPredE, UpdateBPPredE;
 
   logic [3:0] 		    InstrClassD, InstrClassF, InstrClassE;
-  logic [`XLEN-1:0] 	    BTBPredPCF, RASPCF, BTBPredPCMemoryF;
+  logic [`XLEN-1:0] 	    BTBPredPCF, RASPCF;
   logic 		    TargetWrongE;
   logic 		    FallThroughWrongE;
   logic 		    PredictionDirWrongE;
@@ -71,7 +71,7 @@ module bpred
   // This is probably too much logic. 
   // *** This also encourages me to switch to predicting the class.
 
-  assign InstrClassF[2] = InstrF[6:0] == 7'h67 && InstrF[19:15] == 5'h01; // jump register, but not return
+  assign InstrClassF[2] = InstrF[6:0] == 7'h67 && InstrF[19:15] != 5'h01; // jump register, but not return
   assign InstrClassF[1] = InstrF[6:0] == 7'h6F; // jump
   assign InstrClassF[0] = InstrF[6:0] == 7'h63; // branch
   
@@ -102,7 +102,7 @@ module bpred
   BTBPredictor TargetPredictor(.clk(clk),
 			       .reset(reset),
 			       .LookUpPC(PCNextF),
-			       .TargetPC(BTBPredPCMemoryF),
+			       .TargetPC(BTBPredPCF),
 			       .Valid(BTBValidF),
 			       // update
 			       .UpdateEN(InstrClassE[2] | InstrClassE[1] | InstrClassE[0]),
@@ -111,7 +111,7 @@ module bpred
 
   // need to forward when updating to the same address as reading.
   assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
-  assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCMemoryF;
+  assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
 
   // Part 4 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
@@ -155,7 +155,7 @@ module bpred
   flopenrc #(4) InstrClassRegE(.clk(clk),
 			       .reset(reset),
 			       .en(~StallD),
-			       .clear(flushD),
+			       .clear(FlushD),
 			       .d(InstrClassD),
 			       .q(InstrClassE));
 
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 2824efb5..5de133f2 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -74,7 +74,7 @@ module ifu (
 
   assign PrivilegedChangePCM = RetM | TrapM;
 
-  assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
+  assign StallExceptResolveBranchesF = StallF & ~(SelBPPredF | BPPredWrongE | PrivilegedChangePCM);
 
   //mux3    #(`XLEN) pcmux(PCPlus2or4F, PCCorrectE, PrivilegedNextPCM, {PrivilegedChangePCM, BPPredWrongE}, UnalignedPCNextF);
   mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),

From 9b3637bd8770beca558aaa6766fdd93a888fe6ff Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Fri, 19 Feb 2021 20:09:07 -0600
Subject: [PATCH 09/13] RAS needs to be reset or preloaded.  For now I just
 reset it. Fixed bug with the instruction class. Most tests now pass.  Only
 Wally-JAL and the compressed instruction tests fail.  Currently the bpred
 does not support compressed.  This will be in the next version.

---
 wally-pipelined/regression/wave.do              | 9 +++++++--
 wally-pipelined/src/ifu/RAsPredictor.sv         | 9 +++++++--
 wally-pipelined/src/ifu/bpred.sv                | 2 +-
 wally-pipelined/src/wally/wallypipelinedhart.sv | 2 +-
 4 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index a669ce8d..2890b8b6 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -85,8 +85,13 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
 add wave -noupdate /testbench/InstrFName
+add wave -noupdate -expand -group dcache /testbench/dut/hart/MemAdrM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/MemPAdrM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/ReadDataM
+add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {332469 ns} 0} {{Cursor 3} {333566 ns} 0} {{Cursor 4} {675 ns} 0}
+WaveRestoreCursors {{Cursor 2} {363960 ns} 0} {{Cursor 3} {365915 ns} 0}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 185
@@ -102,4 +107,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {333505 ns} {333689 ns}
+WaveRestoreZoom {365848 ns} {366032 ns}
diff --git a/wally-pipelined/src/ifu/RAsPredictor.sv b/wally-pipelined/src/ifu/RAsPredictor.sv
index d985209b..9090878d 100644
--- a/wally-pipelined/src/ifu/RAsPredictor.sv
+++ b/wally-pipelined/src/ifu/RAsPredictor.sv
@@ -44,6 +44,7 @@ module RASPredictor
 
   logic [StackSize-1:0]     PtrD, PtrQ, PtrP1, PtrM1;
   logic [StackSize-1:0] [`XLEN-1:0] memory;
+  integer 			    index;
   
   assign CounterEn = pop | push | incr;
 
@@ -60,8 +61,12 @@ module RASPredictor
 			   .d(PtrD),
 			   .q(PtrQ));
 
-  always_ff @ (posedge clk) begin
-    if(push) begin
+  // RAS must be reset. 
+  always_ff @ (posedge clk, posedge reset) begin
+    if(reset) begin
+      for(index=0; index<StackSize; index++)
+	memory[index] <= {`XLEN{1'b0}};
+    end else if(push) begin
       memory[PtrP1] <= #1 pushPC;
     end
   end
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index 36fbab68..c589035c 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -67,7 +67,7 @@ module bpred
 
   // Part 1 decode the instruction class.
   // *** for now I'm skiping the compressed instructions
-  assign InstrClassF[3] = InstrF[5:0] == 7'h67 && InstrF[19:15] == 5'h01; // return
+  assign InstrClassF[3] = InstrF[6:0] == 7'h67 && InstrF[19:15] == 5'h01; // return
   // This is probably too much logic. 
   // *** This also encourages me to switch to predicting the class.
 
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 3753c3b1..2edeb902 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -91,7 +91,7 @@ module wallypipelinedhart (
            
   ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
 
-  ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
+  ieu ieu(.*); // integer execution unit: integer register file, datapath and controller
   dmem dmem(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
 
   ahblite ebu( // *** make IRData InstrF

From 37e6a45d762f4171db467dc9f9458e93b3bec9a3 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Fri, 26 Feb 2021 19:43:40 -0600
Subject: [PATCH 10/13] Updating the test bench to include a function radix. 
 Not done.

---
 wally-pipelined/bin/extractFunctionRadix.sh   |  19 +++-
 wally-pipelined/regression/wave.do            | 100 +++++++++++-------
 wally-pipelined/testbench/function_radix.sv   |  84 +++++++++++++++
 .../testbench/testbench-imperas.sv            |   6 +-
 4 files changed, 168 insertions(+), 41 deletions(-)
 create mode 100644 wally-pipelined/testbench/function_radix.sv

diff --git a/wally-pipelined/bin/extractFunctionRadix.sh b/wally-pipelined/bin/extractFunctionRadix.sh
index 1a8ca7f6..0cec0972 100755
--- a/wally-pipelined/bin/extractFunctionRadix.sh
+++ b/wally-pipelined/bin/extractFunctionRadix.sh
@@ -1,10 +1,17 @@
 #!/bin/bash
 
+allProgramRadixFile="FunctionRadix"
+
+index=0
+
 for objDumpFile in "$@";
 do
-
     # get the lines with named labels from the obj files.
-    listOfAddr=`egrep -i '^[0-9]{8} <[0-9a-zA-Z_]+>' $objDumpFile`
+    # 64 bit addresses
+    listOfAddr16=`egrep -i '^[0-9]{16} <[0-9a-zA-Z_]+>' $objDumpFile`
+    # 32 bit addresses
+    listOfAddr8=`egrep -i '^[0-9]{8} <[0-9a-zA-Z_]+>' $objDumpFile`
+    listOfAddr=`echo "$listOfAddr16" "$listOfAddr8"`
 
     # parse out the addresses and the labels
     addresses=`echo "$listOfAddr" | awk '{print $1}'`
@@ -29,4 +36,12 @@ do
     echo "    -default hex -color green" >> $objDumpFile.do
     echo "}" >> $objDumpFile.do
 
+    # now create the all in one version
+    # put the index at the begining of each line
+    allAddresses=`paste -d'\0' <(printf "%04x" "$index") <(echo "$addresses")`
+
+    printf "%04x%s" "$index" "$addresses" >> $allProgramRadixFile.addr
+
+    index=$(($index+1))
+    
 done
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 2890b8b6..3601be0f 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -8,13 +8,13 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
 add wave -noupdate -divider <NULL>
 add wave -noupdate /testbench/dut/hart/ebu/IReadF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/InstrStall
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/InstrStall
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
 add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
 add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
 add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
@@ -22,41 +22,41 @@ add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbe
 add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
 add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
 add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
-add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
-add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
-add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePCIndex
-add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePrediction
-add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
-add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassF
-add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassD
-add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassE
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
+add wave -noupdate -group Bpred -expand -group direction -divider Update
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePrediction
+add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
+add wave -noupdate -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassF
+add wave -noupdate -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassD
+add wave -noupdate -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
 add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredWrongE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/ValidBits
 add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredF
 add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBValidF
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPCIndexQ
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
 add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPC
-add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
-add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
-add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
-add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
-add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
-add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
+add wave -noupdate -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
+add wave -noupdate -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
+add wave -noupdate -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
+add wave -noupdate -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
+add wave -noupdate -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
+add wave -noupdate -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
 add wave -noupdate -group BTB -divider Update
 add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
 add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
@@ -77,6 +77,12 @@ add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/PCLinkW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
 add wave -noupdate /testbench/dut/hart/ieu/c/RegWriteE
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
@@ -90,11 +96,29 @@ add wave -noupdate -expand -group dcache /testbench/dut/hart/MemPAdrM
 add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM
 add wave -noupdate -expand -group dcache /testbench/dut/hart/ReadDataM
 add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/LoadStallD
+add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/dp/WriteDataE
+add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
+add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
+add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
+add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {363960 ns} 0} {{Cursor 3} {365915 ns} 0}
+WaveRestoreCursors {{Cursor 2} {231033 ns} 0} {{Cursor 3} {1276133 ns} 0}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
-configure wave -valuecolwidth 185
+configure wave -valuecolwidth 518
 configure wave -justifyvalue left
 configure wave -signalnamewidth 1
 configure wave -snapdistance 10
@@ -107,4 +131,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {365848 ns} {366032 ns}
+WaveRestoreZoom {1276094 ns} {1276208 ns}
diff --git a/wally-pipelined/testbench/function_radix.sv b/wally-pipelined/testbench/function_radix.sv
new file mode 100644
index 00000000..e13fbfcb
--- /dev/null
+++ b/wally-pipelined/testbench/function_radix.sv
@@ -0,0 +1,84 @@
+// Ross Thompson
+// November 05, 2019
+// Oklahoma State University
+
+module function_radix();
+
+   parameter PRELOAD_FILE = "funct_addr.txt";
+
+   integer memory_bank [];
+   integer index;
+
+   logic [`XLEN-1:0] pc;
+   
+   initial begin
+     $init_signal_spy("/riscv_mram_tb/dut/pc", "/riscv_mram_tb/function_radix/pc");
+   end
+
+   task automatic bin_search_min;
+      input integer pc;
+      input integer length;
+      ref integer   array [];
+      output integer minval;
+
+      integer 	     left, right;
+      integer 	     mid;
+
+      begin
+	 left = 0;
+	 right = length;
+	 while (left <= right) begin
+	    mid = left + ((right - left) / 2);
+	    if (array[mid] == pc) begin
+	       minval = array[mid];
+	       return;
+            end
+	    if (array[mid] < pc) begin
+	      left = mid + 1;
+	    end else begin
+	      right = mid -1;
+	    end
+	 end // while (left <= right)
+	 // if the element pc is now found, right and left will be equal at this point.
+	 // we need to check if pc is less than the array at left or greather.
+	 // if it is less than pc, then we select left as the index.
+	 // if it is greather we want 1 less than left.
+	 if (array[left] < pc) begin
+	    minval = array[left];
+	    return;	    
+	 end else begin
+	    minval = array[left-1];
+	    return;
+	 end
+      end
+   endtask
+
+   
+   // preload
+   initial $readmemh(PRELOAD_FILE, memory_bank);
+
+   // we need to count the number of lines in the file so we can set line_count.
+   integer fp;
+   integer line_count = 0;
+   logic [31:0] line;
+   initial begin
+      fp = $fopen(PRELOAD_FILE, "r");
+      // read line by line to count lines
+      if (fp) begin
+	 while (! $feof(fp)) begin
+	    $fscanf(fp, "%h\n", line);
+	    line_count = line_count + 1;
+	 end
+      end else begin
+	 $display("Cannot open file %s for reading.", PRELOAD_FILE);
+	 $stop;
+      end
+   end
+
+   always @(pc) begin
+      bin_search_min(pc, line_count, memory_bank, index);
+      
+   end
+
+endmodule // function_radix
+
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 91e32059..38b9a6d7 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -405,7 +405,11 @@ string tests32i[] = {
           reset = 1; # 17; reset = 0;
         end
       end
-    end
+    end // always @ (negedge clk)
+
+  // track the current function or label
+  function_rfunction_radix function_radix();
+  
 endmodule
 
 /* verilator lint_on STMTDLY */

From 7592a0dacb5757a7960ddc3faff0ea23575f684c Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Fri, 26 Feb 2021 20:12:27 -0600
Subject: [PATCH 11/13] Shreya and I found a bug with the exeuction of JAL and
 JALR instructions.  The link was only set in the writeback stage.  Once the
 branch predictor started correctly predicting JAL(R)s the ALU and forwarding
 logic need to have the PCLinkE at the execution stage in case an instruction
 in the next two clocks need the data.

---
 wally-pipelined/regression/wave.do              |  2 +-
 wally-pipelined/src/ieu/controller.sv           |  3 ++-
 wally-pipelined/src/ieu/datapath.sv             | 10 ++++++++--
 wally-pipelined/src/ieu/ieu.sv                  |  2 ++
 wally-pipelined/src/ifu/bpred.sv                |  5 +++--
 wally-pipelined/src/ifu/ifu.sv                  |  5 +++--
 wally-pipelined/src/wally/wallypipelinedhart.sv |  2 +-
 wally-pipelined/testbench/testbench-imperas.sv  |  2 +-
 8 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 3601be0f..636d4095 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -115,7 +115,7 @@ add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/
 add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
 add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {231033 ns} 0} {{Cursor 3} {1276133 ns} 0}
+WaveRestoreCursors {{Cursor 2} {231033 ns} 0} {{Cursor 3} {1276117 ns} 0}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 518
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 5a62f014..0edb40fe 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -44,6 +44,7 @@ module controller(
   output logic 	     ALUSrcAE, ALUSrcBE,
   output logic       TargetSrcE,
   output logic       MemReadE,  // for Hazard Unit
+  output logic       JumpE,
   // Memory stage control signals
   input  logic       FlushM,
   input  logic       DataMisalignedM,
@@ -64,7 +65,7 @@ module controller(
   logic 	    RegWriteD, RegWriteE;
   logic [1:0] ResultSrcD, ResultSrcE, ResultSrcM;
   logic [1:0] MemRWD, MemRWE;
-  logic		    JumpD, JumpE;
+  logic		    JumpD;
   logic		    BranchD, BranchE;
   logic	[1:0] ALUOpD;
   logic [4:0] ALUControlD;
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index bb02bad5..5499e57f 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -38,7 +38,9 @@ module datapath (
   input  logic [4:0]       ALUControlE,
   input  logic             ALUSrcAE, ALUSrcBE,
   input  logic             TargetSrcE, 
+  input  logic             JumpE,
   input  logic [`XLEN-1:0] PCE,
+  input  logic [`XLEN-1:0] PCLinkE,
   output logic [2:0]       FlagsE,
   output logic [`XLEN-1:0] PCTargetE,
   // Memory stage signals
@@ -67,7 +69,7 @@ module datapath (
   // Execute stage signals
   logic [`XLEN-1:0] RD1E, RD2E;
   logic [`XLEN-1:0] ExtImmE;
-  logic [`XLEN-1:0] PreSrcAE, SrcAE, SrcBE;
+  logic [`XLEN-1:0] PreSrcAE, SrcAE, SrcBE, SrcAE2, SrcBE2;
   logic [`XLEN-1:0] ALUResultE;
   logic [`XLEN-1:0] WriteDataE;
   logic [`XLEN-1:0] TargetBaseE;
@@ -95,8 +97,10 @@ module datapath (
   mux3  #(`XLEN)  faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE);
   mux3  #(`XLEN)  fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
   mux2  #(`XLEN)  srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE);
+  mux2  #(`XLEN)  srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);  
   mux2  #(`XLEN)  srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE);
-  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, ALUResultE, FlagsE);
+  mux2  #(`XLEN)  srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
+  alu   #(`XLEN)  alu(SrcAE2, SrcBE2, ALUControlE, ALUResultE, FlagsE);
   mux2  #(`XLEN)  targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
   assign  PCTargetE = ExtImmE + TargetBaseE;
 
@@ -111,5 +115,7 @@ module datapath (
   floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
   floprc #(5)    RdWEg(clk, reset, FlushW, RdM, RdW);
 
+  // This mux4:1 no longer needs to include PCLinkW.  This is set correctly in the execution stage.
+  // *** need to look at how the decoder is coded to fix.
   mux4  #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRReadValW, ResultSrcW, ResultW);	
 endmodule
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index 7ed4bdff..2e3dbc85 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -33,6 +33,7 @@ module ieu (
   output logic             IllegalBaseInstrFaultD,
   // Execute Stage interface
   input  logic [`XLEN-1:0] PCE, 
+  input  logic [`XLEN-1:0] PCLinkE,
   output logic [`XLEN-1:0] PCTargetE,
   // Memory stage interface
   input  logic             DataMisalignedM,
@@ -68,6 +69,7 @@ module ieu (
   logic [1:0]       ForwardAE, ForwardBE;
   logic             RegWriteM, RegWriteW;
   logic             MemReadE;
+  logic             JumpE;
            
   controller c(.OpD(InstrD[6:0]), .Funct3D(InstrD[14:12]), .Funct7b5D(InstrD[30]), .*);
   datapath   dp(.*);             
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index c589035c..e6ed30b3 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -78,6 +78,7 @@ module bpred
   // Part 2 branch direction prediction
 
   twoBitPredictor DirPredictor(.clk(clk),
+			       .reset(reset),
 			       .LookUpPC(PCNextF),
 			       .Prediction(BPPredF),
 			       // update
@@ -110,8 +111,8 @@ module bpred
 			       .UpdateTarget(PCTargetE));
 
   // need to forward when updating to the same address as reading.
-  assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
-  assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
+  //assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
+  //assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
 
   // Part 4 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 5de133f2..317a1da2 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -36,10 +36,11 @@ module ifu (
   // Decode  
   output logic 		   InstrStall,
   // Execute
+  output logic [`XLEN-1:0] PCLinkE,
   input logic 		   PCSrcE, 
   input logic [`XLEN-1:0]  PCTargetE,
   output logic [`XLEN-1:0] PCE,
-  output logic BPPredWrongE,		   
+  output logic 		   BPPredWrongE, 
   // Mem
   input logic 		   RetM, TrapM, 
   input logic [`XLEN-1:0]  PrivilegedNextPCM, 
@@ -58,7 +59,7 @@ module ifu (
   logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
   logic StallExceptResolveBranchesF, PrivilegedChangePCM;
   logic IllegalCompInstrD;
-  logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM;
+  logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkM;
   logic        CompressedF;
   logic [31:0]     InstrRawD, InstrE;
   logic [31:0]     nop = 32'h00000013; // instruction for NOP
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 2edeb902..9cce4559 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -57,7 +57,7 @@ module wallypipelinedhart (
   logic [`XLEN-1:0] SrcAM;
 //  logic [31:0] InstrF;
   logic [31:0] InstrD, InstrM;
-  logic [`XLEN-1:0] PCE, PCM, PCLinkW;
+  logic [`XLEN-1:0] PCE, PCM, PCLinkE, PCLinkW;
   logic [`XLEN-1:0] PCTargetE;
   logic [`XLEN-1:0] CSRReadValW;
   logic [`XLEN-1:0] PrivilegedNextPCM;
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 38b9a6d7..343791ae 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -408,7 +408,7 @@ string tests32i[] = {
     end // always @ (negedge clk)
 
   // track the current function or label
-  function_rfunction_radix function_radix();
+  //function_rfunction_radix function_radix();
   
 endmodule
 

From 52d95d415fd4bb2fa49c120f50517172870a5b35 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Thu, 4 Mar 2021 09:23:35 -0600
Subject: [PATCH 12/13] Converted to using the BTB to predict the instruction
 class.

---
 wally-pipelined/src/ifu/BTBPredictor.sv | 22 ++++++------
 wally-pipelined/src/ifu/bpred.sv        | 47 +++++++++++--------------
 wally-pipelined/src/ifu/ifu.sv          | 20 +++++++++--
 3 files changed, 50 insertions(+), 39 deletions(-)

diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv
index 041f2b64..4a78353f 100644
--- a/wally-pipelined/src/ifu/BTBPredictor.sv
+++ b/wally-pipelined/src/ifu/BTBPredictor.sv
@@ -35,11 +35,13 @@ module BTBPredictor
    input logic 		    reset,
    input logic [`XLEN-1:0]  LookUpPC,
    output logic [`XLEN-1:0] TargetPC,
+   output logic [3:0] 	    InstrClass,
    output logic 	    Valid,
    // update
    input logic 		    UpdateEN,
    input logic [`XLEN-1:0]  UpdatePC,
-   input logic [`XLEN-1:0]  UpdateTarget
+   input logic [`XLEN-1:0]  UpdateTarget,
+   input logic [3:0] 	    UpdateInstrClass
    );
 
   localparam TotalDepth = 2 ** Depth;
@@ -82,15 +84,15 @@ module BTBPredictor
   // and other indirection branch data.
   // Another optimization may be using a PC relative address.
 
-  SRAM2P1R1W #(Depth, `XLEN) memory(.clk(clk),
-				    .reset(reset),
-				    .RA1(LookUpPCIndex),
-				    .RD1(TargetPC),
-				    .REN1(1'b1),
-				    .WA1(UpdatePCIndex),
-				    .WD1(UpdateTarget),
-				    .WEN1(UpdateEN),
-				    .BitWEN1({`XLEN{1'b1}}));
+  SRAM2P1R1W #(Depth, `XLEN+4) memory(.clk(clk),
+				      .reset(reset),
+				      .RA1(LookUpPCIndex),
+				      .RD1({{InstrClass, TargetPC}}),
+				      .REN1(1'b1),
+				      .WA1(UpdatePCIndex),
+				      .WD1({UpdateInstrClass, UpdateTarget}),
+				      .WEN1(UpdateEN),
+				      .BitWEN1({`XLEN{1'b1}}));
 
 
 endmodule
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index e6ed30b3..613120c0 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -36,9 +36,6 @@ module bpred
    input logic [`XLEN-1:0]  PCNextF, // *** forgot to include this one on the I/O list
    output logic [`XLEN-1:0] BPPredPCF,
    output logic 	    SelBPPredF,
-   input logic [31:0] 	    InstrF, // we are going to use the opcode to indicate what type instruction this is.
-   // if this is too slow we will have to predict the type of instruction.
-   // Execute state
    // Update Predictor
    input logic [`XLEN-1:0]  PCE, // The address of the currently executing instruction
    // 1 hot encoding
@@ -50,6 +47,7 @@ module bpred
    input logic [`XLEN-1:0]  PCTargetE, // The branch destination if the branch is taken.
    input logic [`XLEN-1:0]  PCD, // The address the branch predictor took.
    input logic [`XLEN-1:0]  PCLinkE, // The address following the branch instruction. (AKA Fall through address)
+   input logic [3:0] 	    InstrClassE,
    // Report branch prediction status
    output logic 	    BPPredWrongE
    );
@@ -57,7 +55,7 @@ module bpred
   logic 		    BTBValidF;
   logic [1:0] 		    BPPredF, BPPredD, BPPredE, UpdateBPPredE;
 
-  logic [3:0] 		    InstrClassD, InstrClassF, InstrClassE;
+  logic [3:0] 		    BPInstrClassF, BPInstrClassD, BPInstrClassE;
   logic [`XLEN-1:0] 	    BTBPredPCF, RASPCF;
   logic 		    TargetWrongE;
   logic 		    FallThroughWrongE;
@@ -65,17 +63,8 @@ module bpred
   logic 		    PredictionPCWrongE;
   logic [`XLEN-1:0] 	    CorrectPCE;
 
-  // Part 1 decode the instruction class.
-  // *** for now I'm skiping the compressed instructions
-  assign InstrClassF[3] = InstrF[6:0] == 7'h67 && InstrF[19:15] == 5'h01; // return
-  // This is probably too much logic. 
-  // *** This also encourages me to switch to predicting the class.
 
-  assign InstrClassF[2] = InstrF[6:0] == 7'h67 && InstrF[19:15] != 5'h01; // jump register, but not return
-  assign InstrClassF[1] = InstrF[6:0] == 7'h6F; // jump
-  assign InstrClassF[0] = InstrF[6:0] == 7'h63; // branch
-  
-  // Part 2 branch direction prediction
+  // Part 1 branch direction prediction
 
   twoBitPredictor DirPredictor(.clk(clk),
 			       .reset(reset),
@@ -91,40 +80,42 @@ module bpred
   // 2) Any information which is necessary for the predictor to built it's next state.
   // For a 2 bit table this is the prediction count.
 
-  assign SelBPPredF = ((InstrClassF[0] & BPPredF[1] & BTBValidF) | 
-		       InstrClassF[3] |
-		       (InstrClassF[2] & BTBValidF) | 
-		       InstrClassF[1] & BTBValidF) ;
+  assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | 
+		       BPInstrClassF[3] |
+		       (BPInstrClassF[2] & BTBValidF) | 
+		       BPInstrClassF[1] & BTBValidF) ;
 
 
-  // Part 3 Branch target address prediction
+  // Part 2 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
 
   BTBPredictor TargetPredictor(.clk(clk),
 			       .reset(reset),
 			       .LookUpPC(PCNextF),
 			       .TargetPC(BTBPredPCF),
+			       .InstrClass(BPInstrClassF),
 			       .Valid(BTBValidF),
 			       // update
 			       .UpdateEN(InstrClassE[2] | InstrClassE[1] | InstrClassE[0]),
 			       .UpdatePC(PCE),
-			       .UpdateTarget(PCTargetE));
+			       .UpdateTarget(PCTargetE),
+			       .UpdateInstrClass(InstrClassE));
 
   // need to forward when updating to the same address as reading.
   //assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
   //assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
 
-  // Part 4 RAS
+  // Part 3 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
   RASPredictor RASPredictor(.clk(clk),
 			    .reset(reset),
-			    .pop(InstrClassF[3]),
+			    .pop(BPInstrClassF[3]),
 			    .popPC(RASPCF),
 			    .push(InstrClassE[3]),
 			    .incr(1'b0),
 			    .pushPC(PCLinkE));
 
-  assign BPPredPCF = InstrClassF[3] ? RASPCF : BTBPredPCF;
+  assign BPPredPCF = BPInstrClassF[3] ? RASPCF : BTBPredPCF;
   
   
 
@@ -150,15 +141,17 @@ module bpred
 			       .reset(reset),
 			       .en(~StallF),
 			       .clear(FlushF),
-			       .d(InstrClassF),
-			       .q(InstrClassD));
+			       .d(BPInstrClassF),
+			       .q(BPInstrClassD));
 
   flopenrc #(4) InstrClassRegE(.clk(clk),
 			       .reset(reset),
 			       .en(~StallD),
 			       .clear(FlushD),
-			       .d(InstrClassD),
-			       .q(InstrClassE));
+			       .d(BPInstrClassD),
+			       .q(BPInstrClassE));
+
+  
 
   // Check the prediction makes execution.
   assign TargetWrongE = PCTargetE != PCD;
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 317a1da2..ccd481f8 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -67,6 +67,8 @@ module ifu (
   // branch predictor signals
   logic 	   SelBPPredF;
   logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F;
+  logic [3:0] 	    InstrClassD, InstrClassE;
+  
   
 
   // *** put memory interface on here, InstrF becomes output
@@ -109,13 +111,12 @@ module ifu (
 	      .PCNextF(PCNextF),
 	      .BPPredPCF(BPPredPCF),
 	      .SelBPPredF(SelBPPredF),
-	      .InstrF(InstrF), // *** this is flushed internally. The logic is redundant with some out here.
-	      // Also I believe this port will be removed.
 	      .PCE(PCE),
 	      .PCSrcE(PCSrcE),
 	      .PCTargetE(PCTargetE),
 	      .PCD(PCD),
 	      .PCLinkE(PCLinkE),
+	      .InstrClassE(InstrClassE),
 	      .BPPredWrongE(BPPredWrongE));
   // The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE.
   assign PCCorrectE =  PCSrcE ? PCTargetE : PCLinkE;
@@ -142,6 +143,14 @@ module ifu (
   assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
   // *** combine these with others in better way, including M, F
 
+
+  // the branch predictor needs a compact decoding of the instruction class.
+  // *** consider adding in the alternate return address x5 for returns.
+  assign InstrClassD[3] = InstrD[6:0] == 7'h67 && InstrD[19:15] == 5'h01; // return
+  assign InstrClassD[2] = InstrD[6:0] == 7'h67 && InstrD[19:15] != 5'h01; // jump register, but not return
+  assign InstrClassD[1] = InstrD[6:0] == 7'h6F; // jump
+  assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
+
   // Misaligned PC logic
 
   generate
@@ -164,6 +173,13 @@ module ifu (
   flopr #(`XLEN) PCMReg(clk, reset, PCE, PCM);
   flopr #(`XLEN) PCWReg(clk, reset, PCM, PCW); // *** probably not needed; delete later
 
+  flopenrc #(4) InstrClassRegE(.clk(clk),
+			       .reset(reset),
+			       .en(~StallD),
+			       .clear(FlushD),
+			       .d(InstrClassD),
+			       .q(InstrClassE));
+
   // seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.  
   // either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or
   // have dedicated adder in Mem stage based on PCM + 2 or 4

From 4d14c714a744a2892543ec063f31c17fed208501 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Thu, 4 Mar 2021 13:01:41 -0600
Subject: [PATCH 13/13] Fixed forwarding around the 2 bit predictor.

---
 wally-pipelined/src/ifu/BTBPredictor.sv    |  3 +--
 wally-pipelined/src/ifu/twoBitPredictor.sv | 20 ++++++++++++++++++--
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv
index 4a78353f..85cb586c 100644
--- a/wally-pipelined/src/ifu/BTBPredictor.sv
+++ b/wally-pipelined/src/ifu/BTBPredictor.sv
@@ -80,9 +80,8 @@ module BTBPredictor
   assign Valid = ValidBits[LookUpPCIndexQ];
 
   // the BTB contains the target address.
-  // *** future version may contain the instruction class, a tag or partial tag,
-  // and other indirection branch data.
   // Another optimization may be using a PC relative address.
+  // *** need to add forwarding.
 
   SRAM2P1R1W #(Depth, `XLEN+4) memory(.clk(clk),
 				      .reset(reset),
diff --git a/wally-pipelined/src/ifu/twoBitPredictor.sv b/wally-pipelined/src/ifu/twoBitPredictor.sv
index 704d7fb0..f01f48dc 100644
--- a/wally-pipelined/src/ifu/twoBitPredictor.sv
+++ b/wally-pipelined/src/ifu/twoBitPredictor.sv
@@ -31,7 +31,7 @@ module twoBitPredictor
   #(parameter int Depth = 10
     )
   (input logic clk,
-   input logic reset,
+   input logic 		   reset,
    input logic [`XLEN-1:0] LookUpPC,
    output logic [1:0] 	   Prediction,
    // update
@@ -42,6 +42,8 @@ module twoBitPredictor
 
   logic [Depth-1:0] 	   LookUpPCIndex, UpdatePCIndex;
   logic [1:0] 		   PredictionMemory;
+  logic 		   DoForwarding, DoForwardingF;
+  logic [1:0] 		   UpdatePredictionF;
   
 
   // hashing function for indexing the PC
@@ -63,6 +65,20 @@ module twoBitPredictor
 				.BitWEN1(2'b11));
 
   // need to forward when updating to the same address as reading.
-  assign Prediction = (UpdatePC == LookUpPC) ? UpdatePrediction : PredictionMemory;
+  // first we compare to see if the update and lookup addreses are the same
+  assign DoForwarding = UpdatePCIndex == LookUpPCIndex;
+
+  // register the update value and the forwarding signal into the Fetch stage
+  flopr #(1) DoForwardingReg(.clk(clk),
+			     .reset(reset),
+			     .d(DoForwarding),
+			     .q(DoForwardingF));
+  
+  flopr #(2) UpdatePredictionReg(.clk(clk),
+				 .reset(reset),
+				 .d(UpdatePrediction),
+				 .q(UpdatePredictionF));
+
+  assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory;
   
 endmodule