diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index 20519bbb..8bb8ad21 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -82,7 +82,7 @@ for test in tests32gc:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c", "wally32periph"] 
+tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c"] 
 for test in tests32ic:
   tc = TestCase(
         name=test,
@@ -100,6 +100,15 @@ for test in tests32e:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
+ahbTests = [("0", "0"), ("0", "1"), ("1", "0"), ("1", "1"), ("2", "0"), ("2", "1")] 
+for test in ahbTests:
+  tc = TestCase(
+        name="RAM_LATENCH_" + test[0] + "_BURST_EN_" + test[1],
+        variant="ahb",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+  
 
 import os
 from multiprocessing import Pool, TimeoutError
diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do
index d36a95ee..146ab04c 100644
--- a/pipelined/regression/wally-pipelined-batch.do
+++ b/pipelined/regression/wally-pipelined-batch.do
@@ -55,6 +55,20 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     run -all
     exec ./slack-notifier/slack-notifier.py
 
+} elseif {$2 eq "ahb"} {
+    vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596  +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+    # start and run simulation
+    # remove +acc flag for faster sim during regressions if there is no need to access internal signals
+    vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
+    vsim -lib wkdir/work_${1}_${2}_${3}_${4} testbenchopt  -fatal 7
+    # Adding coverage increases runtime from 2:00 to 4:29.  Can't run it all the time
+    #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
+    #vsim -coverage -lib work_$2 workopt_$2
+
+    # power add generates the logging necessary for said generation.
+    # power add -r /dut/core/*
+    run -all
+    # power off -r /dut/core/*
 } else {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
     # start and run simulation
diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do
index 4de37ec4..fe17bd57 100644
--- a/pipelined/regression/wally-pipelined.do
+++ b/pipelined/regression/wally-pipelined.do
@@ -76,7 +76,11 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     run 20 ms
 
 } else {
-    vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
+    if {$2 eq "ahb"} {
+        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+    } else {
+        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
+    }
     vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
 
     vsim workopt +nowarn3829  -fatal 7
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 57d1ab22..db27aa2f 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -104,6 +104,7 @@ logic [3:0] dummy;
         "wally64periph":                  tests = wally64periph;
         "coremark":                       tests = coremark;
         "fpga":                           tests = fpga;
+        "ahb" :                           tests = ahb;
       endcase 
     end else begin // RV32
       case (TEST)
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index 5ce84f53..d4976736 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -1917,3 +1917,8 @@ string imperas32f[] = '{
     `WALLYTEST,
     "NULL"
  };
+
+ string ahb[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/F/src/fadd_b11-01.S"
+ };