From 3ce82f93c0064c401d226c7c1a1530392ce33959 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 22:12:04 -0700 Subject: [PATCH 1/6] added premilinary boundary ccrossing cases --- .../references/WALLY-pmp-01.reference_output | 8 +++++- .../rv64i_m/privilege/src/WALLY-pmp-01.S | 26 ++++++++++++------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output index ea5a0cb1..031d8797 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output @@ -1,6 +1,6 @@ 0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 00000000 -20040000 # writeback of value written to PMPADDR1 +20040001 # writeback of value written to PMPADDR1 00000000 2004003f # writeback of value written to PMPADDR2 00000000 @@ -26,6 +26,12 @@ 00000000 00000bad 00000000 +00000005 # read test with access fault when access begins in allowed region and ends in protected NA region +00000000 +00000bad +00000000 +00000007 # write test with access fault when access begins in allowed region and ends in protected TOR region +00000000 00600dbb # read test success from region with L=X=W=R=0 00000000 0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S index fc3864d3..dcc2a2dc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S @@ -60,18 +60,19 @@ test_cases: # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written. # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | -.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | -.8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | -.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | -.8byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | -.8byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | +.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1B | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | +.8byte 0x1, 0x20040001, write_pmpaddr_1 # | 1 | 0x20040001 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100004-801000FF R | +.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 16 | 0 | NA4 | 1 | 1 | 0 | 80100200-80100203 XW | +.8byte 0x4, 0x20040081, write_pmpaddr_4 # | 4 | 0x20040081 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x5, 0x20040084, write_pmpaddr_5 # | 5 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100204-80100210 X | +.8byte 0x5, 0x200400C1, write_pmpaddr_6 # | 6 | 0x200400C1 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100304-80100307 locked out | +.8byte 0x6, 0x2004013F, write_pmpaddr_7 # | 7 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | # Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes. .8byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. -.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001F +.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001B .8byte 0x2, 0x1F00000000000000, write_pmpcfg_2 # write pmpcfg2, output 0x1F00000000000000 # write known values to memory where W=0. This should be possible since we're in machine mode. @@ -90,7 +91,14 @@ test_cases: # Test 12.3.2.2.2 Machine mode access -.8byte 0x80100300, 0x0, read64_test # access fault to region with L=1, R=0 +.8byte 0x80100304, 0x0, read32_test # access fault to region with L=1, R=0 + +# accesses across PMP region boundaries +.8byte 0x80100300, 0x0, read64_test # access fault when access begins in allowed NA region and goes into protected region. + +.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. +.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. + .8byte 0x80100400, 0x0, read64_test # successful access to region with L=X=W=R=0 # Test 12.3.2.2.3 System mode access From 3c6b85606896179c6771685354c9c243d55b5392 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:08:39 -0700 Subject: [PATCH 2/6] Added cause_s_soft_from_m_interrupt --- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 00e235f3..85b5ab8c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -162,6 +162,11 @@ cause_s_soft_interrupt: csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. ret +cause_s_soft_from_m_interrupt: + li t3, 0x2 + csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + ret + cause_m_ext_interrupt: // ========== Configure PLIC ========== li a3, 0x40 From f0027aef2365176b10949702a3ead7770ec55e16 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:09:43 -0700 Subject: [PATCH 3/6] replaced inerrupt tests with allowed versions --- .../privilege/references/WALLY-trap-s-01.reference_output | 8 -------- .../rv64i_m/privilege/src/WALLY-stvec-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-trap-01.S | 4 ++-- .../rv64i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- 4 files changed, 6 insertions(+), 14 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index fe559dfb..cdc88369 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -60,14 +60,6 @@ 00000000 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -0007ec01 # value to indicate successful vectoring on s soft interrupt -00000000 -00000001 # scause value from s soft interrupt -80000000 -00000000 # stval for ssoft interrupt (0x0) -00000000 -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 0007ec03 # value to indicate successful vectoring on m soft interrupt 00000000 00000003 # scause value from m soft interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S index 4a4bdb76..05ecf515 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -49,7 +49,7 @@ jal cause_s_soft_interrupt // only cause one interrupt since we just want to tes GOTO_M_MODE -jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode +jal cause_s_soft_from_m_interrupt // set software interrupt pending without it firing so we can make it fire in U mode GOTO_U_MODE // Should cause software interrupt to fire off. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 41d9cd07..b44b6440 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -50,7 +50,7 @@ GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -jal cause_s_soft_interrupt +jal cause_s_soft_from_m_interrupt jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt @@ -72,7 +72,7 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall // M mode ecall -jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. +jal cause_s_soft_interrupt // S Mode Interrupts Ignored in M mode. sip writeable when mideleg = 1 jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index cfe02f3a..525e7927 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -56,12 +56,12 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -// some interrupts excluded becaus writing MIP is illegal from S mode -jal cause_s_soft_interrupt +// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9) +//jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO li a3, 0x40 jal cause_m_ext_interrupt From e949d3dc4bac0e3119d078dc015ab80e92a310d7 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:16:57 -0700 Subject: [PATCH 4/6] ported fixes to 32 bit tests --- .../privilege/references/WALLY-trap-s-01.reference_output | 4 ---- .../rv32i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 089aeba9..5ee52bee 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -29,10 +29,6 @@ 00000008 # scause from U mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 -0007ec01 # value to indicate successful vectoring on s soft interrupt -80000001 # scause value from s soft interrupt -00000000 # stval for ssoft interrupt (0x0) -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 0007ec03 # value to indicate successful vectoring on m soft interrupt 80000003 # scause value from m soft interrupt 00000000 # stval for msoft interrupt (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 4b1e2afa..85758b10 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -// some interrupts excluded becaus writing MIP is illegal from S mode -jal cause_s_soft_interrupt +// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9) +//jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO li a3, 0x40 jal cause_m_ext_interrupt From 60b2d77c289cb24e3619201f17e3e93644e3bd89 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:18:31 -0700 Subject: [PATCH 5/6] added working tests back into regression --- testbench/tests.vh | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 64b5ca59..93c1d7ea 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1852,7 +1852,6 @@ string arch64zbs[] = '{ string wally64priv[] = '{ `WALLYTEST, -// "rv64i_m/privilege/src/BUG66", "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S", "rv64i_m/privilege/src/WALLY-mie-01.S", @@ -1863,15 +1862,15 @@ string arch64zbs[] = '{ "rv64i_m/privilege/src/WALLY-mtvec-01.S", "rv64i_m/privilege/src/WALLY-pma-01.S", "rv64i_m/privilege/src/WALLY-pmp-01.S", -// "rv64i_m/privilege/src/WALLY-sie-01.S", + "rv64i_m/privilege/src/WALLY-sie-01.S", "rv64i_m/privilege/src/WALLY-status-mie-01.S", -// "rv64i_m/privilege/src/WALLY-status-sie-01.S", + "rv64i_m/privilege/src/WALLY-status-sie-01.S", "rv64i_m/privilege/src/WALLY-status-tw-01.S", "rv64i_m/privilege/src/WALLY-status-tvm-01.S", "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S", -// "rv64i_m/privilege/src/WALLY-stvec-01.S", -// "rv64i_m/privilege/src/WALLY-trap-01.S", -// "rv64i_m/privilege/src/WALLY-trap-s-01.S", + "rv64i_m/privilege/src/WALLY-stvec-01.S", + "rv64i_m/privilege/src/WALLY-trap-01.S", + "rv64i_m/privilege/src/WALLY-trap-s-01.S", "rv64i_m/privilege/src/WALLY-trap-sret-01.S", "rv64i_m/privilege/src/WALLY-trap-u-01.S", "rv64i_m/privilege/src/WALLY-wfi-01.S", @@ -1951,15 +1950,15 @@ string arch64zbs[] = '{ "rv32i_m/privilege/src/WALLY-mtvec-01.S", "rv32i_m/privilege/src/WALLY-pma-01.S", "rv32i_m/privilege/src/WALLY-pmp-01.S", -// "rv32i_m/privilege/src/WALLY-sie-01.S", + "rv32i_m/privilege/src/WALLY-sie-01.S", "rv32i_m/privilege/src/WALLY-status-mie-01.S", -// "rv32i_m/privilege/src/WALLY-status-sie-01.S", + "rv32i_m/privilege/src/WALLY-status-sie-01.S", "rv32i_m/privilege/src/WALLY-status-tw-01.S", "rv32i_m/privilege/src/WALLY-status-tvm-01.S", "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S", -// "rv32i_m/privilege/src/WALLY-stvec-01.S", -// "rv32i_m/privilege/src/WALLY-trap-01.S", -// "rv32i_m/privilege/src/WALLY-trap-s-01.S", + "rv32i_m/privilege/src/WALLY-stvec-01.S", + "rv32i_m/privilege/src/WALLY-trap-01.S", + "rv32i_m/privilege/src/WALLY-trap-s-01.S", "rv32i_m/privilege/src/WALLY-trap-sret-01.S", "rv32i_m/privilege/src/WALLY-trap-u-01.S", "rv32i_m/privilege/src/WALLY-wfi-01.S", From b856698ce24a25e250064c8901fe61653201108a Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 24 Mar 2023 11:27:41 -0700 Subject: [PATCH 6/6] Revert "added premilinary boundary ccrossing cases" This reverts commit 3ce82f93c0064c401d226c7c1a1530392ce33959. --- .../references/WALLY-pmp-01.reference_output | 8 +----- .../rv64i_m/privilege/src/WALLY-pmp-01.S | 26 +++++++------------ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output index 031d8797..ea5a0cb1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output @@ -1,6 +1,6 @@ 0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 00000000 -20040001 # writeback of value written to PMPADDR1 +20040000 # writeback of value written to PMPADDR1 00000000 2004003f # writeback of value written to PMPADDR2 00000000 @@ -26,12 +26,6 @@ 00000000 00000bad 00000000 -00000005 # read test with access fault when access begins in allowed region and ends in protected NA region -00000000 -00000bad -00000000 -00000007 # write test with access fault when access begins in allowed region and ends in protected TOR region -00000000 00600dbb # read test success from region with L=X=W=R=0 00000000 0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S index dcc2a2dc..fc3864d3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S @@ -60,19 +60,18 @@ test_cases: # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written. # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | -.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1B | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | -.8byte 0x1, 0x20040001, write_pmpaddr_1 # | 1 | 0x20040001 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100004-801000FF R | -.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 16 | 0 | NA4 | 1 | 1 | 0 | 80100200-80100203 XW | -.8byte 0x4, 0x20040081, write_pmpaddr_4 # | 4 | 0x20040081 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x5, 0x20040084, write_pmpaddr_5 # | 5 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100204-80100210 X | -.8byte 0x5, 0x200400C1, write_pmpaddr_6 # | 6 | 0x200400C1 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100304-80100307 locked out | -.8byte 0x6, 0x2004013F, write_pmpaddr_7 # | 7 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | +.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | +.8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | +.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | +.8byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | +.8byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | # Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes. .8byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. -.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001B +.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001F .8byte 0x2, 0x1F00000000000000, write_pmpcfg_2 # write pmpcfg2, output 0x1F00000000000000 # write known values to memory where W=0. This should be possible since we're in machine mode. @@ -91,14 +90,7 @@ test_cases: # Test 12.3.2.2.2 Machine mode access -.8byte 0x80100304, 0x0, read32_test # access fault to region with L=1, R=0 - -# accesses across PMP region boundaries -.8byte 0x80100300, 0x0, read64_test # access fault when access begins in allowed NA region and goes into protected region. - -.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. -.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. - +.8byte 0x80100300, 0x0, read64_test # access fault to region with L=1, R=0 .8byte 0x80100400, 0x0, read64_test # successful access to region with L=X=W=R=0 # Test 12.3.2.2.3 System mode access