From 6299c0ef0ba3fc1cbbef840c29f90bd814865803 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 25 Apr 2023 20:30:46 -0700 Subject: [PATCH] Cacheway Exclude FlushStage=1 when SetValidWay=1 We determined that this case is not hit even for i$, so this case is also excluded separately for i$. It could be a better idea to remove the ~FlushStage check completely (if we're sure). My reasoning for this one is written as a comment in the exclusion script: since a pipeline stall is asserted by the cache in the fetch stage (which happens before going into the WRITE_LINE state and asserting SetValidWay), there seems to be no way to trigger a FlushStage (FlushW for D$) while the stallM is active. --- sim/coverage-exclusions-rv64gc.do | 6 +++++- src/cache/cacheway.sv | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 3db7d049..241c9b06 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -77,7 +77,7 @@ for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1 coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6 # below: flushD can't go high during an icache write b/c of pipeline stall - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 } ## D$ Exclusions. @@ -89,6 +89,10 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 + + # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before + # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW. + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 } # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 095b8c1d..f504f40a 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -102,7 +102,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay assign ClearDirtyWay = ClearDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn - assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: icache SetValidEN + assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR