From 6188f10732b85f82ed21382d2d4e4c65e32b3cbd Mon Sep 17 00:00:00 2001 From: Thomas Fleming Date: Tue, 13 Apr 2021 13:39:22 -0400 Subject: [PATCH] Move InstrPageFault to fetch stage --- wally-pipelined/src/ebu/pagetablewalker.sv | 16 +++++++------ wally-pipelined/src/privileged/privileged.sv | 23 +++++++++++-------- .../src/wally/wallypipelinedhart.sv | 2 +- 3 files changed, 23 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/src/ebu/pagetablewalker.sv b/wally-pipelined/src/ebu/pagetablewalker.sv index 83c1de84..17014e5f 100644 --- a/wally-pipelined/src/ebu/pagetablewalker.sv +++ b/wally-pipelined/src/ebu/pagetablewalker.sv @@ -61,7 +61,7 @@ module pagetablewalker ( output logic MMUTranslationComplete, // Faults - output logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM + output logic InstrPageFaultF, LoadPageFaultM, StorePageFaultM ); // Internal signals @@ -154,7 +154,8 @@ module pagetablewalker ( // else if (~ValidPTE || (LeafPTE && BadMegapage)) // NextWalkerState = FAULT; // *** Leave megapage implementation for later - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; + // *** need to check if megapage valid/aligned + else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0; else NextWalkerState = FAULT; LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0; @@ -185,7 +186,7 @@ module pagetablewalker ( assign MMUTranslationComplete = '0; assign DTLBWriteM = '0; assign ITLBWriteF = '0; - assign InstrPageFaultM = '0; + assign InstrPageFaultF = '0; assign LoadPageFaultM = '0; assign StorePageFaultM = '0; @@ -208,7 +209,7 @@ module pagetablewalker ( FAULT: begin assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; assign MMUTranslationComplete = '1; - assign InstrPageFaultM = ~DTLBMissM; + assign InstrPageFaultF = ~DTLBMissM; assign LoadPageFaultM = DTLBMissM && ~MemStore; assign StorePageFaultM = DTLBMissM && MemStore; end @@ -243,13 +244,14 @@ module pagetablewalker ( IDLE: if (MMUTranslate) NextWalkerState = LEVEL2; else NextWalkerState = IDLE; LEVEL2: if (~MMUReady) NextWalkerState = LEVEL2; + else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1; else NextWalkerState = FAULT; LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1; // else if (~ValidPTE || (LeafPTE && BadMegapage)) // NextWalkerState = FAULT; // *** Leave megapage implementation for later - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; + else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0; else NextWalkerState = FAULT; LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0; @@ -285,7 +287,7 @@ module pagetablewalker ( assign MMUTranslationComplete = '0; assign DTLBWriteM = '0; assign ITLBWriteF = '0; - assign InstrPageFaultM = '0; + assign InstrPageFaultF = '0; assign LoadPageFaultM = '0; assign StorePageFaultM = '0; @@ -312,7 +314,7 @@ module pagetablewalker ( FAULT: begin assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; assign MMUTranslationComplete = '1; - assign InstrPageFaultM = ~DTLBMissM; + assign InstrPageFaultF = ~DTLBMissM; assign LoadPageFaultM = DTLBMissM && ~MemStore; assign StorePageFaultM = DTLBMissM && MemStore; end diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 4d772dc2..d0cf2ea1 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -40,7 +40,7 @@ module privileged ( input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongM, input logic [3:0] InstrClassM, input logic PrivilegedM, - input logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM, + input logic InstrPageFaultF, LoadPageFaultM, StorePageFaultM, input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD, input logic LoadMisalignedFaultM, LoadAccessFaultM, input logic StoreMisalignedFaultM, StoreAccessFaultM, @@ -62,8 +62,9 @@ module privileged ( logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; logic IllegalCSRAccessM; - logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; - logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; + logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; + logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM; + logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; logic IllegalInstrFaultM; logic BreakpointFaultM, EcallFaultM; @@ -129,13 +130,15 @@ module privileged ( // assign StorePageFaultM = 0; // pipeline fault signals - flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD); - flopenrc #(2) faultregE(clk, reset, FlushE, ~StallE, - {IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD - {IllegalIEUInstrFaultE, InstrAccessFaultE}); - flopenrc #(2) faultregM(clk, reset, FlushM, ~StallM, - {IllegalIEUInstrFaultE, InstrAccessFaultE}, - {IllegalIEUInstrFaultM, InstrAccessFaultM}); + flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, + {InstrPageFaultF, InstrAccessFaultF}, + {InstrPageFaultD, InstrAccessFaultD}); + flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE, + {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE}); + flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE}, + {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM}); trap trap(.*); diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 9b2bfe6a..1dba0b63 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -76,7 +76,7 @@ module wallypipelinedhart ( logic InstrMisalignedFaultM; logic DataMisalignedM; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; - logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM; + logic InstrPageFaultF, LoadPageFaultM, StorePageFaultM; logic LoadMisalignedFaultM, LoadAccessFaultM; logic StoreMisalignedFaultM, StoreAccessFaultM; logic [`XLEN-1:0] InstrMisalignedAdrM;