From 61027f650c47d613176944da584b753e769c4a8f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 1 Jul 2021 17:37:53 -0500 Subject: [PATCH] OMG. It's working! --- wally-pipelined/regression/wave.do | 103 ++++++++--------- wally-pipelined/src/cache/ICacheCntrl.sv | 124 +++++++++++---------- wally-pipelined/src/lsu/lsuArb.sv | 39 +++++-- wally-pipelined/src/mmu/pagetablewalker.sv | 17 +-- 4 files changed, 141 insertions(+), 142 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index f6bf34cc..213b5cee 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -299,6 +299,8 @@ add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/paget add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/pagetablewalker/HPTWStall add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWRead add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/EndWalk add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/MMUReadPTE add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/PRegEn add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/CurrentPTE @@ -318,17 +320,17 @@ add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/h add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/EndWalk add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr -add wave -noupdate -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState -add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW -add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate -add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead -add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr -add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE -add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady -add wave -noupdate -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU +add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState +add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/arbiter/SelPTW +add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/pagetablewalker/MMUStall +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady +add wave -noupdate -expand -group {LSU ARB} -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU add wave -noupdate /testbench/dut/hart/lsu/DataStall add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW -add wave -noupdate /testbench/dut/uncore/genblk2/plic/ExtIntM add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HSELUART @@ -351,8 +353,8 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb -add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate /testbench/dut/hart/pagetablewalker/StartWalk add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation @@ -364,20 +366,9 @@ add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/Virtua add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/TLBWrite add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/WriteLines -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/SATP_REGW -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/STATUS_MXR -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/STATUS_SUM -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/PrivilegeModeW -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/TLBAccessType -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/VirtualAddress -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/PageTypeWriteVal -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/TLBFlush TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 8} {3766 ns} 0} {{Cursor 3} {3377 ns} 0} {{Cursor 4} {3215 ns} 0} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {3377 ns} 0} {{Cursor 4} {3215 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 189 configure wave -justifyvalue left @@ -392,4 +383,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {3163 ns} {3403 ns} +WaveRestoreZoom {4209 ns} {4657 ns} diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index bc5c30b3..ea52130c 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -25,48 +25,50 @@ `include "wally-config.vh" -module ICacheCntrl #(parameter BLOCKLEN = 256) ( - // Inputs from pipeline - input logic clk, reset, - input logic StallF, StallD, - input logic FlushD, +module ICacheCntrl #(parameter BLOCKLEN = 256) + ( + // Inputs from pipeline + input logic clk, reset, + input logic StallF, StallD, + input logic FlushD, - // Input the address to read - // The upper bits of the physical pc - input logic [`PA_BITS-1:0] PCNextF, - input logic [`PA_BITS-1:0] PCPF, - // Signals to/from cache memory - // The read coming out of it - input logic [31:0] ICacheMemReadData, - input logic ICacheMemReadValid, - // The address at which we want to search the cache memory - output logic [`PA_BITS-1:0] PCTagF, - output logic [`PA_BITS-1:0] PCNextIndexF, - output logic ICacheReadEn, - // Load data into the cache - output logic ICacheMemWriteEnable, - output logic [BLOCKLEN-1:0] ICacheMemWriteData, + // Input the address to read + // The upper bits of the physical pc + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, + // Signals to/from cache memory + // The read coming out of it + input logic [31:0] ICacheMemReadData, + input logic ICacheMemReadValid, + // The address at which we want to search the cache memory + output logic [`PA_BITS-1:0] PCTagF, + output logic [`PA_BITS-1:0] PCNextIndexF, + output logic ICacheReadEn, + // Load data into the cache + output logic ICacheMemWriteEnable, + output logic [BLOCKLEN-1:0] ICacheMemWriteData, - // Outputs to rest of ifu - // High if the instruction in the fetch stage is compressed - output logic CompressedF, - // The instruction that was requested - // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros - output logic [31:0] FinalInstrRawF, + // Outputs to rest of ifu + // High if the instruction in the fetch stage is compressed + output logic CompressedF, + // The instruction that was requested + // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros + output logic [31:0] FinalInstrRawF, - // Outputs to pipeline control stuff - output logic ICacheStallF, EndFetchState, - input logic ITLBMissF, - input logic ITLBWriteF, + // Outputs to pipeline control stuff + output logic ICacheStallF, EndFetchState, + input logic ITLBMissF, + input logic ITLBWriteF, + input logic WalkerInstrPageFaultF, - // Signals to/from ahblite interface - // A read containing the requested data - input logic [`XLEN-1:0] InstrInF, - input logic InstrAckF, - // The read we request from main memory - output logic [`PA_BITS-1:0] InstrPAdrF, - output logic InstrReadF -); + // Signals to/from ahblite interface + // A read containing the requested data + input logic [`XLEN-1:0] InstrInF, + input logic InstrAckF, + // The read we request from main memory + output logic [`PA_BITS-1:0] InstrPAdrF, + output logic InstrReadF + ); // FSM states localparam STATE_READY = 0; @@ -125,39 +127,39 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( localparam WORDSPERLINE = BLOCKLEN/`XLEN; localparam LOGWPL = $clog2(WORDSPERLINE); - localparam integer PA_WIDTH = `PA_BITS - 2; + localparam integer PA_WIDTH = `PA_BITS - 2; - logic [4:0] CurrState, NextState; - logic hit, spill; - logic SavePC; - logic [1:0] PCMux; - logic CntReset; - logic PreCntEn, CntEn; - logic spillSave; - logic UnalignedSelect; - logic FetchCountFlag; + logic [4:0] CurrState, NextState; + logic hit, spill; + logic SavePC; + logic [1:0] PCMux; + logic CntReset; + logic PreCntEn, CntEn; + logic spillSave; + logic UnalignedSelect; + logic FetchCountFlag; localparam FetchCountThreshold = WORDSPERLINE - 1; - logic [LOGWPL:0] FetchCount, NextFetchCount; + logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF; + logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF; logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; - logic [15:0] SpillDataBlock0; + logic [15:0] SpillDataBlock0; localparam [31:0] NOP = 32'h13; - logic reset_q; - logic [1:0] PCMux_q; + logic reset_q; + logic [1:0] PCMux_q; - // Misaligned signals - //logic [`XLEN:0] MisalignedInstrRawF; - //logic MisalignedStall; - // Cache fault signals - //logic FaultStall; + // Misaligned signals + //logic [`XLEN:0] MisalignedInstrRawF; + //logic MisalignedStall; + // Cache fault signals + //logic FaultStall; // on spill we want to get the first 2 bytes of the next cache block. // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can @@ -181,7 +183,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // truncate the offset from PCPF for memory address generation assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; - // Detect if the instruction is compressed + // Detect if the instruction is compressed assign CompressedF = FinalInstrRawF[1:0] != 2'b11; @@ -372,7 +374,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( NextState = STATE_READY; end STATE_TLB_MISS: begin - if (ITLBWriteF) begin + if (ITLBWriteF | WalkerInstrPageFaultF) begin NextState = STATE_TLB_MISS_DONE; end else begin NextState = STATE_TLB_MISS; @@ -425,7 +427,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // store read data from memory interface before writing into SRAM. - genvar i; + genvar i; generate for (i = 0; i < WORDSPERLINE; i++) begin flopenr #(`XLEN) flop(.clk(clk), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index bf925704..76d89798 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -101,23 +101,38 @@ module lsuArb always_comb begin case(CurrState) StateReady: -/* -----\/----- EXCLUDED -----\/----- - if (HPTWTranslate & DataStall) NextState = StatePTWPending; - else - -----/\----- EXCLUDED -----/\----- */ - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - StatePTWPending: - if (HPTWTranslate & ~DataStall) NextState = StatePTWActive; - else if (HPTWTranslate & DataStall) NextState = StatePTWPending; - else NextState = StateReady; + if (HPTWTranslate) NextState = StatePTWActive; + else NextState = StateReady; StatePTWActive: - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; + if (HPTWTranslate) NextState = StatePTWActive; + else NextState = StateReady; + default: NextState = StateReady; + endcase + end + +/* -----\/----- EXCLUDED -----\/----- + + always_comb begin + case(CurrState) + StateReady: + /-* -----\/----- EXCLUDED -----\/----- + if (HPTWTranslate & DataStall) NextState = StatePTWPending; + else + -----/\----- EXCLUDED -----/\----- *-/ + if (HPTWTranslate) NextState = StatePTWActive; + else NextState = StateReady; + StatePTWPending: + if (HPTWTranslate & ~DataStall) NextState = StatePTWActive; + else if (HPTWTranslate & DataStall) NextState = StatePTWPending; + else NextState = StateReady; + StatePTWActive: + if (HPTWTranslate) NextState = StatePTWActive; + else NextState = StateReady; default: NextState = StateReady; endcase end + -----/\----- EXCLUDED -----/\----- */ // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index e425b367..3670069b 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -369,9 +369,6 @@ module pagetablewalker HPTWRead = 1'b1; end else begin NextWalkerState = FAULT; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; end end @@ -409,9 +406,6 @@ module pagetablewalker HPTWRead = 1'b1; end else begin NextWalkerState = FAULT; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; end end @@ -450,9 +444,6 @@ module pagetablewalker HPTWRead = 1'b1; end else begin NextWalkerState = FAULT; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; end end @@ -479,9 +470,6 @@ module pagetablewalker TranslationPAdr = TranslationVAdrQ; end else begin NextWalkerState = FAULT; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; end end @@ -492,7 +480,10 @@ module pagetablewalker FAULT: begin NextWalkerState = IDLE; - MMUStall = 1'b0; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + MMUStall = 1'b0; end // Default case should never happen