From 60573b92b257666afb2ae33d2dd6b3c6df112352 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Nov 2021 08:48:46 -0700 Subject: [PATCH] Adding custom Wally test infrastructure --- .../{wally-I.py => wally-I-PIPELINE.py} | 2 +- .../rv32i_m/I/src/WALLY-PIPELINE.S | 82 +++++++++++++++++++ .../riscv-test-suite/rv64i_m/D/Makefile | 3 + .../riscv-test-suite/rv64i_m/D/Makefrag | 35 ++++++++ .../rv64i_m/I/src/WALLY-PIPELINE.S | 82 +++++++++++++++++++ .../regression/regression-wally.py | 2 +- wally-pipelined/testbench/testbench.sv | 51 ++---------- wally-pipelined/testbench/tests.vh | 30 ++++++- 8 files changed, 242 insertions(+), 45 deletions(-) rename tests/testgen/{wally-I.py => wally-I-PIPELINE.py} (99%) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S diff --git a/tests/testgen/wally-I.py b/tests/testgen/wally-I-PIPELINE.py similarity index 99% rename from tests/testgen/wally-I.py rename to tests/testgen/wally-I-PIPELINE.py index b186e21c..80ac853b 100755 --- a/tests/testgen/wally-I.py +++ b/tests/testgen/wally-I-PIPELINE.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 ################################## -# wally-I.py +# wally-I-PIPELINE.py # # David_Harris@hmc.edu 27 October 2021 # diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S new file mode 100644 index 00000000..28d36e3e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S @@ -0,0 +1,82 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 08:46:04.665699// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + +RVTEST_SIGBASE( x8,signature_x8_1) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile new file mode 100644 index 00000000..a474441d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile @@ -0,0 +1,3 @@ +include ../../Makefile.include + +$(eval $(call compile_template,-march=rv64id -mabi=lp64 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag new file mode 100644 index 00000000..261a9a85 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag @@ -0,0 +1,35 @@ +# RISC-V Architecture Test RV64IM Makefrag +# +# Copyright (c) 2018, Imperas Software Ltd. +# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV64IM architectural tests + +rv64im_sc_tests = \ + +rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests)) + +target_tests += $(rv64im_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S new file mode 100644 index 00000000..e7d29cc8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S @@ -0,0 +1,82 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu +// Created 2021-11-01 08:46:04.668632// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + +RVTEST_SIGBASE( x8,signature_x8_1) +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x8_0: + .fill 0*(XLEN/32),4,0xdeadbeef + + +signature_x8_1: + .fill 19*(XLEN/32),4,0xdeadbeef + + +signature_x1_0: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_1: + .fill 256*(XLEN/32),4,0xdeadbeef + + +signature_x1_2: + .fill 148*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S +// David_Harris@hmc.edu diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 79532c5c..49ca8712 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -41,7 +41,7 @@ def getBuildrootTC(short): BRgrepstr=str(MAX_EXPECTED)+" instructions" return TestCase(name="buildroot",cmd=BRcmd,grepstr=BRgrepstr) -tests64 = ["arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"] +tests64 = ["wally64i", "arch64i", "arch64priv", "arch64c", "arch64m", "imperas64i", "imperas64p", "imperas64mmu", "imperas64f", "imperas64d", "imperas64m", "imperas64a", "imperas64c"] #, "testsBP64"] for test in tests64: tc = TestCase( name=test, diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index 8c25f154..13ba7e16 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -94,7 +94,9 @@ logic [3:0] dummy; "imperas64c": if (`C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "testsBP64": tests = testsBP64; - // *** add arch f and d tests, peripheral tests + "wally64i": tests = wally64i; + "wally64priv": tests = wally64priv; + "wally64periph": tests = wally64periph; endcase end else begin // RV32 case (TEST) @@ -111,51 +113,15 @@ logic [3:0] dummy; "imperas32a": if (`A_SUPPORTED) tests = imperas32a; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; - // ***add arch f and d tests + "wally32i": tests = wally32i; + "wally32priv": tests = wally32priv; + "wally32periph": tests = wally32periph; endcase end if (tests.size() == 1) begin $display("TEST %s not supported in this configuration", TEST); $stop; end - //if (TEST == "arch-64m") //tests = {archtests64m}; - /* if (`XLEN == 64) begin // RV64 - if (`TESTSBP) begin - tests = testsBP64; - // testsbp should not run the other tests. It starts at address 0 rather than - // 0x8000_0000, the next if must remain an else if. - end else if (TESTSPERIPH) - tests = imperastests64periph; - else if (TESTSPRIV) - tests = imperastests64p; - else begin - tests = {imperastests64p,imperastests64i, imperastests64periph}; - if (`C_SUPPORTED) tests = {tests, imperastests64ic}; - else tests = {tests, imperastests64iNOc}; - if (`F_SUPPORTED) tests = {imperastests64f, tests}; - if (`D_SUPPORTED) tests = {imperastests64d, tests}; - if (`MEM_VIRTMEM) tests = {imperastests64mmu, tests}; - if (`A_SUPPORTED) tests = {imperastests64a, tests}; - if (`M_SUPPORTED) tests = {imperastests64m, tests}; - end - //tests = {imperastests64a, tests}; - end else begin // RV32 - // *** add the 32 bit bp tests - if (TESTSPERIPH) - tests = imperastests32periph; - else if (TESTSPRIV) - tests = imperastests32p; - else begin - tests = {archtests32i, imperastests32i, imperastests32p};//,imperastests32periph}; *** broken at the moment - if (`C_SUPPORTED) tests = {tests, imperastests32ic}; - else tests = {tests, imperastests32iNOc}; - if (`F_SUPPORTED) tests = {imperastests32f, tests}; - if (`MEM_VIRTMEM) tests = {imperastests32mmu, tests}; - if (`A_SUPPORTED) tests = {imperastests32a, tests}; - if (`M_SUPPORTED) tests = {imperastests32m, tests}; - tests = {archtests32i}; - end - end */ end string signame, memfilename, pathname; @@ -203,9 +169,10 @@ logic [3:0] dummy; end end // read test vectors into memory - if (tests[0] == `IMPERASTEST) + pathname = tvpaths[tests[0].atoi()]; +/* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; - else pathname = tvpaths[1]; + else pathname = tvpaths[1]; */ memfilename = {pathname, tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.uncore.dtim.RAM); ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index 42b1fc0b..b10be876 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -25,10 +25,12 @@ `define IMPERASTEST "0" `define RISCVARCHTEST "1" +`define WALLYTEST "2" string tvpaths[] = '{ "../../tests/imperas-riscv-tests/work/", - "../../addins/riscv-arch-test/work/" + "../../addins/riscv-arch-test/work/", + "../../tests/wally-riscv-arch-test/work/" }; string imperas32mmu[] = '{ @@ -1067,4 +1069,30 @@ string imperas32f[] = '{ "rv32i_m/I/xori-01", "4010" }; + string wally64i[] = '{ + `WALLYTEST, + "rv64i_m/I/add-01", "9010" +// "rv64i_m/I/pipeline-01", "9010" + }; + + string wally64priv[] = '{ + `WALLYTEST + }; + + string wally64periph[] = '{ + `WALLYTEST + }; + +string wally32i[] = '{ + `WALLYTEST, + "rv64i_m/I/pipeline-01", "9010" + }; + + string wally32priv[] = '{ + `WALLYTEST + }; + + string wally32periph[] = '{ + `WALLYTEST + };