From 600e7802dd14693dc49602ae10f511d1ff1cd9d0 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 4 Jul 2021 18:56:30 -0400
Subject: [PATCH] Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and
 simplified size muxing in lsuArb

---
 wally-pipelined/src/lsu/lsu.sv                  | 12 ++++++------
 wally-pipelined/src/lsu/lsuArb.sv               | 10 +++-------
 wally-pipelined/src/wally/wallypipelinedhart.sv |  8 ++++----
 3 files changed, 13 insertions(+), 17 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 8d4df6ec..a2bcf52b 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -64,7 +64,7 @@ module lsu (
   output logic [1:0] 	      AtomicMaskedM,
   input logic 		      MemAckW, // from ahb
   input logic [`XLEN-1:0]     HRDATAW, // from ahb
-  output logic [2:0] 	      Funct3MfromLSU,
+  output logic [2:0] 	      SizeFromLSU,
   output logic 		      StallWfromLSU,
 
 
@@ -132,7 +132,7 @@ module lsu (
   logic 	    MMUTranslate;
   logic 	    HPTWRead;
   logic [1:0] 	    MemRWMtoLSU;
-  logic [2:0] 	    Funct3MtoLSU;
+  logic [2:0] 	    SizeToLSU;
   logic [1:0] 	    AtomicMtoLSU;
   logic [`XLEN-1:0] MemAdrMtoLSU;
   logic [`XLEN-1:0] WriteDataMtoLSU;
@@ -204,7 +204,7 @@ module lsu (
 		 // LSU
 		 .DisableTranslation(DisableTranslation),
 		 .MemRWMtoLSU(MemRWMtoLSU),
-		 .Funct3MtoLSU(Funct3MtoLSU),
+		 .SizeToLSU(SizeToLSU),
 		 .AtomicMtoLSU(AtomicMtoLSU),
 		 .MemAdrMtoLSU(MemAdrMtoLSU),          
 		 .WriteDataMtoLSU(WriteDataMtoLSU),   // *** ??????????????
@@ -220,7 +220,7 @@ module lsu (
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
   dmmu(.TLBAccessType(MemRWMtoLSU),
        .VirtualAddress(MemAdrMtoLSU),
-       .Size(Funct3MtoLSU[1:0]),
+       .Size(SizeToLSU[1:0]),
        .PTEWriteVal(PageTableEntryM),
        .PageTypeWriteVal(PageTypeM),
        .TLBWrite(DTLBWriteM),
@@ -244,7 +244,7 @@ module lsu (
 
   // Determine if an Unaligned access is taking place
   always_comb
-    case(Funct3MtoLSU[1:0]) 
+    case(SizeToLSU[1:0]) 
       2'b00:  DataMisalignedMfromLSU = 0;                       // lb, sb, lbu
       2'b01:  DataMisalignedMfromLSU = MemAdrMtoLSU[0];              // lh, sh, lhu
       2'b10:  DataMisalignedMfromLSU = MemAdrMtoLSU[1] | MemAdrMtoLSU[0]; // lw, sw, flw, fsw, lwu
@@ -400,7 +400,7 @@ module lsu (
   end // always_comb
 
   // *** for now just pass through size
-  assign Funct3MfromLSU = Funct3MtoLSU;
+  assign SizeFromLSU = SizeToLSU;
   assign StallWfromLSU = StallWtoLSU;
   
 
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index dc77ec9d..23e88970 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -54,7 +54,7 @@ module lsuArb
    // to LSU   
    output logic 	    DisableTranslation, 
    output logic [1:0] 	    MemRWMtoLSU,
-   output logic [2:0] 	    Funct3MtoLSU,
+   output logic [2:0] 	    SizeToLSU,
    output logic [1:0] 	    AtomicMtoLSU,
    output logic [`XLEN-1:0] MemAdrMtoLSU,
    output logic [`XLEN-1:0] WriteDataMtoLSU,
@@ -87,6 +87,7 @@ module lsuArb
   statetype CurrState, NextState;
   logic 		    SelPTW;
   logic 		    HPTWStallD;
+  logic [2:0] PTWSize;
   
 
   flopenl #(.TYPE(statetype)) StateReg(.clk(clk),
@@ -139,13 +140,8 @@ module lsuArb
   
   generate
     assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
-  /*  if (`XLEN == 32) begin
-      assign Funct3MtoLSU = SelPTW ? 3'b010 : Funct3M;
-    end else begin
-      assign Funct3MtoLSU = SelPTW ? 3'b011 : Funct3M;
-    end*/
   endgenerate
-  mux2 sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoLSU);
+  mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, SizeToLSU);
 
   assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM;
   assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM;
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 1c44565f..f18d5af4 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -159,7 +159,7 @@ module wallypipelinedhart
 
   // IEU vs HPTW arbitration signals to send to LSU
   logic [1:0] 		    MemRWMtoLSU;
-  logic [2:0] 		    Funct3MtoLSU;
+  logic [2:0] 		    SizeToLSU;
   logic [1:0] 		    AtomicMtoLSU;
   logic [`XLEN-1:0] 	    MemAdrMtoLSU;
   logic [`XLEN-1:0] 	    WriteDataMtoLSU;
@@ -169,7 +169,7 @@ module wallypipelinedhart
   logic 		    DataMisalignedMfromLSU;
   logic 		    StallWtoLSU;
   logic 		    StallWfromLSU;  
-  logic [2:0] 		    Funct3MfromLSU;
+  logic [2:0] 		    SizeFromLSU;
 
   
   ifu ifu(.InstrInF(InstrRData),
@@ -207,7 +207,7 @@ module wallypipelinedhart
 	  .AtomicMaskedM(AtomicMaskedM),
 	  .MemAckW(MemAckW),
 	  .HRDATAW(HRDATAW),
-	  .Funct3MfromLSU(Funct3MfromLSU),           // stays the same
+	  .SizeFromLSU(SizeFromLSU),           // stays the same
 	  .StallWfromLSU(StallWfromLSU),             // stays the same
 	  .DSquashBusAccessM(DSquashBusAccessM),     // probalby removed after dcache implemenation?
 	  // currently not connected (but will need to be used for lsu talking to ahb.
@@ -261,7 +261,7 @@ module wallypipelinedhart
 	       //.InstrRData(InstrF), // hook up InstrF later
 	       .ISquashBusAccessF(1'b0), // *** temporary hack to disable PMP instruction fetch checking
 	       .WriteDataM(WriteDataM),
-	       .MemSizeM(Funct3MfromLSU[1:0]), .UnsignedLoadM(Funct3MfromLSU[2]),
+	       .MemSizeM(SizeFromLSU[1:0]), .UnsignedLoadM(SizeFromLSU[2]),
 	       .Funct7M(InstrM[31:25]),
 	       .HRDATAW(HRDATAW),
 	       .StallW(StallWfromLSU),