From 5f7b0b8a9b293e5455f22e2ead6fd13b7b269034 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 16 Nov 2022 12:36:58 -0600 Subject: [PATCH] Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr. --- pipelined/src/cache/cache.sv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 6fe11f35..46cdcd6a 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -117,13 +117,15 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// // Choose read address (RAdr). Normally use NextAdr, but use PAdr during stalls - // and FlushAdr when handling D$ flushes + // and FlushAdr when handling D$ flushes + // The icache must update to the newest PCNextF on flush as it is probably a trap. Trap + // sets PCNextF to XTVEC and the icache must start reading the instruction. mux3 #(SETLEN) AdrSelMux( .d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr), - .s({SelFlush, (SelAdr | SelHPTW)}), .y(RAdr)); + .s({SelFlush, ((SelAdr | SelHPTW) & ~((DCACHE == 0) & FlushStage))}), .y(RAdr)); // Array of cache ways, along with victim, hit, dirty, and read merging logic - cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) + cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE) CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .FlushStage,