From 0b4186f1e87f6677f1f0087363f26f7abab1842e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 12:05:49 -0600 Subject: [PATCH 1/2] Vectored interrupts now require 64 byte alignment. Eliminates adder. --- pipelined/src/privileged/csr.sv | 3 ++- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 22 ++++++++--------- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 24 +++++++++---------- 3 files changed, 25 insertions(+), 24 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index f68c9d88..5fe94770 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -143,7 +143,8 @@ module csr #(parameter logic VectoredM; logic [`XLEN-1:0] TVecPlusCauseM; assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01); - assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; + //assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; + assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else assign TrapVectorM = TVecAlignedM; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index ac3d81c3..a6c1cedd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -299,23 +299,23 @@ end_trap_triggers: // -------------------------------------------------------------------------------------------- -.align 2 +.align 6 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. - j segfault_\MODE\() // 2: reserved - j m_soft_vector_\MODE\() // 3: breakpoint - j segfault_\MODE\() // 4: reserved - j s_time_vector_\MODE\() // 5: load access fault - j segfault_\MODE\() // 6: reserved - j m_time_vector_\MODE\() // 7: store access fault - j segfault_\MODE\() // 8: reserved - j s_ext_vector_\MODE\() // 9: ecall from S-mode - j segfault_\MODE\() // 10: reserved - j m_ext_vector_\MODE\() // 11: ecall from M-mode + j segfault_\MODE\() + j m_soft_vector_\MODE\() + j segfault_\MODE\() + j s_time_vector_\MODE\() + j segfault_\MODE\() + j m_time_vector_\MODE\() + j segfault_\MODE\() + j s_ext_vector_\MODE\() + j segfault_\MODE\() + j m_ext_vector_\MODE\() // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index a0691f2b..e75c339e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -293,23 +293,23 @@ end_trap_triggers: // // -------------------------------------------------------------------------------------------- -.align 3 +.align 6 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way - j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. - j segfault_\MODE\() // 2: reserved - j m_soft_vector_\MODE\() // 3: breakpoint - j segfault_\MODE\() // 4: reserved - j s_time_vector_\MODE\() // 5: load access fault - j segfault_\MODE\() // 6: reserved - j m_time_vector_\MODE\() // 7: store access fault - j segfault_\MODE\() // 8: reserved - j s_ext_vector_\MODE\() // 9: ecall from S-mode - j segfault_\MODE\() // 10: reserved - j m_ext_vector_\MODE\() // 11: ecall from M-mode + j s_soft_vector_\MODE\() + j segfault_\MODE\() + j m_soft_vector_\MODE\() + j segfault_\MODE\() + j s_time_vector_\MODE\() + j segfault_\MODE\() + j m_time_vector_\MODE\() + j segfault_\MODE\() + j s_ext_vector_\MODE\() + j segfault_\MODE\() + j m_ext_vector_\MODE\() // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): From c3b43b2fac67079c5a57ed8c18db4d30a2d1e089 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 13:16:09 -0600 Subject: [PATCH 2/2] Waiting on fix for wally64periph uart test. would like to remove vectored interrupt adder. --- pipelined/src/privileged/csr.sv | 6 ++++-- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 3 ++- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 3 ++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 5fe94770..1b2ed42e 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -143,8 +143,10 @@ module csr #(parameter logic VectoredM; logic [`XLEN-1:0] TVecPlusCauseM; assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01); - //assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; - assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; + // *** Would like you use concat version, but breaks uart test wally64priv when + // mtvec is aligned to 64 bytes. + assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; + //assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else assign TrapVectorM = TVecAlignedM; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index a6c1cedd..82279e92 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -299,7 +299,8 @@ end_trap_triggers: // -------------------------------------------------------------------------------------------- -.align 6 +//.align 6 +.align 2 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index e75c339e..bd43eb11 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -293,7 +293,8 @@ end_trap_triggers: // // -------------------------------------------------------------------------------------------- -.align 6 +//.align 6 +.align 3 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented