diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index f68c9d88..1b2ed42e 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -143,7 +143,10 @@ module csr #(parameter
     logic VectoredM;
     logic [`XLEN-1:0] TVecPlusCauseM;
     assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01);
+	// *** Would like you use concat version, but breaks uart test wally64priv when
+	// mtvec is aligned to 64 bytes.
     assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00};
+	//assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00};
     mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
   end else 
     assign TrapVectorM = TVecAlignedM;
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index ac3d81c3..82279e92 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -299,6 +299,7 @@ end_trap_triggers:
     // --------------------------------------------------------------------------------------------
 
 
+//.align 6
 .align 2
 trap_handler_\MODE\():
     j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
@@ -306,16 +307,16 @@ trap_handler_\MODE\():
     // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
     // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
     j s_soft_vector_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
-    j segfault_\MODE\()            // 2: reserved
-    j m_soft_vector_\MODE\()    // 3: breakpoint
-    j segfault_\MODE\()            // 4: reserved
-    j s_time_vector_\MODE\()    // 5: load access fault
-    j segfault_\MODE\()            // 6: reserved
-    j m_time_vector_\MODE\()    // 7: store access fault
-    j segfault_\MODE\()            // 8: reserved
-    j s_ext_vector_\MODE\()     // 9: ecall from S-mode
-    j segfault_\MODE\()            // 10: reserved
-    j m_ext_vector_\MODE\()     // 11: ecall from M-mode
+    j segfault_\MODE\()
+    j m_soft_vector_\MODE\()
+    j segfault_\MODE\()     
+    j s_time_vector_\MODE\()
+    j segfault_\MODE\()     
+    j m_time_vector_\MODE\()
+    j segfault_\MODE\()     
+    j s_ext_vector_\MODE\() 
+    j segfault_\MODE\()     
+    j m_ext_vector_\MODE\() 
     // 12 through >=16 are reserved or designated for platform use
 
 trap_unvectored_\MODE\():
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index a0691f2b..bd43eb11 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -293,23 +293,24 @@ end_trap_triggers:
     //     
     // --------------------------------------------------------------------------------------------
 
+//.align 6
 .align 3
 trap_handler_\MODE\():
     j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
     // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
     // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
     // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
-    j s_soft_vector_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
-    j segfault_\MODE\()            // 2: reserved
-    j m_soft_vector_\MODE\()    // 3: breakpoint
-    j segfault_\MODE\()            // 4: reserved
-    j s_time_vector_\MODE\()    // 5: load access fault
-    j segfault_\MODE\()            // 6: reserved
-    j m_time_vector_\MODE\()    // 7: store access fault
-    j segfault_\MODE\()            // 8: reserved
-    j s_ext_vector_\MODE\()     // 9: ecall from S-mode
-    j segfault_\MODE\()            // 10: reserved
-    j m_ext_vector_\MODE\()     // 11: ecall from M-mode
+    j s_soft_vector_\MODE\()
+    j segfault_\MODE\()     
+    j m_soft_vector_\MODE\()
+    j segfault_\MODE\()     
+    j s_time_vector_\MODE\()
+    j segfault_\MODE\()     
+    j m_time_vector_\MODE\()
+    j segfault_\MODE\()     
+    j s_ext_vector_\MODE\() 
+    j segfault_\MODE\()     
+    j m_ext_vector_\MODE\() 
     // 12 through >=16 are reserved or designated for platform use
 
 trap_unvectored_\MODE\():