From 5eb1fff27d9944eb626789e84510458a590101ea Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 29 Aug 2022 17:11:27 -0500
Subject: [PATCH] Have a rough working multi manager!

---
 pipelined/src/lsu/lsu.sv                  | 5 ++++-
 pipelined/src/wally/wallypipelinedcore.sv | 4 +++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 9a089def..58013f9d 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -83,6 +83,7 @@ module lsu (
    (* mark_debug = "true" *)   output logic [2:0] LSUHSIZE, 
    (* mark_debug = "true" *)   output logic [2:0] LSUHBURST,
    (* mark_debug = "true" *)   output logic [1:0] LSUHTRANS,
+   (* mark_debug = "true" *)   output logic [`XLEN/8-1:0] LSUHWSTRB,
    (* mark_debug = "true" *)   output logic LSUTransComplete,
             // page table walker
    input logic [`XLEN-1:0]  SATP_REGW, // from csr
@@ -277,7 +278,9 @@ module lsu (
       assign LSUHSIZE = LSUFunct3M;
  
       flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM));
-      assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
+
+      flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
+      flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB);
 
 /* -----\/----- EXCLUDED -----\/-----
       busfsm #(LOGBWPL) busfsm(
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index a3481430..4d6ec36d 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -147,6 +147,7 @@ module wallypipelinedcore (
   logic             LSUBusWrite;
   logic             LSUBusAck, LSUBusInit;
   logic [`XLEN-1:0]         LSUHWDATA;
+  logic [`XLEN/8-1:0]       LSUHWSTRB;
   logic                     LSUHWRITE;
   logic                     LSUHREADY;
   
@@ -264,7 +265,7 @@ module wallypipelinedcore (
   .ReadDataW, .FlushDCacheM,
   // connected to ahb (all stay the same)
   .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
-  .HRDATA, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete,
+  .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete,
           .LSUHWRITE, .LSUHREADY,
 
     // connect to csr or privilege and stay the same.
@@ -333,6 +334,7 @@ module wallypipelinedcore (
      // Signals from Data Cache
      .LSUHADDR,
      .LSUHWDATA,
+     .LSUHWSTRB,
      .LSUHSIZE,
      .LSUHBURST,
      .LSUHTRANS,