From 5dc4fb757af778abd918f02da633d0ce7aa3964c Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 10:20:02 -0700 Subject: [PATCH] Continued busdp/ebu simplification --- pipelined/src/ebu/ahblite.sv | 41 ++++++++----------- pipelined/src/ifu/ifu.sv | 14 +++---- pipelined/src/ifu/irom.sv | 48 +++++++++++++++++++++++ pipelined/src/lsu/lsu.sv | 12 +++--- pipelined/src/wally/wallypipelinedcore.sv | 28 ++++++------- 5 files changed, 90 insertions(+), 53 deletions(-) create mode 100644 pipelined/src/ifu/irom.sv diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 6c3d0c33..8d2a58f1 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -41,29 +41,27 @@ module ahblite ( input logic UnsignedLoadM, input logic [1:0] AtomicMaskedM, // Signals from Instruction Cache - input logic [`PA_BITS-1:0] IFUBusAdr, + input logic [`PA_BITS-1:0] IFUHADDR, + input logic [2:0] IFUHBURST, + input logic [1:0] IFUHTRANS, input logic IFUBusRead, - output logic [`XLEN-1:0] IFUBusHRDATA, - output logic IFUBusAck, - output logic IFUBusInit, - input logic [2:0] IFUBurstType, - input logic [1:0] IFUTransType, input logic IFUTransComplete, + output logic IFUBusInit, + output logic IFUBusAck, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUHADDR, - input logic LSUBusRead, - input logic LSUBusWrite, - input logic [`XLEN-1:0] LSUBusHWDATA, - output logic [`XLEN-1:0] LSUHRDATA, + input logic [`XLEN-1:0] LSUHWDATA, input logic [2:0] LSUHSIZE, input logic [2:0] LSUHBURST, input logic [1:0] LSUHTRANS, + input logic LSUBusRead, + input logic LSUBusWrite, input logic LSUTransComplete, - output logic LSUBusAck, output logic LSUBusInit, + output logic LSUBusAck, + // AHB-Lite external signals - (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic HREADY, HRESP, (* mark_debug = "true" *) output logic HCLK, HRESETn, (* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address @@ -86,8 +84,7 @@ module ahblite ( logic LSUGrant; logic [31:0] AccessAddress; - logic [2:0] ISize; - + assign HCLK = clk; assign HRESETn = ~reset; @@ -133,11 +130,10 @@ module ahblite ( // bus outputs assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); - assign AccessAddress = (LSUGrant) ? LSUHADDR[31:0] : IFUBusAdr[31:0]; + assign AccessAddress = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0]; assign HADDR = AccessAddress; - assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign HSIZE = (LSUGrant) ? {1'b0, LSUHSIZE[1:0]} : ISize; - assign HBURST = (LSUGrant) ? LSUHBURST : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. + assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits + assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. 000: Single (SINGLE) @@ -153,23 +149,20 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = (LSUGrant) ? LSUHTRANS : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); // Byte mask for HWSTRB swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB)); // delay write data by one cycle for - flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); flop #(1) writereg(HCLK, HWRITE, HWRITED); - // Route signals to Instruction and Data Caches - // *** assumes AHBW = XLEN - assign IFUBusHRDATA = HRDATA; - assign LSUHRDATA = HRDATA; + // Send control back to IFU and LSU assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE)); assign IFUBusAck = HREADY & (BusState == INSTRREAD); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 1f3bda8c..1c21bbbf 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -36,14 +36,14 @@ module ifu ( input logic StallF, StallD, StallE, StallM, input logic FlushF, FlushD, FlushE, FlushM, // Bus interface -(* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, +(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) input logic IFUBusAck, (* mark_debug = "true" *) input logic IFUBusInit, -(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, +(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, -(* mark_debug = "true" *) output logic [2:0] IFUBurstType, -(* mark_debug = "true" *) output logic [1:0] IFUTransType, +(* mark_debug = "true" *) output logic [2:0] IFUHBURST, +(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, (* mark_debug = "true" *) output logic IFUTransComplete, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute @@ -203,9 +203,9 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) busdp(.clk, .reset, - .HRDATA(IFUBusHRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), - .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUBurstType), .HTRANS(IFUTransType), .BusTransComplete(IFUTransComplete), - .LSUFunct3M(3'b010), .HADDR(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), + .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), + .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete), + .LSUFunct3M(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr), .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv new file mode 100644 index 00000000..fccc916d --- /dev/null +++ b/pipelined/src/ifu/irom.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// irom.sv +// +// Written: Ross Thompson ross1728@gmail.com January 30, 2022 +// Modified: +// +// Purpose: simple instruction ROM +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module irom( + input logic clk, reset, + input logic [1:0] LSURWM, + input logic [`XLEN-1:0] IEUAdrE, + input logic TrapM, + output logic [`LLEN-1:0] ReadDataWordM +); + + +// localparam ADDR_WDITH = $clog2(`IROM_RAM_RANGE/8); // *** replace with tihs when defined + localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size + localparam OFFSET = $clog2(`LLEN/8); + + brom1p1rw #(`LLEN/8, 8, ADDR_WDITH) + rom(.clk, .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM)); +endmodule + diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 514b165e..06dac355 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -70,8 +70,8 @@ module lsu ( (* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) input logic LSUBusAck, (* mark_debug = "true" *) input logic LSUBusInit, - (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUHRDATA, - (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, + (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, + (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUHSIZE, (* mark_debug = "true" *) output logic [2:0] LSUHBURST, (* mark_debug = "true" *) output logic [1:0] LSUHTRANS, @@ -224,7 +224,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) busdp( .clk, .reset, - .HRDATA(LSUHRDATA), .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), + .HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), @@ -234,8 +234,8 @@ module lsu ( mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DLSUBusBuffer[`XLEN-1:0]}), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), - .s(SelUncachedAdr), .y(LSUBusHWDATA)); + mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), + .s(SelUncachedAdr), .y(LSUHWDATA)); if(`DCACHE) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( @@ -254,7 +254,7 @@ module lsu ( assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; end end else begin: nobus // block: bus - assign {LSUBusHWDATA, SelUncachedAdr} = '0; + assign {LSUHWDATA, SelUncachedAdr} = '0; assign ReadDataWordMuxM = LittleEndianReadDataWordM; end diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 5fc8904f..4b2f4d11 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -136,12 +136,11 @@ module wallypipelinedcore ( logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] IFUBusAdr; - logic [`XLEN-1:0] IFUBusHRDATA; + logic [`PA_BITS-1:0] IFUHADDR; logic IFUBusRead; logic IFUBusAck, IFUBusInit; - logic [2:0] IFUBurstType; - logic [1:0] IFUTransType; + logic [2:0] IFUHBURST; + logic [1:0] IFUHTRANS; logic IFUTransComplete; // AHB LSU interface @@ -149,8 +148,7 @@ module wallypipelinedcore ( logic LSUBusRead; logic LSUBusWrite; logic LSUBusAck, LSUBusInit; - logic [`XLEN-1:0] LSUHRDATA; - logic [`XLEN-1:0] LSUBusHWDATA; + logic [`XLEN-1:0] LSUHWDATA; logic BPPredWrongE; logic BPPredDirWrongM; @@ -178,8 +176,8 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .FlushF, .FlushD, .FlushE, .FlushM, // Fetch - .IFUBusHRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUTransComplete, + .HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR, + .IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete, .ICacheAccess, .ICacheMiss, // Execute @@ -264,7 +262,7 @@ module wallypipelinedcore ( .ReadDataW, .FlushDCacheM, // connected to ahb (all stay the same) .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, - .LSUHRDATA, .LSUBusHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, + .HRDATA, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -296,16 +294,14 @@ module wallypipelinedcore ( ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), - .IFUBusAdr, .IFUBusRead, - .IFUBusHRDATA, - .IFUBurstType, - .IFUTransType, + .IFUHADDR, .IFUBusRead, + .IFUHBURST, + .IFUHTRANS, .IFUTransComplete, .IFUBusAck, .IFUBusInit, // Signals from Data Cache - .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, - .LSUHRDATA, + .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, @@ -313,7 +309,7 @@ module wallypipelinedcore ( .LSUBusAck, .LSUBusInit, - .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, + .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED);