From 5d9dab61495b1b8e32573a733a7d41d0143f5998 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 1 Aug 2022 20:48:45 -0500 Subject: [PATCH] pulled swbbytemask out of subword write. --- pipelined/src/ebu/ahblite.sv | 4 +--- pipelined/src/lsu/lsu.sv | 12 +++++++++--- pipelined/src/lsu/subwordwrite.sv | 10 +--------- pipelined/src/wally/wallypipelinedcore.sv | 3 --- 4 files changed, 11 insertions(+), 18 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index a502bf9f..4203f0f5 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -49,7 +49,6 @@ module ahblite ( input logic [2:0] IFUBurstType, input logic [1:0] IFUTransType, input logic IFUTransComplete, - input logic [(`XLEN-1)/8:0] ByteMaskM, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUBusAdr, @@ -157,8 +156,7 @@ module ahblite ( assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); - //assign HWSTRB = ByteMaskM; - // Byte mask for HWSTRB + // Byte mask for HWSTRB swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB)); // delay write data by one cycle for diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e6f63264..540ff6b8 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -77,8 +77,6 @@ module lsu ( (* mark_debug = "true" *) output logic [2:0] LSUBurstType, (* mark_debug = "true" *) output logic [1:0] LSUTransType, (* mark_debug = "true" *) output logic LSUTransComplete, - output logic [(`XLEN-1)/8:0] ByteMaskM, - // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -116,6 +114,7 @@ module lsu ( logic [`XLEN-1:0] LSUWriteDataM; logic [`XLEN-1:0] WriteDataM; logic [`LLEN-1:0] ReadDataM; + logic [(`XLEN-1)/8:0] ByteMaskM; // *** TO DO: Burst mode @@ -277,7 +276,14 @@ module lsu ( subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), - .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM); + .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM); + + // Compute byte masks + //swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM[2:0]), .ByteMask(ByteMaskM)); + swbytemaskword #(`XLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(ByteMaskM)); + // *** fix me. + //swbytemaskword #(.WORDLEN(`XLEN)) + //swbytemaskword (.Size(LSUFunct3M[2:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM)); ///////////////////////////////////////////////////////////////////////////////////////////// // MW Pipeline Register diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index b9306236..d42033ef 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -34,16 +34,8 @@ module subwordwrite ( input logic [2:0] LSUPAdrM, input logic [2:0] LSUFunct3M, input logic [`XLEN-1:0] AMOWriteDataM, - output logic [`XLEN-1:0] LittleEndianWriteDataM, - output logic [`XLEN/8-1:0] ByteMaskM -); + output logic [`XLEN-1:0] LittleEndianWriteDataM); - // Compute byte masks - //swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM)); - // *** fix me. - swbytemaskword #(.WORDLEN(`XLEN)) - swbytemaskword (.Size(LSUFunct3M[2:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM)); - // Replicate data for subword writes if (`XLEN == 64) begin:sww always_comb diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 372f4aba..200789c4 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -116,7 +116,6 @@ module wallypipelinedcore ( logic [1:0] PageType; logic sfencevmaM, wfiM, IntPendingM; logic SelHPTW; - logic [`XLEN/8-1:0] ByteMaskM; // PMA checker signals @@ -266,7 +265,6 @@ module wallypipelinedcore ( // connected to ahb (all stay the same) .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, - .ByteMaskM, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -313,7 +311,6 @@ module wallypipelinedcore ( .LSUTransComplete, .LSUBusAck, .LSUBusInit, - .ByteMaskM, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,