diff --git a/pipelined/src/ebu/abhinterface.sv b/pipelined/src/ebu/abhinterface.sv
index d2973533..c0b360ee 100644
--- a/pipelined/src/ebu/abhinterface.sv
+++ b/pipelined/src/ebu/abhinterface.sv
@@ -53,11 +53,11 @@ module ahbinterface #(parameter WRITEABLE = 0)
   input logic                CPUBusy,
   output logic               BusStall,
   output logic               BusCommitted,
-  output logic [`XLEN-1:0]   ReadDataWordM);
+  output logic [`XLEN-1:0]   ReadDataWord);
   
   logic                       CaptureEn;
 
-  flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM));
+  flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWord));
 
   if(WRITEABLE) begin
     // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN    
diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv
index ba802227..52990e16 100644
--- a/pipelined/src/ebu/buscachefsm.sv
+++ b/pipelined/src/ebu/buscachefsm.sv
@@ -124,6 +124,7 @@ module buscachefsm #(parameter integer   WordCountThreshold,
   assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT;
 
   assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) |
+					//(BusCurrState == STATE_CAPTURE & ~RW[0]) |  // replace the next line with this.  Fails uart test but i think it's a test problem not a hardware problem.
 					(BusCurrState == STATE_CAPTURE) | 
                     (BusCurrState == STATE_CACHE_FETCH) |
                     (BusCurrState == STATE_CACHE_EVICT);
diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv
index e5cc9891..788ff3ba 100644
--- a/pipelined/src/ebu/busfsm.sv
+++ b/pipelined/src/ebu/busfsm.sv
@@ -71,7 +71,8 @@ module busfsm
   end
 
   assign BusStall = (BusCurrState == STATE_READY & |RW) |
-					(BusCurrState == STATE_CAPTURE);
+//					(BusCurrState == STATE_CAPTURE & ~RW[0]); // possible optimization here.  fails uart test, but i'm not sure the failure is valid.
+					(BusCurrState == STATE_CAPTURE); 
   
   assign BusCommitted = BusCurrState != STATE_READY;
 
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 6f2948ec..4f451708 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -252,7 +252,7 @@ module ifu (
       ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), 
         .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
         .HWSTRB(), .RW, .ByteMask(), .WriteData('0),
-        .CPUBusy, .BusStall, .BusCommitted(), .ReadDataWordM(AllInstrRawF[31:0]));
+        .CPUBusy, .BusStall, .BusCommitted(), .ReadDataWord(AllInstrRawF[31:0]));
 
       assign IFUHBURST = 3'b0;
       assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 7f1f491a..f8ecc233 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -294,7 +294,7 @@ module lsu (
       ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), 
         .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
         .HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
-        .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM);
+        .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWord(ReadDataWordM));
           
       assign ReadDataWordMuxM = LittleEndianReadDataWordM;  // from byte swapping
       assign LSUHBURST = 3'b0;