From 5b1f9797f52a3616db9348560bc310ad95a629d5 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Mon, 19 Jul 2021 07:59:27 -0500
Subject: [PATCH] update part I on sbtm change

---
 wally-pipelined/src/fpu/divconv.sv                 | 4 ++--
 wally-pipelined/src/fpu/{sbtm.sv => sbtm_div.sv}   | 2 +-
 wally-pipelined/src/fpu/{sbtm2.sv => sbtm_sqrt.sv} | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)
 rename wally-pipelined/src/fpu/{sbtm.sv => sbtm_div.sv} (92%)
 rename wally-pipelined/src/fpu/{sbtm2.sv => sbtm_sqrt.sv} (92%)

diff --git a/wally-pipelined/src/fpu/divconv.sv b/wally-pipelined/src/fpu/divconv.sv
index 8a853300..7cfde7ad 100755
--- a/wally-pipelined/src/fpu/divconv.sv
+++ b/wally-pipelined/src/fpu/divconv.sv
@@ -45,8 +45,8 @@ module divconv (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_o
    assign n2 = op_type ? d2 : {n,11'h0};
    
    // IA div/sqrt
-   sbtm ia1 (d[52:41], ia_div);
-   sbtm2 ia2 (d2[63:52], ia_sqrt);
+   sbtm_div ia1 (d[52:41], ia_div);
+   sbtm_sqrt ia2 (d2[63:52], ia_sqrt);
    assign ia_out = op_type ? {ia_sqrt, {53{1'b0}}} : {ia_div, {53{1'b0}}};
    
    // Choose IA or iteration
diff --git a/wally-pipelined/src/fpu/sbtm.sv b/wally-pipelined/src/fpu/sbtm_div.sv
similarity index 92%
rename from wally-pipelined/src/fpu/sbtm.sv
rename to wally-pipelined/src/fpu/sbtm_div.sv
index 5c12f7b2..ceda26a5 100644
--- a/wally-pipelined/src/fpu/sbtm.sv
+++ b/wally-pipelined/src/fpu/sbtm_div.sv
@@ -1,4 +1,4 @@
-module sbtm (input logic [11:0] a, output logic [10:0] ia_out);
+module sbtm_div (input logic [11:0] a, output logic [10:0] ia_out);
 
    // bit partitions
    logic [3:0] x0;
diff --git a/wally-pipelined/src/fpu/sbtm2.sv b/wally-pipelined/src/fpu/sbtm_sqrt.sv
similarity index 92%
rename from wally-pipelined/src/fpu/sbtm2.sv
rename to wally-pipelined/src/fpu/sbtm_sqrt.sv
index 8b66f199..9f1ca5e2 100644
--- a/wally-pipelined/src/fpu/sbtm2.sv
+++ b/wally-pipelined/src/fpu/sbtm_sqrt.sv
@@ -1,4 +1,4 @@
-module sbtm2 (input logic [11:0] a, output logic [10:0] y);
+module sbtm_sqrt (input logic [11:0] a, output logic [10:0] y);
 
    // bit partitions
    logic [4:0] x0;