diff --git a/fpga/constraints/constraints-artyA7.xdc b/fpga/constraints/constraints-artyA7.xdc index 866d78c9..464af749 100644 --- a/fpga/constraints/constraints-artyA7.xdc +++ b/fpga/constraints/constraints-artyA7.xdc @@ -1,7 +1,9 @@ # The main clocks are all autogenerated by the Xilinx IP -# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus. -# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. -# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. +# mmcm_clkout1 is the 22Mhz clock from the DDR3 IP used to drive wally and the AHB Bus. +# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4. +# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP. + +# clock comes from pin E3 and is 100Mhz create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] @@ -41,7 +43,7 @@ set_property PACKAGE_PIN D0 [get_ports UARTSout] set_max_delay -from [get_ports UARTSin] 10.000 set_max_delay -to [get_ports UARTSout] 10.000 set_property IOSTANDARD LVCMOS33 [get_ports UARTSin] -set_property IOSTANDARD LVCMOS3 [get_ports UARTSout] +set_property IOSTANDARD LVCMOS33 [get_ports UARTSout] set_property DRIVE 6 [get_ports UARTSout] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin] diff --git a/fpga/generator/xlnx_ddr3-artya7-mig.prj b/fpga/generator/xlnx_ddr3-artya7-mig.prj new file mode 100644 index 00000000..b7536491 --- /dev/null +++ b/fpga/generator/xlnx_ddr3-artya7-mig.prj @@ -0,0 +1,162 @@ + + + + + + + + mig_7series_0 + + 1 + + 1 + + OFF + + 1024 + + ON + + Enabled + + xc7a100t-csg324/-1 + + 4.2 + + Single-Ended + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a100ti-csg324 + + + + DDR3_SDRAM/Components/MT41J128M16XX-125 + 3000 + 1.8V + 4:1 + 102.564 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 14 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + ROUND_ROBIN + 28 + 64 + 4 + 0 + + + + + diff --git a/fpga/generator/xlnx_ddr3-artya7.tcl b/fpga/generator/xlnx_ddr3-artya7.tcl new file mode 100644 index 00000000..25d0af0d --- /dev/null +++ b/fpga/generator/xlnx_ddr3-artya7.tcl @@ -0,0 +1,30 @@ +set partNumber xc7a100tcsg324-1 +set boardName arty-a7 + +set ipName xlnx_ddr3 + +create_project $ipName . -force -part $partNumber +#set_property board_part $boardName [current_project] + +# really just these two lines which change +create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName + +# to recreate one of these. +# 1. use the gui to generate a mig. +# 2. Find the xci file in project_1/project_1.srcs/sources_1/ip/mig_7series_0/ +# 3. Run vivado in tcl mode and use command list_property [get_ips $ipName] +# to find all parameters for this ip. +# 4. Then reconstruct the list with the needed parameters. +# turns out the ddr3 mig cannot be built this way like the ddr 4 mig?!?!? +# instead we need to read the project file, but we have to copy it to the corret location first +cp $WALLY/fpga/generator/xlnx_ddr3-artya7-mig.prj IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/ + +# unlike the vertex ultra scale and ultra scale + fpga's the atrix 7 mig we only get ui clock. + +set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-artya7-mig.prj}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1