From 1591a40f6870d104bfb2705058d164d3fa4cad80 Mon Sep 17 00:00:00 2001 From: bbracker Date: Tue, 26 Oct 2021 12:43:42 -0700 Subject: [PATCH 1/2] bugfix argument passing to GDB script; remove outdated GDB script --- .../testvector-generation/checkpoint.gdb | 64 ------------------- .../testvector-generation/genCheckpoint.gdb | 6 +- .../testvector-generation/genCheckpoint.sh | 4 +- 3 files changed, 5 insertions(+), 69 deletions(-) delete mode 100644 wally-pipelined/linux-testgen/testvector-generation/checkpoint.gdb diff --git a/wally-pipelined/linux-testgen/testvector-generation/checkpoint.gdb b/wally-pipelined/linux-testgen/testvector-generation/checkpoint.gdb deleted file mode 100644 index 1d79bc8a..00000000 --- a/wally-pipelined/linux-testgen/testvector-generation/checkpoint.gdb +++ /dev/null @@ -1,64 +0,0 @@ -define genCheckpoint - # GDB config - set pagination off - set logging overwrite on - set logging redirect on - set confirm off - - # QEMU must also use TCP port 1240 - target extended-remote :1240 - - # QEMU Config - maintenance packet Qqemu.PhyMemMode:1 - - # Symbol file - file ../buildroot-image-output/vmlinux - - # Argument Parsing - set $tcpPort=$arg0 - set $instrCount=$arg1 - set $statePath=$arg2 - set $ramPath=$arg3 - set $checkPC=$arg4 - set $checkPCoccurences=$arg5 - eval "set $statePath = \"%s/stateGDB.txt\"", $statePath - eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath - - - # Step over reset vector into actual code - stepi 100 - # Set breakpoint for where to stop - b do_idle - # Proceed to checkpoint - printf "GDB proceeding to checkpoint at %d instrs\n", $instrCount - #stepi $instrCount-1000 - b *$checkPC - ignore 2 $checkPCoccurences - c - - printf "Reached checkpoint at %d instrs\n", $instrCount - - # Log all registers to a file - printf "GDB storing state to %s\n", $statePath - eval "set logging file %s", $statePath - set logging on - info all-registers - set logging off - - # Log main memory to a file - printf "GDB storing RAM to %s\n", $ramPath - eval "set logging file %s", $ramPath - set logging on - x/134217728xb 0x80000000 - set logging off - - # Continue to checkpoint; stop on the 3rd time - # Should reach login prompt by then - printf "GDB continuing execution to login prompt\n" - ignore 1 2 - c - - printf "GDB reached login prompt!\n" - kill - q -end diff --git a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.gdb b/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.gdb index 65ce1559..92630698 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.gdb +++ b/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.gdb @@ -1,4 +1,4 @@ -define genCheckpoint +define genCheckpoint # GDB config set pagination off set logging overwrite on @@ -8,7 +8,7 @@ define genCheckpoint # Argument Parsing set $tcpPort=$arg0 set $instrCount=$arg1 - set $statePath=$arg1 + set $statePath=$arg2 set $ramPath=$arg2 set $checkPC=$arg3 set $checkPCoccurences=$arg4 @@ -31,7 +31,7 @@ define genCheckpoint # Proceed to checkpoint printf "GDB proceeding to checkpoint at %d instrs\n", $instrCount #stepi $instrCount-1000 - b *$checkPC + eval "b *0x%s",$checkPC ignore 2 $checkPCoccurences c diff --git a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh b/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh index 249094ea..f3542034 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh +++ b/wally-pipelined/linux-testgen/testvector-generation/genCheckpoint.sh @@ -3,7 +3,7 @@ source genSettings.sh tcpPort=1236 -instrs=50000000 +instrs=10000000 checkOutDir="$outDir/checkpoint$instrs" checkIntermedDir="$checkOutDir/intermediate-outputs" @@ -28,7 +28,7 @@ then -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on,rr=replay,rrfile="$intermedDir/$recordFile" \ -gdb tcp::$tcpPort -S) \ - & riscv64-unknown-elf-gdb -quiet -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" 0x$pc $occurences" + & riscv64-unknown-elf-gdb -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" \"$pc\" $occurences" # Post-Process GDB outputs ./parseState.py "$checkOutDir" ./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt" From c4170ece27f0bdfe184badc91e733ff20d8a256b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 27 Oct 2021 09:57:11 -0500 Subject: [PATCH 2/2] Replaced async reset flip flops with sync reset flip flops in cache and bpread. --- wally-pipelined/src/cache/cachereplacementpolicy.sv | 2 +- wally-pipelined/src/cache/cacheway.sv | 6 +++--- wally-pipelined/src/cache/dcachefsm.sv | 2 +- wally-pipelined/src/cache/icachefsm.sv | 2 +- wally-pipelined/src/ifu/RAsPredictor.sv | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv index d2739a7c..e02c3675 100644 --- a/wally-pipelined/src/cache/cachereplacementpolicy.sv +++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv @@ -49,7 +49,7 @@ module cachereplacementpolicy logic LRUWriteEnD; /* verilator lint_off BLKLOOPINIT */ - always_ff @(posedge clk, posedge reset) begin + always_ff @(posedge clk) begin if (reset) begin RAdrD <= '0; MemPAdrMD <= '0; diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv index bb760bba..6f9c0855 100644 --- a/wally-pipelined/src/cache/cacheway.sv +++ b/wally-pipelined/src/cache/cacheway.sv @@ -111,7 +111,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay; - always_ff @(posedge clk, posedge reset) begin + always_ff @(posedge clk) begin if (reset) ValidBits <= {NUMLINES{1'b0}}; else if (InvalidateAll) @@ -134,14 +134,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, generate if(DIRTY_BITS) begin - always_ff @(posedge clk, posedge reset) begin + always_ff @(posedge clk) begin if (reset) DirtyBits <= {NUMLINES{1'b0}}; else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1; else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0; end - always_ff @(posedge clk, posedge reset) begin + always_ff @(posedge clk) begin SetDirtyD <= SetDirty; ClearDirtyD <= ClearDirty; end diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 4fba55bd..59f90462 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -144,7 +144,7 @@ module dcachefsm assign CntEn = PreCntEn & AHBAck; - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv index 82590747..2461e0dd 100644 --- a/wally-pipelined/src/cache/icachefsm.sv +++ b/wally-pipelined/src/cache/icachefsm.sv @@ -116,7 +116,7 @@ module icachefsm logic PreCntEn; // the FSM is always runing, do not stall. - always_ff @(posedge clk, posedge reset) + always_ff @(posedge clk) if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; diff --git a/wally-pipelined/src/ifu/RAsPredictor.sv b/wally-pipelined/src/ifu/RAsPredictor.sv index bde30be5..44929e3c 100644 --- a/wally-pipelined/src/ifu/RAsPredictor.sv +++ b/wally-pipelined/src/ifu/RAsPredictor.sv @@ -62,7 +62,7 @@ module RASPredictor .q(PtrQ)); // RAS must be reset. - always_ff @ (posedge clk, posedge reset) begin + always_ff @ (posedge clk) begin if(reset) begin for(index=0; index