From 1fe06bc670517438bdc4b46f6ff5112cf389387e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 7 Jul 2021 17:52:16 -0500 Subject: [PATCH 001/112] Partial implementation of the data cache. Missing the fsm. --- wally-pipelined/src/cache/DCacheMem.sv | 107 ++++++++++++ wally-pipelined/src/cache/ICacheMem.sv | 4 +- wally-pipelined/src/cache/dcache.sv | 221 +++++++++++++++++++++++++ wally-pipelined/src/lsu/dcache.sv | 184 -------------------- 4 files changed, 330 insertions(+), 186 deletions(-) create mode 100644 wally-pipelined/src/cache/DCacheMem.sv create mode 100644 wally-pipelined/src/cache/dcache.sv delete mode 100644 wally-pipelined/src/lsu/dcache.sv diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv new file mode 100644 index 00000000..b82858db --- /dev/null +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -0,0 +1,107 @@ +/////////////////////////////////////////// +// DCacheMem (Memory for the Data Cache) +// +// Written: ross1728@gmail.com July 07, 2021 +// Implements the data, tag, valid, dirty, and replacement bits. +// +// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26) + (input logic clk, + input logic reset, + + input logic [$clog2(NUMLINES)-1:0] Adr, + input logic [$clog2(NUMLINES)-1:0] WAdr, // write address for valid and dirty only + input logic WriteEnable, + input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, + input logic [BLOCKLEN-1:0] WriteData, + input logic [TAGLEN-1:0] WriteTag, + input logic SetValid, + input logic ClearValid, + input logic SetDirty, + input logic ClearDirty, + + output logic [BLOCKLEN-1:0] ReadData, + output logic [TAGLEN-1:0] ReadTag, + output logic Valid, + output logic Dirty + ); + + genvar words; + + generate + for(words = 0; words < BLOCKLEN/`XLEN; words++) begin + sram1rw #(.DEPTH(`XLEN), + .WIDTH(NUMLINES)) + CacheDataMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadData[(words+1)*`XLEN-1:words*`XLEN]), + .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), + .WriteEnable(WriteEnable & WriteWordEnable[words])); + end + endgenerate + + sram1rw #(.DEPTH(TAGLEN), + .WIDTH(NUMLINES)) + CacheTagMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadTag), + .WriteData(WriteTag), + .WriteEnable(WriteEnable)); + + + sram1rw #(.DEPTH(BLOCKLEN), + .WIDTH(NUMLINES)) + CacheDataMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadData), + .WriteData(WriteData), + .WriteEnable(WriteEnable)); + + sram1rw #(.DEPTH(TAGLEN), + .WIDTH(NUMLINES)) + CacheTagMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadTag), + .WriteData(WriteTag), + .WriteEnable(WriteEnable)); + + always_ff @(posedge clk, posedge reset) begin + if (reset) + ValidBits <= {NUMLINES{1'b0}}; + else if (SetValid & WriteEnable) ValidBits[WAdr] <= 1'b1; + else if (ClearValid & WriteEnable) ValidBits[WAdr] <= 1'b0; + Valid <= ValidBits[Adr]; + end + + always_ff @(posedge clk, posedge reset) begin + if (reset) + DirtyBits <= {NUMLINES{1'b0}}; + else if (SetDirty & WriteEnable) DirtyBits[WAdr] <= 1'b1; + else if (ClearDirty & WriteEnable) DirtyBits[WAdr] <= 1'b0; + Dirty <= DirtyBits[Adr]; + end + + +endmodule; // DCacheMemWay + + diff --git a/wally-pipelined/src/cache/ICacheMem.sv b/wally-pipelined/src/cache/ICacheMem.sv index 9a5fdbe2..ce3507ba 100644 --- a/wally-pipelined/src/cache/ICacheMem.sv +++ b/wally-pipelined/src/cache/ICacheMem.sv @@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) // If flush is high, invalidate the entire cache input logic flush, - input logic [`PA_BITS-1:0] PCTagF, // physical address - input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address + input logic [`PA_BITS-1:0] PCTagF, // physical address + input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address input logic WriteEnable, input logic [BLOCKLEN-1:0] WriteLine, output logic [BLOCKLEN-1:0] ReadLineF, diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv new file mode 100644 index 00000000..54b5276d --- /dev/null +++ b/wally-pipelined/src/cache/dcache.sv @@ -0,0 +1,221 @@ +/////////////////////////////////////////// +// dcache (data cache) +// +// Written: ross1728@gmail.com July 07, 2021 +// Implements the L1 data cache +// +// Purpose: Storage for data and meta data. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module dcache + (input logic clk, + input logic reset, + input logic StallM, + input logic StallW, + input logic FlushM, + input logic FlushW, + + // cpu side + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [1:0] AtomicM, + input logic [`PA_BITS-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [`PA_BITS-1:0] MemPAdrM, // physical address + + input logic [`XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] ReadDataW, + output logic DCacheStall, + + // inputs from TLB and PMA/P + input logic FaultM, + input logic DTLBMissM, + // ahb side + output logic [`PA_BITS-1:0] AHBPAdr, // to ahb + output logic AHBRead, + output logic AHBWrite, + input logic AHBAck, // from ahb + input logic [`XLEN-1:0] HRDATA, // from ahb + output logic [`XLEN-1:0] HWDATA, // to ahb + output logic [2:0] AHBSize + ); + + localparam integer BLOCKLEN = 256; + localparam integer NUMLINES = 512; + localparam integer NUMWAYS = 4; + localparam integer NUMREPL_BITS = 3; + + localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer INDEXLEN = $clog2(NUMLINES); + localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; + localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + + + logic [1:0] AdrSel; + logic [`PA_BITS-1:0] MemPAdrW; + logic [INDEXLEN-1:0] SRAMAdr; + logic [NUMWAYS-1:0] WriteEnable; + logic [NUMWAYS-1:0] WriteWordEnable; + logic [BLOCKLEN-1:0] SRAMWriteData; + logic [TAGLEN-1:0] WriteTag; + logic SetValid, ClearValid; + logic SetDirty, ClearDirty; + logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; + logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; + logic [NUMWAYS-1:0] Valid, Dirty, WayHit; + logic Hit; + logic [NUMREPL_BITS-1:0] ReplacementBits, NewReplacement; + logic [BLOCKLEN-1:0] ReadDataSelectWayM; + logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; + logic [`XLEN-1:0] WriteDataW, FinalWriteDataW; + logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + + + typedef enum {STATE_READY, + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_WRITE_BACK, + STATE_MISS_READ_SRAM, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_WRITE_BACK, + STATE_AMO_MISS_READ_SRAM, + STATE_AMO_MISS_UPDATE, + STATE_AMO_MISS_WRITE, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_SRAM_BUSY, + STATE_PTW_READY, + STATE_PTW_FETCH, + STATE_UNCACHED} statetype; + + statetype CurrState, NextState; + + + flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), + .en(~StallW), + .d(MemPAdrM), + .q(MemPAdrW)); + + mux3 #(INDEXLEN) + AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSET-1:OFFSET]), + .d1(MemPAdrM[INDEXLEN+OFFSET-1:OFFSET]), + .d2(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .s(AdrSel), + .y(SRAMAdr)); + + genvar way; + generate + for(way = 0; way < NUMWAYS; way = way + 1) begin + DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN)) + MemWay(.clk(clk), + .reset(reset), + .Adr(SRAMAdr), + .WAdr(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .WriteEnable(SRAMWriteEnable[way]), + .WriteWordEnable(SRAMWordEnable[way]), + .WriteData(SRAMWriteData), + .WriteTag(WriteTag), + .SetValid(SetValid), + .ClearValid(ClearValid), + .SetDirty(SetDirty), + .ClearDirty(ClearDirty), + .ReadData(ReadDataM[way]), + .ReadTag(ReadTag[way]), + .Valid(Valid[way]), + .Dirty(Dirty[way])); + assign WayHit = Valid & (ReadTag[way] == MemAdrM); + assign ReadDataMaskedM = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + end + endgenerate + + always_ff @(posedge clk, posedge reset) begin + if (reset) ReplacementBits <= '0; + else if (WriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; + end + + assign Hit = |WayHit; + assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. + + // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can + // easily build a variable input mux. + genvar index; + generate + for (index = 0; index < WORDSPERLINE; index++) begin + assign ReadDataSelectWayM[index] = ReadDataSelectM[((index+1)*`XLEN)-1: (index*`XLEN)]; + end + endgenerate + + // variable input mux + assign WordReadDataM = ReadDataSelectWayM[MemPAdrM[WORDSPERLINE+$clog2(`XLEN/8) : $clog2(`XLEN/8)]]; + // finally swr + subwordread subwordread(.HRDATA(WordReadDataM), + .HADDRD(MemPAdrM[`XLEN/8-1:0]), + .HSIZED(Funct3M), + .HRDATAMasked(FinalReadDataM)); + + flopen #(XLEN) ReadDataWReg(.clk(clk), + .en(~StallW), + .d(FinalReadDataM), + .q(ReadDataW)); + + // write path + flopen #(XLEN) WriteDataWReg(.clk(clk), + .en(~StallW), + .d(WriteDataM), + .q(WriteDataW)); + + subwordwrite subwordwrite(.HRDATA(ReadDataW), + .HADDRD(MemPAdrM[`XLEN/8-1:0]), + .HSIZED(Funct3W), + .HWDATAIN(WriteDataW), + .HWDATA(FinalWriteDataW)); + + // register the fetch data from the next level of memory. + generate + for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer + flopen #(`XLEN) fb(.clk(clk), + .en(AHBAck & (index == FetchCount)), + .d(HRDATA), + .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); + end + endgenerate + + // mux between the CPU's write and the cache fetch. + generate + for(index = 0; index < WORDSPERLINE; index++) begin + assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalWriteDataW; + end + endgenerate + + mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsW), + .d1(DCacheMemWriteData), + .s(SelMemWriteData), + .y(SRAMWriteData)); + + + + + +endmodule; // dcache + + diff --git a/wally-pipelined/src/lsu/dcache.sv b/wally-pipelined/src/lsu/dcache.sv deleted file mode 100644 index e8dfeb5c..00000000 --- a/wally-pipelined/src/lsu/dcache.sv +++ /dev/null @@ -1,184 +0,0 @@ -/////////////////////////////////////////// -// dcache.sv -// -// Written: jaallen@g.hmc.edu 2021-04-15 -// Modified: -// -// Purpose: Cache memory for the dmem so it can access memory less often, saving cycles -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -`include "wally-config.vh" - -module dcache( - // Basic pipeline stuff - input logic clk, reset, - input logic StallW, - input logic FlushW, - // Upper bits of physical address - input logic [`PA_BITS-1:12] UpperPAdrM, - // Lower 12 bits of virtual address, since it's faster this way - input logic [11:0] LowerVAdrM, - // Write to the dcache - input logic [`XLEN-1:0] DCacheWriteDataM, - input logic DCacheReadM, DCacheWriteM, - // Data read in from the ebu unit - input logic [`XLEN-1:0] ReadDataW, - input logic MemAckW, - // Access requested from the ebu unit - output logic [`PA_BITS-1:0] MemPAdrM, - output logic MemReadM, MemWriteM, - // High if the dcache is requesting a stall - output logic DCacheStallW, - // The data that was requested from the cache - output logic [`XLEN-1:0] DCacheReadW -); - - // Configuration parameters - // TODO Move these to a config file - localparam integer DCACHELINESIZE = 256; - localparam integer DCACHENUMLINES = 512; - - // Input signals to cache memory - logic FlushMem; - logic [`PA_BITS-1:12] DCacheMemUpperPAdr; - logic [11:0] DCacheMemLowerAdr; - logic DCacheMemWriteEnable; - logic [DCACHELINESIZE-1:0] DCacheMemWriteData; - logic [`XLEN-1:0] DCacheMemWritePAdr; - logic EndFetchState; - // Output signals from cache memory - logic [`XLEN-1:0] DCacheMemReadData; - logic DCacheMemReadValid; - - wtdirectmappedmem #(.LINESIZE(DCACHELINESIZE), .NUMLINES(DCACHENUMLINES), .WORDSIZE(`XLEN)) cachemem( - .*, - // Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall - .stall(StallW), - .flush(FlushMem), - .ReadUpperPAdr(DCacheMemUpperPAdr), - .ReadLowerAdr(DCacheMemLowerAdr), - .LoadEnable(DCacheMemWriteEnable), - .LoadLine(DCacheMemWriteData), - .LoadPAdr(DCacheMemWritePAdr), - .DataWord(DCacheMemReadData), - .DataValid(DCacheMemReadValid), - .WriteEnable(0), - .WriteWord(0), - .WritePAdr(0), - .WriteSize(2'b10) - ); - - dcachecontroller #(.LINESIZE(DCACHELINESIZE)) controller(.*); - - // For now, assume no writes to executable memory - assign FlushMem = 1'b0; -endmodule - -module dcachecontroller #(parameter LINESIZE = 256) ( - // Inputs from pipeline - input logic clk, reset, - input logic StallW, - input logic FlushW, - - // Input the address to read - // The upper bits of the physical pc - input logic [`PA_BITS-1:12] DCacheMemUpperPAdr, - // The lower bits of the virtual pc - input logic [11:0] DCacheMemLowerAdr, - - // Signals to/from cache memory - // The read coming out of it - input logic [`XLEN-1:0] DCacheMemReadData, - input logic DCacheMemReadValid, - // Load data into the cache - output logic DCacheMemWriteEnable, - output logic [LINESIZE-1:0] DCacheMemWriteData, - output logic [`XLEN-1:0] DCacheMemWritePAdr, - - // The read that was requested - output logic [31:0] DCacheReadW, - - // Outputs to pipeline control stuff - output logic DCacheStallW, EndFetchState, - - // Signals to/from ahblite interface - // A read containing the requested data - input logic [`XLEN-1:0] ReadDataW, - input logic MemAckW, - // The read we request from main memory - output logic [`PA_BITS-1:0] MemPAdrM, - output logic MemReadM, MemWriteM -); - - // Cache fault signals - logic FaultStall; - - // Handle happy path (data in cache) - - always_comb begin - DCacheReadW = DCacheMemReadData; - end - - - // Handle cache faults - - localparam integer WORDSPERLINE = LINESIZE/`XLEN; - localparam integer LOGWPL = $clog2(WORDSPERLINE); - localparam integer OFFSETWIDTH = $clog2(LINESIZE/8); - - logic FetchState, BeginFetchState; - logic [LOGWPL:0] FetchWordNum, NextFetchWordNum; - logic [`PA_BITS-1:0] LineAlignedPCPF; - - flopr #(1) FetchStateFlop(clk, reset, BeginFetchState | (FetchState & ~EndFetchState), FetchState); - flopr #(LOGWPL+1) FetchWordNumFlop(clk, reset, NextFetchWordNum, FetchWordNum); - - genvar i; - generate - for (i=0; i < WORDSPERLINE; i++) begin:sb - flopenr #(`XLEN) flop(clk, reset, FetchState & (i == FetchWordNum), ReadDataW, DCacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]); - end - endgenerate - - // Enter the fetch state when we hit a cache fault - always_comb begin - BeginFetchState = ~DCacheMemReadValid & ~FetchState & (FetchWordNum == 0); - end - // Exit the fetch state once the cache line has been loaded - flopr #(1) EndFetchStateFlop(clk, reset, DCacheMemWriteEnable, EndFetchState); - - // Machinery to request the correct addresses from main memory - always_comb begin - MemReadM = FetchState & ~EndFetchState & ~DCacheMemWriteEnable; - LineAlignedPCPF = {DCacheMemUpperPAdr, DCacheMemLowerAdr[11:OFFSETWIDTH], {OFFSETWIDTH{1'b0}}}; - MemPAdrM = LineAlignedPCPF + FetchWordNum*(`XLEN/8); - NextFetchWordNum = FetchState ? FetchWordNum+MemAckW : {LOGWPL+1{1'b0}}; - end - - // Write to cache memory when we have the line here - always_comb begin - DCacheMemWritePAdr = LineAlignedPCPF; - DCacheMemWriteEnable = FetchWordNum == {1'b1, {LOGWPL{1'b0}}} & FetchState & ~EndFetchState; - end - - // Stall the pipeline while loading a new line from memory - always_comb begin - DCacheStallW = FetchState | ~DCacheMemReadValid; - end -endmodule From 910ddb83ae078923bfa36a2a54d6b9b76cffdb0a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 8 Jul 2021 15:26:16 -0500 Subject: [PATCH 002/112] This d cache fsm is getting complex. --- wally-pipelined/src/cache/ICacheCntrl.sv | 1 + wally-pipelined/src/cache/dcache.sv | 387 +++++++++++++++++------ 2 files changed, 298 insertions(+), 90 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index e7098d75..2b5ce55d 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -413,6 +413,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) assign NextFetchCount = FetchCount + 1'b1; // This part is confusing. + // *** Ross Thompson reduce the complexity. This is just dumb. // we need to remove the offset bits (PCPTrunkF). Because the AHB interface is XLEN wide // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 54b5276d..2988c6a4 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -5,125 +5,130 @@ // Implements the L1 data cache // // Purpose: Storage for data and meta data. -// +// // A component of the Wally configurable RISC-V project. -// +// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software // is furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// `include "wally-config.vh" module dcache - (input logic clk, - input logic reset, - input logic StallM, - input logic StallW, - input logic FlushM, - input logic FlushW, + (input logic clk, + input logic reset, + input logic StallM, + input logic StallW, + input logic FlushM, + input logic FlushW, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [1:0] AtomicM, + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [1:0] AtomicM, input logic [`PA_BITS-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address - - input logic [`XLEN-1:0] WriteDataM, + + input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, - output logic DCacheStall, + output logic DCacheStall, // inputs from TLB and PMA/P - input logic FaultM, - input logic DTLBMissM, + input logic FaultM, + input logic DTLBMissM, + input logic UncachedM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb - output logic AHBRead, - output logic AHBWrite, - input logic AHBAck, // from ahb + output logic AHBRead, + output logic AHBWrite, + input logic AHBAck, // from ahb input logic [`XLEN-1:0] HRDATA, // from ahb - output logic [`XLEN-1:0] HWDATA, // to ahb - output logic [2:0] AHBSize + output logic [`XLEN-1:0] HWDATA, // to ahb + output logic [2:0] AHBSize ); - localparam integer BLOCKLEN = 256; - localparam integer NUMLINES = 512; - localparam integer NUMWAYS = 4; - localparam integer NUMREPL_BITS = 3; + localparam integer BLOCKLEN = 256; + localparam integer NUMLINES = 512; + localparam integer NUMWAYS = 4; + localparam integer NUMREPL_BITS = 3; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); - localparam integer INDEXLEN = $clog2(NUMLINES); - localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; - localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer INDEXLEN = $clog2(NUMLINES); + localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; + localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + localparam integer LOGWPL = $clog2(WORDSPERLINE); + - logic [1:0] AdrSel; - logic [`PA_BITS-1:0] MemPAdrW; - logic [INDEXLEN-1:0] SRAMAdr; - logic [NUMWAYS-1:0] WriteEnable; - logic [NUMWAYS-1:0] WriteWordEnable; - logic [BLOCKLEN-1:0] SRAMWriteData; - logic [TAGLEN-1:0] WriteTag; - logic SetValid, ClearValid; - logic SetDirty, ClearDirty; - logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; - logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] Valid, Dirty, WayHit; - logic Hit; + logic SelAdrM; + logic [`PA_BITS-1:0] MemPAdrW; + logic [INDEXLEN-1:0] SRAMAdr; + logic [NUMWAYS-1:0] WriteEnable; + logic [NUMWAYS-1:0] WriteWordEnable; + logic [BLOCKLEN-1:0] SRAMWriteData; + logic SetValidM, ClearValidM, SetValidW, ClearValidW; + logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; + logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; + logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; + logic [NUMWAYS-1:0] Valid, Dirty, WayHit; + logic CacheHit; logic [NUMREPL_BITS-1:0] ReplacementBits, NewReplacement; - logic [BLOCKLEN-1:0] ReadDataSelectWayM; - logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; - logic [`XLEN-1:0] WriteDataW, FinalWriteDataW; - logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + logic [BLOCKLEN-1:0] ReadDataSelectWayM; + logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; + logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; + logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + logic [LOGWPL:0] FetchCount, NextFetchCount; + logic [NUMWAYS-1:0] SRAMWordWriteEnableM, SRAMWordWriteEnableW; + logic [WORDSPERLINE-1:0] SRAMWordEnable [NUMWAYS-1:0]; + logic SelMemWriteDataM, SelMemWriteDataW; + logic [2:0] Funct3W; + + logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; + logic SRAMBlockWriteEnableM; + logic SRAMWriteEnable; + + logic SaveSRAMRead; + logic [1:0] AtomicW; + + - typedef enum {STATE_READY, - STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, - STATE_MISS_WRITE_BACK, - STATE_MISS_READ_SRAM, - STATE_AMO_MISS_FETCH_WDV, - STATE_AMO_MISS_FETCH_DONE, - STATE_AMO_MISS_WRITE_BACK, - STATE_AMO_MISS_READ_SRAM, - STATE_AMO_MISS_UPDATE, - STATE_AMO_MISS_WRITE, - STATE_AMO_UPDATE, - STATE_AMO_WRITE, - STATE_SRAM_BUSY, - STATE_PTW_READY, - STATE_PTW_FETCH, - STATE_UNCACHED} statetype; - - statetype CurrState, NextState; + // data path flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), .en(~StallW), .d(MemPAdrM), .q(MemPAdrW)); - mux3 #(INDEXLEN) + mux2 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSET-1:OFFSET]), .d1(MemPAdrM[INDEXLEN+OFFSET-1:OFFSET]), - .d2(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), - .s(AdrSel), - .y(SRAMAdr)); + .s(SelAdrM), + .y(AdrMuxOut)); - genvar way; + + mux2 #(INDEXLEN) + SelAdrlMux2(.d0(AdrMuxOut), + .d1(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .s(SRAMWordWriteEnableW), + .y(SRAMAdr)); + + + genvar way; generate for(way = 0; way < NUMWAYS; way = way + 1) begin DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN)) @@ -134,11 +139,11 @@ module dcache .WriteEnable(SRAMWriteEnable[way]), .WriteWordEnable(SRAMWordEnable[way]), .WriteData(SRAMWriteData), - .WriteTag(WriteTag), - .SetValid(SetValid), - .ClearValid(ClearValid), - .SetDirty(SetDirty), - .ClearDirty(ClearDirty), + .WriteTag(MemPAdrW[`PA_BITS-1:OFFSET+INDEXLEN]), + .SetValid(SetValidW), + .ClearValid(ClearValidW), + .SetDirty(SetDirtyW), + .ClearDirty(ClearDirtyW), .ReadData(ReadDataM[way]), .ReadTag(ReadTag[way]), .Valid(Valid[way]), @@ -150,10 +155,13 @@ module dcache always_ff @(posedge clk, posedge reset) begin if (reset) ReplacementBits <= '0; - else if (WriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; + else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; end - - assign Hit = |WayHit; + + // *** TODO add replacement policy + assign NewReplacement = '0; + + assign CacheHit = |WayHit; assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can @@ -183,13 +191,29 @@ module dcache .en(~StallW), .d(WriteDataM), .q(WriteDataW)); - + + flopr #(3) Funct3WReg(.clk(clk), + .reset(reset), + .d(Funct3M), + .q(Funct3W)); + subwordwrite subwordwrite(.HRDATA(ReadDataW), .HADDRD(MemPAdrM[`XLEN/8-1:0]), .HSIZED(Funct3W), .HWDATAIN(WriteDataW), .HWDATA(FinalWriteDataW)); + generate + if (`A_SUPPORTED) begin + logic [`XLEN-1:0] AMOResult; + amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W), + .result(AMOResult)); + mux2 #(`XLEN) wdmux(FinalWriteDataW, AMOResult, SelAMOWrite & AtomicW[1], FinalAMOWriteDataW); + end else + assign FinalAMOWriteDataW = FinalWriteDataW; + endgenerate + + // register the fetch data from the next level of memory. generate for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer @@ -199,23 +223,206 @@ module dcache .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); end endgenerate + + flopenr #(LOGWPL+1) + FetchCountReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(NextFetchCount), + .q(FetchCount)); + + assign NextFetchCount = FetchCount + 1'b1; + + assign AHBPAdr = (FetchCount << (`XLEN/8)) + MemPAdrM; + // remove later + assign AHBSize = 3'b000; + // mux between the CPU's write and the cache fetch. generate for(index = 0; index < WORDSPERLINE; index++) begin - assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalWriteDataW; + assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataW; end endgenerate mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsW), .d1(DCacheMemWriteData), - .s(SelMemWriteData), + .s(SRAMBlockWriteEnableM), .y(SRAMWriteData)); + + // control path *** eventually move to own module. + + logic AnyCPUReqM; + logic FetchCountFlag; + logic PreCntEn; + logic CntEn; + logic CntReset; + + typedef enum {STATE_READY, + STATE_READ_MISS_FETCH_WDV, + STATE_READ_MISS_FETCH_DONE, + STATE_READ_MISS_CHECK_EVICTED_DIRTY, + STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_READ_MISS_WRITE_CACHE_BLOCK, + STATE_READ_MISS_READ_WORD, + STATE_WRITE_MISS_FETCH_WDV, + STATE_WRITE_MISS_FETCH_DONE, + STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, + STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_WRITE_MISS_WRITE_CACHE_BLOCK, + STATE_WRITE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_CHECK_EVICTED_DIRTY, + STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_AMO_MISS_WRITE_CACHE_BLOCK, + STATE_AMO_MISS_READ_WORD, + STATE_AMO_MISS_UPDATE_WORD, + STATE_AMO_MISS_WRITE_WORD, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_SRAM_BUSY, + STATE_PTW_READY, + STATE_PTW_MISS_FETCH_WDV, + STATE_PTW_MISS_FETCH_DONE, + STATE_PTW_MISS_CHECK_EVICTED_DIRTY, + STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_PTW_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_MISS_READ_SRAM, + STATE_UNCACHED_WDV, + STATE_UNCACHED_DONE} statetype; + + statetype CurrState, NextState; + localparam FetchCountThreshold = WORDSPERLINE - 1; + + assign AnyCPUReqM = |MemRWM | (|AtomicM); + assign FetchCountFlag = (FetchCount == FetchCountThreshold); + + flopenr #(LOGWPL+1) + FetchCountReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(NextFetchCount), + .q(FetchCount)); + + assign NextFetchCount = FetchCount + 1'b1; + + assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableW; + + flopr #(1+4+2) + SRAMWritePipeReg(.clk(clk), + .reset(reset), + .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDiryM, ClearDirtyM, AtomicM}), + .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDiryM, ClearDirtyM, AtomicW})); + + + // fsm state regs + flopenl #(.TYPE(statetype)) + FSMReg(.clk(clk), + .load(reset), + .en(1'b1), + .val(STATE_READY), + .d(NextState), + .q(CurrState)); + + // next state logic and some state ouputs. + always_comb begin + DCacheStall = 1'b0; + SelAdrM = 2'b00; + PreCntEn = 1'b0; + SetValidM = 1'b0; + ClearValidM = 1'b0; + SetDirtyM = 1'b0; + ClearDirtyM = 1'b0; + SelMemWriteDataM = 1'b0; + SRAMWordWriteEnableM = 1'b0; + SRAMBlockWriteEnableM = 1'b0; + SaveSRAMRead = 1'b1; + CntReset = 1'b0; + + case (CurrState) + STATE_READY: begin + // sram busy + if (AnyCPUReqM & SRAMWordWriteEnableW) begin + NextState = STATE_BUSY; + DCacheStall = 1'b1; + end + // TLB Miss + else if(AnyCPUReqM & DTLBMissM) begin + NextState = STATE_PTW_MISS_FETCH_WDV; + end + // amo hit + else if(|AtomicM & ~UncachedM & ~FSMReg & CacheHit & ~DTLBMissM) begin + NextState = STATE_AMO_UPDATE; + DCacheStall = 1'b1; + end + // read hit valid cached + else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + NextState = STATE_READY; + DCacheStall = 1'b0; + end + // write hit valid cached + else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + NextState = STATE_READY; + DCacheStall = 1'b0; + SRAMWordWriteEnableM = 1'b1; + SetDirtyM = 1'b1; + end + // read miss valid cached + else if(MemRWM[1] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_READ_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end + // fault + else if(|MemRWM & FaultM & ~DTLBMissM) begin + NextState = STATE_READY; + end + end + STATE_AMO_UPDATE: begin + NextState = STATE_AMO_WRITE; + SaveSRAMRead = 1'b1; + SRAMWordWriteEnableM = 1'b1; // pipelined 1 cycle + end + STATE_AMO_WRITE: begin + NextState = STATE_READY; + SelAMOWrite = 1'b1; + end + + STATE_READ_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + if (FetchCountFlag & AHBAck) begin + NextState = STATE_READ_MISS_FETCH_DONE; + end else begin + NextState = STATE_READ_MISS_FETCH_WDV; + end + end + + STATE_READ_MISS_FETCH_DONE: begin + DCacheStall = 1'b1; + NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; + end + + STATE_PTW_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + AdrSel = 2'b01; + if (FetchCountFlag & AHBAck) begin + NextState = STATE_PTW_MISS_FETCH_DONE; + end else begin + NextState = STATE_PTW_MISS_FETCH_WDV; + end + end + default: begin + end + endcase + end + + assign CntEn = PreCntEn & AHBAck; + endmodule; // dcache - - From 93aa39ca3172ee44843ab3fc8503ec5e7f8e61cf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 8 Jul 2021 17:53:08 -0500 Subject: [PATCH 003/112] completed read miss branch through dcache fsm. The challenge now is to connect to ahb and lsu. --- wally-pipelined/src/cache/dcache.sv | 42 ++++++++++++++++++++++++++--- wally-pipelined/src/ebu/ahblite.sv | 7 +---- wally-pipelined/src/ifu/ifu.sv | 2 -- 3 files changed, 39 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 2988c6a4..84370328 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -81,6 +81,7 @@ module dcache logic SetValidM, ClearValidM, SetValidW, ClearValidW; logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] VictimReadDataMaskedM [NUMWAYS-1:0]; logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; logic [NUMWAYS-1:0] Valid, Dirty, WayHit; logic CacheHit; @@ -102,7 +103,11 @@ module dcache logic SaveSRAMRead; logic [1:0] AtomicW; - + logic [NUMWAYS-1:0] VictimWay; + logic [NUMWAYS-1:0] VictimDirtyWay; + logic [BLOCKLEN-1:0] VictimReadDataSelectWayM; + logic VictimDirty; + @@ -149,7 +154,11 @@ module dcache .Valid(Valid[way]), .Dirty(Dirty[way])); assign WayHit = Valid & (ReadTag[way] == MemAdrM); - assign ReadDataMaskedM = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + assign ReadDataMaskedM[way] = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + + // the cache block candiate for eviction + assign VictimReadDataMaskedM[way] = VictimWay[way] & ReadDataM[way]; + assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; end endgenerate @@ -160,9 +169,14 @@ module dcache // *** TODO add replacement policy assign NewReplacement = '0; + assign VictimWay = 4'b0001; + assign SRAMWriteEnable = SRAMBlockWriteEnableM ? VictimWay : '0; assign CacheHit = |WayHit; assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. + assign VictimReadDataSelectWayM = | VictimReadDataMaskedM; + assign VictimDirty = | VictimDirtyWay; + // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can // easily build a variable input mux. @@ -344,7 +358,9 @@ module dcache SRAMBlockWriteEnableM = 1'b0; SaveSRAMRead = 1'b1; CntReset = 1'b0; - + AHBRead = 1'b0; + AHBWrite = 1'b0; + case (CurrState) STATE_READY: begin // sram busy @@ -397,6 +413,7 @@ module dcache STATE_READ_MISS_FETCH_WDV: begin DCacheStall = 1'b1; PreCntEn = 1'b1; + AHBRead = 1'b1; if (FetchCountFlag & AHBAck) begin NextState = STATE_READ_MISS_FETCH_DONE; end else begin @@ -406,7 +423,24 @@ module dcache STATE_READ_MISS_FETCH_DONE: begin DCacheStall = 1'b1; - NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; + if(VictimDirt) begin + NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; + end else begin + NextState = STATE_READ_MISS_WRITE_CACHE_BLOCK; + end + end + + STATE_READ_MISS_WRITE_CACHE_BLOCK: begin + SRAMBlockWriteEnableM = 1'b1; + DCacheStall = 1'b1; + NextState = STATE_READ_MISS_READ_WORD; + SelAdrM = 1'b1; + end + + STATE_READ_MISS_READ_WORD: begin + DCacheStall = 1'b1; + SelAdrM = 1'b1; + NextState = STATE_READY; end STATE_PTW_MISS_FETCH_WDV: begin diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 4bd079e9..fda8f693 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -109,16 +109,11 @@ module ahblite ( // interface that might be used in place of the ahblite. always_comb case (BusState) - IDLE: /*if (MMUTranslate) ProposedNextBusState = MMUTRANSLATE; - else*/ if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD; + IDLE: if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD; else if (MemReadM) ProposedNextBusState = MEMREAD; // Memory has priority over instructions else if (MemWriteM) ProposedNextBusState = MEMWRITE; else if (InstrReadF) ProposedNextBusState = INSTRREAD; else ProposedNextBusState = IDLE; -/* -----\/----- EXCLUDED -----\/----- - MMUTRANSLATE: if (~HREADY) ProposedNextBusState = MMUTRANSLATE; - else ProposedNextBusState = IDLE; - -----/\----- EXCLUDED -----/\----- */ ATOMICREAD: if (~HREADY) ProposedNextBusState = ATOMICREAD; else ProposedNextBusState = ATOMICWRITE; ATOMICWRITE: if (~HREADY) ProposedNextBusState = ATOMICWRITE; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 8b113f8c..e306efa4 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -84,8 +84,6 @@ module ifu ( output logic InstrAccessFaultF, output logic ISquashBusAccessF -// output logic [5:0] IHSELRegionsF - ); logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; From 94c3fde7241d4349876930145508d864156dd90f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 8 Jul 2021 18:03:52 -0500 Subject: [PATCH 004/112] Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. --- wally-pipelined/src/lsu/lsu.sv | 128 ++++++++++----------- wally-pipelined/src/lsu/lsuArb.sv | 42 +++---- wally-pipelined/src/mmu/pagetablewalker.sv | 36 +++--- 3 files changed, 103 insertions(+), 103 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index ff47138c..51fa0a4a 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -123,22 +123,22 @@ module lsu logic [`XLEN-1:0] PageTableEntryM; logic [1:0] PageTypeM; logic DTLBWriteM; - logic [`XLEN-1:0] MMUReadPTE; + logic [`XLEN-1:0] HPTWReadPTE; logic MMUReady; logic HPTWStall; - logic [`XLEN-1:0] MMUPAdr; - logic MMUTranslate; + logic [`XLEN-1:0] HPTWPAdr; + logic HPTWTranslate; logic HPTWRead; - logic [1:0] MemRWMtoLSU; - logic [2:0] SizeToLSU; - logic [1:0] AtomicMtoLSU; - logic [`XLEN-1:0] MemAdrMtoLSU; - logic [`XLEN-1:0] WriteDataMtoLSU; - logic [`XLEN-1:0] ReadDataWFromLSU; - logic StallWtoLSU; - logic CommittedMfromLSU; - logic SquashSCWfromLSU; - logic DataMisalignedMfromLSU; + logic [1:0] MemRWMtoDCache; + logic [2:0] SizetoDCache; + logic [1:0] AtomicMtoDCache; + logic [`XLEN-1:0] MemAdrMtoDCache; + logic [`XLEN-1:0] WriteDataMtoDCache; + logic [`XLEN-1:0] ReadDataWfromDCache; + logic StallWtoDCache; + logic CommittedMfromDCache; + logic SquashSCWfromDCache; + logic DataMisalignedMfromDCache; logic HPTWReady; logic LSUStall; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. @@ -148,7 +148,7 @@ module lsu // for time being until we have a dcache the AHB Lite read bus HRDATAW will be connected to the // CPU's read data input ReadDataW. - assign ReadDataWFromLSU = HRDATAW; + assign ReadDataWfromDCache = HRDATAW; pagetablewalker pagetablewalker( @@ -166,11 +166,11 @@ module lsu .PageTypeM(PageTypeM), .ITLBWriteF(ITLBWriteF), .DTLBWriteM(DTLBWriteM), - .MMUReadPTE(MMUReadPTE), + .HPTWReadPTE(HPTWReadPTE), .MMUReady(HPTWReady), .HPTWStall(HPTWStall), - .MMUPAdr(MMUPAdr), - .MMUTranslate(MMUTranslate), + .HPTWPAdr(HPTWPAdr), + .HPTWTranslate(HPTWTranslate), .HPTWRead(HPTWRead), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), @@ -182,10 +182,10 @@ module lsu lsuArb arbiter(.clk(clk), .reset(reset), // HPTW connection - .HPTWTranslate(MMUTranslate), + .HPTWTranslate(HPTWTranslate), .HPTWRead(HPTWRead), - .HPTWPAdr(MMUPAdr), - .HPTWReadPTE(MMUReadPTE), + .HPTWPAdr(HPTWPAdr), + .HPTWReadPTE(HPTWReadPTE), .HPTWStall(HPTWStall), // CPU connection .MemRWM(MemRWM), @@ -201,23 +201,23 @@ module lsu .DCacheStall(DCacheStall), // LSU .DisableTranslation(DisableTranslation), - .MemRWMtoLSU(MemRWMtoLSU), - .SizeToLSU(SizeToLSU), - .AtomicMtoLSU(AtomicMtoLSU), - .MemAdrMtoLSU(MemAdrMtoLSU), - .WriteDataMtoLSU(WriteDataMtoLSU), // *** ?????????????? - .StallWtoLSU(StallWtoLSU), - .CommittedMfromLSU(CommittedMfromLSU), - .SquashSCWfromLSU(SquashSCWfromLSU), - .DataMisalignedMfromLSU(DataMisalignedMfromLSU), - .ReadDataWFromLSU(ReadDataWFromLSU), + .MemRWMtoDCache(MemRWMtoDCache), + .SizetoDCache(SizetoDCache), + .AtomicMtoDCache(AtomicMtoDCache), + .MemAdrMtoDCache(MemAdrMtoDCache), + .WriteDataMtoDCache(WriteDataMtoDCache), // *** ?????????????? + .StallWtoDCache(StallWtoDCache), + .CommittedMfromDCache(CommittedMfromDCache), + .SquashSCWfromDCache(SquashSCWfromDCache), + .DataMisalignedMfromDCache(DataMisalignedMfromDCache), + .ReadDataWfromDCache(ReadDataWfromDCache), .DataStall(LSUStall)); mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) - dmmu(.VirtualAddress(MemAdrMtoLSU), - .Size(SizeToLSU[1:0]), + dmmu(.VirtualAddress(MemAdrMtoDCache), + .Size(SizetoDCache[1:0]), .PTE(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), @@ -228,8 +228,8 @@ module lsu .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), .AtomicAccessM(AtomicMaskedM[1]), - .WriteAccessM(MemRWMtoLSU[0]), - .ReadAccessM(MemRWMtoLSU[1]), + .WriteAccessM(MemRWMtoDCache[0]), + .ReadAccessM(MemRWMtoDCache[1]), .SquashBusAccess(DSquashBusAccessM), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), @@ -237,36 +237,36 @@ module lsu .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? // Specify which type of page fault is occurring - assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLSU[1]; - assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLSU[0]; + assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoDCache[1]; + assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoDCache[0]; // Determine if an Unaligned access is taking place always_comb - case(SizeToLSU[1:0]) - 2'b00: DataMisalignedMfromLSU = 0; // lb, sb, lbu - 2'b01: DataMisalignedMfromLSU = MemAdrMtoLSU[0]; // lh, sh, lhu - 2'b10: DataMisalignedMfromLSU = MemAdrMtoLSU[1] | MemAdrMtoLSU[0]; // lw, sw, flw, fsw, lwu - 2'b11: DataMisalignedMfromLSU = |MemAdrMtoLSU[2:0]; // ld, sd, fld, fsd + case(SizetoDCache[1:0]) + 2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu + 2'b01: DataMisalignedMfromDCache = MemAdrMtoDCache[0]; // lh, sh, lhu + 2'b10: DataMisalignedMfromDCache = MemAdrMtoDCache[1] | MemAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu + 2'b11: DataMisalignedMfromDCache = |MemAdrMtoDCache[2:0]; // ld, sd, fld, fsd endcase // Squash unaligned data accesses and failed store conditionals // *** this is also the place to squash if the cache is hit - // Changed DataMisalignedMfromLSU to a larger combination of trap sources + // Changed DataMisalignedMfromDCache to a larger combination of trap sources // NonBusTrapM is anything that the bus doesn't contribute to producing // By contrast, using TrapM results in circular logic errors - assign MemReadM = MemRWMtoLSU[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; - assign MemWriteM = MemRWMtoLSU[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; - assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoLSU : 2'b00 ; + assign MemReadM = MemRWMtoDCache[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; + assign MemWriteM = MemRWMtoDCache[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; + assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoDCache : 2'b00 ; assign MemAccessM = MemReadM | MemWriteM; // Determine if M stage committed // Reset whenever unstalled. Set when access successfully occurs - flopr #(1) committedMreg(clk,reset,(CommittedMfromLSU | CommitM) & StallM,preCommittedM); - assign CommittedMfromLSU = preCommittedM | CommitM; + flopr #(1) committedMreg(clk,reset,(CommittedMfromDCache | CommitM) & StallM,preCommittedM); + assign CommittedMfromDCache = preCommittedM | CommitM; // Determine if address is valid - assign LoadMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[1]; - assign StoreMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[0]; + assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; + assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; // Handle atomic load reserved / store conditional generate @@ -275,9 +275,9 @@ module lsu logic ReservationValidM, ReservationValidW; logic lrM, scM, WriteAdrMatchM; - assign lrM = MemReadM && AtomicMtoLSU[0]; - assign scM = MemRWMtoLSU[0] && AtomicMtoLSU[0]; - assign WriteAdrMatchM = MemRWMtoLSU[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; + assign lrM = MemReadM && AtomicMtoDCache[0]; + assign scM = MemRWMtoDCache[0] && AtomicMtoDCache[0]; + assign WriteAdrMatchM = MemRWMtoDCache[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve @@ -286,10 +286,10 @@ module lsu end flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); - flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoLSU, SquashSCM, SquashSCWfromLSU); + flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCWfromDCache); end else begin // Atomic operations not supported assign SquashSCM = 0; - assign SquashSCWfromLSU = 0; + assign SquashSCWfromDCache = 0; end endgenerate @@ -319,10 +319,10 @@ module lsu end else if (AtomicMaskedM[1]) begin NextState = STATE_FETCH_AMO_1; // *** should be some misalign check LSUStall = 1'b1; - end else if((MemReadM & AtomicMtoLSU[0]) | (MemWriteM & AtomicMtoLSU[0])) begin + end else if((MemReadM & AtomicMtoDCache[0]) | (MemWriteM & AtomicMtoDCache[0])) begin NextState = STATE_FETCH_AMO_2; LSUStall = 1'b1; - end else if (MemAccessM & ~DataMisalignedMfromLSU) begin + end else if (MemAccessM & ~DataMisalignedMfromDCache) begin NextState = STATE_FETCH; LSUStall = 1'b1; end else begin @@ -339,9 +339,9 @@ module lsu end STATE_FETCH_AMO_2: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoLSU) begin + if (MemAckW & ~StallWtoDCache) begin NextState = STATE_FETCH_AMO_2; - end else if (MemAckW & StallWtoLSU) begin + end else if (MemAckW & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH_AMO_2; @@ -349,9 +349,9 @@ module lsu end STATE_FETCH: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoLSU) begin + if (MemAckW & ~StallWtoDCache) begin NextState = STATE_READY; - end else if (MemAckW & StallWtoLSU) begin + end else if (MemAckW & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH; @@ -359,7 +359,7 @@ module lsu end STATE_STALLED: begin LSUStall = 1'b0; - if (~StallWtoLSU) begin + if (~StallWtoDCache) begin NextState = STATE_READY; end else begin NextState = STATE_STALLED; @@ -370,7 +370,7 @@ module lsu if (DTLBWriteM) begin NextState = STATE_READY; LSUStall = 1'b1; - end else if (MemReadM & ~DataMisalignedMfromLSU) begin + end else if (MemReadM & ~DataMisalignedMfromDCache) begin NextState = STATE_PTW_FETCH; end else begin NextState = STATE_PTW_READY; @@ -397,8 +397,8 @@ module lsu end // always_comb // *** for now just pass through size - assign SizeFromLSU = SizeToLSU; - assign StallWfromLSU = StallWtoLSU; + assign SizeFromLSU = SizetoDCache; + assign StallWfromLSU = StallWtoDCache; endmodule diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 23e88970..0c7730f1 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -53,17 +53,17 @@ module lsuArb // to LSU output logic DisableTranslation, - output logic [1:0] MemRWMtoLSU, - output logic [2:0] SizeToLSU, - output logic [1:0] AtomicMtoLSU, - output logic [`XLEN-1:0] MemAdrMtoLSU, - output logic [`XLEN-1:0] WriteDataMtoLSU, - output logic StallWtoLSU, + output logic [1:0] MemRWMtoDCache, + output logic [2:0] SizetoDCache, + output logic [1:0] AtomicMtoDCache, + output logic [`XLEN-1:0] MemAdrMtoDCache, + output logic [`XLEN-1:0] WriteDataMtoDCache, + output logic StallWtoDCache, // from LSU - input logic CommittedMfromLSU, - input logic SquashSCWfromLSU, - input logic DataMisalignedMfromLSU, - input logic [`XLEN-1:0] ReadDataWFromLSU, + input logic CommittedMfromDCache, + input logic SquashSCWfromDCache, + input logic DataMisalignedMfromDCache, + input logic [`XLEN-1:0] ReadDataWfromDCache, input logic DataStall ); @@ -136,25 +136,25 @@ module lsuArb // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate); - assign MemRWMtoLSU = SelPTW ? {HPTWRead, 1'b0} : MemRWM; + assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM; generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw endgenerate - mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, SizeToLSU); + mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, SizetoDCache); - assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM; - assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM; - assign WriteDataMtoLSU = SelPTW ? `XLEN'b0 : WriteDataM; - assign StallWtoLSU = SelPTW ? 1'b0 : StallW; + assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; + assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; + assign WriteDataMtoDCache = SelPTW ? `XLEN'b0 : WriteDataM; + assign StallWtoDCache = SelPTW ? 1'b0 : StallW; // demux the inputs from LSU to walker or cpu's data port. - assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWFromLSU; // probably can avoid this demux - assign HPTWReadPTE = SelPTW ? ReadDataWFromLSU : `XLEN'b0 ; // probably can avoid this demux - assign CommittedM = SelPTW ? 1'b0 : CommittedMfromLSU; - assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromLSU; - assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromLSU; + assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux + assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux + assign CommittedM = SelPTW ? 1'b0 : CommittedMfromDCache; + assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache; + assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. // not clear at all. I think it should be LSUStall from the LSU, // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one). diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 6357f1c6..83d15f9b 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -54,13 +54,13 @@ module pagetablewalker // *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU - input logic [`XLEN-1:0] MMUReadPTE, + input logic [`XLEN-1:0] HPTWReadPTE, input logic MMUReady, input logic HPTWStall, // *** modify to send to LSU - output logic [`XLEN-1:0] MMUPAdr, // this probalby should be `PA_BITS wide - output logic MMUTranslate, // *** rename to HPTWReq + output logic [`XLEN-1:0] HPTWPAdr, // this probalby should be `PA_BITS wide + output logic HPTWTranslate, // *** rename to HPTWReq output logic HPTWRead, @@ -158,8 +158,8 @@ module pagetablewalker (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || (WalkerState == FAULT); - assign MMUTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; - //assign MMUTranslate = DTLBMissM | ITLBMissF; + assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; + //assign HPTWTranslate = DTLBMissM | ITLBMissF; // unswizzle PTE bits assign {Dirty, Accessed, Global, User, @@ -203,7 +203,7 @@ module pagetablewalker case (WalkerState) IDLE: begin - if (MMUTranslate && SvMode == `SV32) begin // *** Added SvMode + if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode NextWalkerState = START; end else begin NextWalkerState = IDLE; @@ -303,15 +303,15 @@ module pagetablewalker // a load delay hazard. This will require rewriting the walker fsm. // also need a new signal to save. Should be a mealy output of the fsm // request followed by ~stall. - flopenr #(32) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE); - //mux2 #(32) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE); + flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); assign CurrentPTE = SavedPTE; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; // Assign outputs to ahblite // *** Currently truncate address to 32 bits. This must be changed if // we support larger physical address spaces - assign MMUPAdr = TranslationPAdr[31:0]; + assign HPTWPAdr = TranslationPAdr[31:0]; end else begin @@ -326,7 +326,7 @@ module pagetablewalker WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; -----/\----- EXCLUDED -----/\----- */ - //assign HPTWRead = (WalkerState == IDLE && MMUTranslate) || WalkerState == LEVEL3 || + //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || // WalkerState == LEVEL2 || WalkerState == LEVEL1; @@ -345,7 +345,7 @@ module pagetablewalker case (WalkerState) IDLE: begin - if (MMUTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin + if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin NextWalkerState = START; end else begin NextWalkerState = IDLE; @@ -353,11 +353,11 @@ module pagetablewalker end START: begin - if (MMUTranslate && SvMode == `SV48) begin + if (HPTWTranslate && SvMode == `SV48) begin NextWalkerState = LEVEL3_WDV; TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; HPTWRead = 1'b1; - end else if (MMUTranslate && SvMode == `SV39) begin + end else if (HPTWTranslate && SvMode == `SV39) begin NextWalkerState = LEVEL2_WDV; TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; HPTWRead = 1'b1; @@ -541,20 +541,20 @@ module pagetablewalker // Capture page table entry from ahblite - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE); - //mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE); + flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); assign CurrentPTE = SavedPTE; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; // Assign outputs to ahblite // *** Currently truncate address to 32 bits. This must be changed if // we support larger physical address spaces - assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + assign HPTWPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; end //endgenerate end else begin - assign MMUPAdr = 0; - assign MMUTranslate = 0; + assign HPTWPAdr = 0; + assign HPTWTranslate = 0; assign HPTWRead = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; From ec80cc18206ec40c14f7495d1a4e98d187ca083f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 9 Jul 2021 15:16:38 -0500 Subject: [PATCH 005/112] Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. Also faults and the dcache ptw interlock are not implemented. --- wally-pipelined/src/cache/DCacheMem.sv | 19 +- wally-pipelined/src/cache/ICacheCntrl.sv | 1 + wally-pipelined/src/cache/dcache.sv | 190 ++++++++++-------- wally-pipelined/src/ebu/ahblite.sv | 146 ++++++-------- wally-pipelined/src/ieu/datapath.sv | 3 +- wally-pipelined/src/ieu/ieu.sv | 2 +- wally-pipelined/src/lsu/lsu.sv | 127 +++++++----- wally-pipelined/src/lsu/lsuArb.sv | 15 +- .../src/wally/wallypipelinedhart.sv | 113 +++++------ 9 files changed, 322 insertions(+), 294 deletions(-) diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index b82858db..70668b5d 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -46,6 +46,9 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 output logic Dirty ); + logic [NUMLINES-1:0] ValidBits, DirtyBits; + + genvar words; generate @@ -69,22 +72,6 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 .WriteEnable(WriteEnable)); - sram1rw #(.DEPTH(BLOCKLEN), - .WIDTH(NUMLINES)) - CacheDataMem(.clk(clk), - .Addr(Adr), - .ReadData(ReadData), - .WriteData(WriteData), - .WriteEnable(WriteEnable)); - - sram1rw #(.DEPTH(TAGLEN), - .WIDTH(NUMLINES)) - CacheTagMem(.clk(clk), - .Addr(Adr), - .ReadData(ReadTag), - .WriteData(WriteTag), - .WriteEnable(WriteEnable)); - always_ff @(posedge clk, posedge reset) begin if (reset) ValidBits <= {NUMLINES{1'b0}}; diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 2b5ce55d..629ec7cc 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -196,6 +196,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0; assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit. // verilator lint_off WIDTH + // *** Bug width is wrong. assign FetchCountFlag = (FetchCount == FetchCountThreshold); // verilator lint_on WIDTH diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 84370328..65a0fe8b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -27,35 +27,35 @@ module dcache (input logic clk, - input logic reset, - input logic StallM, - input logic StallW, - input logic FlushM, - input logic FlushW, + input logic reset, + input logic StallM, + input logic StallW, + input logic FlushM, + input logic FlushW, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [1:0] AtomicM, - input logic [`PA_BITS-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [6:0] Funct7M, + input logic [1:0] AtomicM, + input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, - output logic DCacheStall, + output logic DCacheStall, // inputs from TLB and PMA/P - input logic FaultM, - input logic DTLBMissM, - input logic UncachedM, + input logic FaultM, + input logic DTLBMissM, + input logic UncachedM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb - output logic AHBRead, - output logic AHBWrite, - input logic AHBAck, // from ahb + output logic AHBRead, + output logic AHBWrite, + input logic AHBAck, // from ahb input logic [`XLEN-1:0] HRDATA, // from ahb - output logic [`XLEN-1:0] HWDATA, // to ahb - output logic [2:0] AHBSize + output logic [`XLEN-1:0] HWDATA // to ahb ); localparam integer BLOCKLEN = 256; @@ -78,21 +78,23 @@ module dcache logic [NUMWAYS-1:0] WriteEnable; logic [NUMWAYS-1:0] WriteWordEnable; logic [BLOCKLEN-1:0] SRAMWriteData; + logic [BLOCKLEN-1:0] DCacheMemWriteData; logic SetValidM, ClearValidM, SetValidW, ClearValidW; logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; - logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; - logic [BLOCKLEN-1:0] VictimReadDataMaskedM [NUMWAYS-1:0]; - logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] ReadDataBlockWayM [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] VictimReadDataBLockWayMaskedM [NUMWAYS-1:0]; + logic [TAGLEN-1:0] ReadTag [NUMWAYS-1:0]; logic [NUMWAYS-1:0] Valid, Dirty, WayHit; logic CacheHit; - logic [NUMREPL_BITS-1:0] ReplacementBits, NewReplacement; - logic [BLOCKLEN-1:0] ReadDataSelectWayM; - logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; + logic [NUMREPL_BITS-1:0] ReplacementBits [NUMLINES-1:0]; + logic [NUMREPL_BITS-1:0] NewReplacement [NUMLINES-1:0]; + logic [BLOCKLEN-1:0] ReadDataBlockM; + logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; logic [BLOCKLEN-1:0] FinalWriteDataWordsW; logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [NUMWAYS-1:0] SRAMWordWriteEnableM, SRAMWordWriteEnableW; logic [WORDSPERLINE-1:0] SRAMWordEnable [NUMWAYS-1:0]; logic SelMemWriteDataM, SelMemWriteDataW; logic [2:0] Funct3W; @@ -100,16 +102,27 @@ module dcache logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; logic SRAMBlockWriteEnableM; logic SRAMWriteEnable; + logic [NUMWAYS-1:0] SRAMWayWriteEnable; + logic SaveSRAMRead; logic [1:0] AtomicW; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; - logic [BLOCKLEN-1:0] VictimReadDataSelectWayM; + logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic VictimDirty; - + logic SelAMOWrite; + logic [6:0] Funct7W; + logic [INDEXLEN-1:0] AdrMuxOut; + + flopenr #(7) Funct7WReg(.clk(clk), + .reset(reset), + .en(~StallW), + .d(Funct7M), + .q(Funct7W)); + // data path @@ -120,15 +133,15 @@ module dcache .q(MemPAdrW)); mux2 #(INDEXLEN) - AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSET-1:OFFSET]), - .d1(MemPAdrM[INDEXLEN+OFFSET-1:OFFSET]), + AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SelAdrM), .y(AdrMuxOut)); mux2 #(INDEXLEN) SelAdrlMux2(.d0(AdrMuxOut), - .d1(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SRAMWordWriteEnableW), .y(SRAMAdr)); @@ -140,68 +153,89 @@ module dcache MemWay(.clk(clk), .reset(reset), .Adr(SRAMAdr), - .WAdr(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), - .WriteEnable(SRAMWriteEnable[way]), + .WAdr(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .WriteEnable(SRAMWayWriteEnable[way]), .WriteWordEnable(SRAMWordEnable[way]), .WriteData(SRAMWriteData), - .WriteTag(MemPAdrW[`PA_BITS-1:OFFSET+INDEXLEN]), + .WriteTag(MemPAdrW[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .SetValid(SetValidW), .ClearValid(ClearValidW), .SetDirty(SetDirtyW), .ClearDirty(ClearDirtyW), - .ReadData(ReadDataM[way]), + .ReadData(ReadDataBlockWayM[way]), .ReadTag(ReadTag[way]), .Valid(Valid[way]), .Dirty(Dirty[way])); - assign WayHit = Valid & (ReadTag[way] == MemAdrM); - assign ReadDataMaskedM[way] = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + assign WayHit[way] = Valid[way] & (ReadTag[way] == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]); + assign ReadDataBlockWayMaskedM[way] = Valid[way] ? ReadDataBlockWayM[way] : '0; // first part of AO mux. // the cache block candiate for eviction - assign VictimReadDataMaskedM[way] = VictimWay[way] & ReadDataM[way]; + assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0; assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; end endgenerate always_ff @(posedge clk, posedge reset) begin - if (reset) ReplacementBits <= '0; - else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; + if (reset) begin + for(int index = 0; index < NUMLINES-1; index++) + ReplacementBits[index] <= '0; + end + else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement; end // *** TODO add replacement policy - assign NewReplacement = '0; + genvar index; + generate + for(index = 0; index < NUMLINES-1; index++) + assign NewReplacement[index] = '0; + endgenerate assign VictimWay = 4'b0001; - assign SRAMWriteEnable = SRAMBlockWriteEnableM ? VictimWay : '0; + mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0), + .d1(SRAMBlockWriteEnableM ? VictimWay : '0), + .s(SRAMBlockWriteEnableM), + .y(SRAMWayWriteEnable)); + + assign CacheHit = |WayHit; - assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. - assign VictimReadDataSelectWayM = | VictimReadDataMaskedM; + // ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways. + // Need to OR together each way in a bitwise manner. + // Final part of the AO Mux. + always_comb begin + ReadDataBlockM = '0; + VictimReadDataBlockM = '0; + for(int index = 0; index < NUMWAYS; index++) begin + ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM; + VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM; + end + end assign VictimDirty = | VictimDirtyWay; // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can // easily build a variable input mux. - genvar index; generate for (index = 0; index < WORDSPERLINE; index++) begin - assign ReadDataSelectWayM[index] = ReadDataSelectM[((index+1)*`XLEN)-1: (index*`XLEN)]; + assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)]; end endgenerate // variable input mux - assign WordReadDataM = ReadDataSelectWayM[MemPAdrM[WORDSPERLINE+$clog2(`XLEN/8) : $clog2(`XLEN/8)]]; + assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; // finally swr - subwordread subwordread(.HRDATA(WordReadDataM), - .HADDRD(MemPAdrM[`XLEN/8-1:0]), - .HSIZED(Funct3M), - .HRDATAMasked(FinalReadDataM)); + // *** BUG fix HSIZED? why was it this way? + subwordread subwordread(.HRDATA(ReadDataWordM), + .HADDRD(MemPAdrM[2:0]), + .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), + .HRDATAMasked(FinalReadDataWordM)); - flopen #(XLEN) ReadDataWReg(.clk(clk), + flopen #(`XLEN) ReadDataWReg(.clk(clk), .en(~StallW), - .d(FinalReadDataM), + .d(FinalReadDataWordM), .q(ReadDataW)); // write path - flopen #(XLEN) WriteDataWReg(.clk(clk), + flopen #(`XLEN) WriteDataWReg(.clk(clk), .en(~StallW), .d(WriteDataM), .q(WriteDataW)); @@ -212,15 +246,15 @@ module dcache .q(Funct3W)); subwordwrite subwordwrite(.HRDATA(ReadDataW), - .HADDRD(MemPAdrM[`XLEN/8-1:0]), - .HSIZED(Funct3W), + .HADDRD(MemPAdrM[2:0]), + .HSIZED({Funct3W[2], 1'b0, Funct3W[1:0]}), .HWDATAIN(WriteDataW), .HWDATA(FinalWriteDataW)); generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W), + amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W[1:0]), .result(AMOResult)); mux2 #(`XLEN) wdmux(FinalWriteDataW, AMOResult, SelAMOWrite & AtomicW[1], FinalAMOWriteDataW); end else @@ -238,19 +272,16 @@ module dcache end endgenerate - flopenr #(LOGWPL+1) - FetchCountReg(.clk(clk), - .reset(reset | CntReset), - .en(CntEn), - .d(NextFetchCount), - .q(FetchCount)); - - assign NextFetchCount = FetchCount + 1'b1; - - assign AHBPAdr = (FetchCount << (`XLEN/8)) + MemPAdrM; - // remove later - assign AHBSize = 3'b000; - + // *** Coding style. this is just awful. The purpose is to align FetchCount to the + // size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length. + generate + if (`XLEN == 32) begin + assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + MemPAdrM; + end else begin + assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + MemPAdrM; + end + endgenerate + // mux between the CPU's write and the cache fetch. generate @@ -315,7 +346,7 @@ module dcache assign AnyCPUReqM = |MemRWM | (|AtomicM); - assign FetchCountFlag = (FetchCount == FetchCountThreshold); + assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); flopenr #(LOGWPL+1) FetchCountReg(.clk(clk), @@ -331,8 +362,8 @@ module dcache flopr #(1+4+2) SRAMWritePipeReg(.clk(clk), .reset(reset), - .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDiryM, ClearDirtyM, AtomicM}), - .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDiryM, ClearDirtyM, AtomicW})); + .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}), + .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDirtyM, ClearDirtyM, AtomicW})); // fsm state regs @@ -347,7 +378,7 @@ module dcache // next state logic and some state ouputs. always_comb begin DCacheStall = 1'b0; - SelAdrM = 2'b00; + SelAdrM = 1'b0; PreCntEn = 1'b0; SetValidM = 1'b0; ClearValidM = 1'b0; @@ -360,12 +391,13 @@ module dcache CntReset = 1'b0; AHBRead = 1'b0; AHBWrite = 1'b0; - + SelAMOWrite = 1'b0; + case (CurrState) STATE_READY: begin // sram busy if (AnyCPUReqM & SRAMWordWriteEnableW) begin - NextState = STATE_BUSY; + NextState = STATE_SRAM_BUSY; DCacheStall = 1'b1; end // TLB Miss @@ -373,7 +405,7 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit - else if(|AtomicM & ~UncachedM & ~FSMReg & CacheHit & ~DTLBMissM) begin + else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; end @@ -423,7 +455,7 @@ module dcache STATE_READ_MISS_FETCH_DONE: begin DCacheStall = 1'b1; - if(VictimDirt) begin + if(VictimDirty) begin NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; end else begin NextState = STATE_READ_MISS_WRITE_CACHE_BLOCK; @@ -445,7 +477,7 @@ module dcache STATE_PTW_MISS_FETCH_WDV: begin DCacheStall = 1'b1; - AdrSel = 2'b01; + SelAdrM = 1'b1; if (FetchCountFlag & AHBAck) begin NextState = STATE_PTW_MISS_FETCH_DONE; end else begin diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index fda8f693..302b5075 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -35,53 +35,51 @@ package ahbliteState; endpackage module ahblite ( - input logic clk, reset, - input logic StallW, FlushW, + input logic clk, reset, + input logic StallW, // Load control - input logic UnsignedLoadM, - input logic [1:0] AtomicMaskedM, - input logic [6:0] Funct7M, + input logic UnsignedLoadM, + input logic [1:0] AtomicMaskedM, + input logic [6:0] Funct7M, // Signals from Instruction Cache - input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram - input logic InstrReadF, - output logic [`XLEN-1:0] InstrRData, - output logic InstrAckF, + input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram + input logic InstrReadF, + output logic [`XLEN-1:0] InstrRData, + output logic InstrAckF, // Signals from Data Cache - input logic [`PA_BITS-1:0] MemPAdrM, - input logic MemReadM, MemWriteM, - input logic [`XLEN-1:0] WriteDataM, - input logic [1:0] MemSizeM, - //output logic DataStall, - // Signals from MMU - // Signals from PMA checker - input logic DSquashBusAccessM, ISquashBusAccessF, - // Signals to PMA checker (metadata of proposed access) + input logic [`PA_BITS-1:0] DCtoAHBPAdrM, + input logic DCtoAHBReadM, + input logic DCtoAHBWriteM, + input logic [`XLEN-1:0] DCtoAHBWriteData, + output logic [`XLEN-1:0] DCfromAHBReadData, + input logic [1:0] MemSizeM, // *** remove + output logic DCfromAHBAck, // Return from bus - output logic [`XLEN-1:0] HRDATAW, + output logic [`XLEN-1:0] HRDATAW, // AHB-Lite external signals - input logic [`AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [31:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, + input logic [`AHBW-1:0] HRDATA, + input logic HREADY, HRESP, + output logic HCLK, HRESETn, + output logic [31:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, // Delayed signals for writes - output logic [2:0] HADDRD, - output logic [3:0] HSIZED, - output logic HWRITED, + output logic [2:0] HADDRD, + output logic [3:0] HSIZED, + output logic HWRITED, // Stalls - output logic CommitM, MemAckW + output logic CommitM ); logic GrantData; logic [31:0] AccessAddress; logic [2:0] AccessSize, PTESize, ISize; - logic [`AHBW-1:0] HRDATAMasked, ReadDataM, CapturedHRDATAMasked, HRDATANext, WriteData; + logic [`AHBW-1:0] HRDATAMasked, ReadDataM, HRDATANext, CapturedHRDATAMasked, WriteData; logic IReady, DReady; logic CaptureDataM,CapturedDataAvailable; @@ -95,7 +93,7 @@ module ahblite ( // while an instruction read is occuring, the instruction read finishes before // the data access can take place. import ahbliteState::*; - statetype BusState, ProposedNextBusState, NextBusState; + statetype BusState, NextBusState; flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); @@ -109,49 +107,32 @@ module ahblite ( // interface that might be used in place of the ahblite. always_comb case (BusState) - IDLE: if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD; - else if (MemReadM) ProposedNextBusState = MEMREAD; // Memory has priority over instructions - else if (MemWriteM) ProposedNextBusState = MEMWRITE; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - ATOMICREAD: if (~HREADY) ProposedNextBusState = ATOMICREAD; - else ProposedNextBusState = ATOMICWRITE; - ATOMICWRITE: if (~HREADY) ProposedNextBusState = ATOMICWRITE; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - MEMREAD: if (~HREADY) ProposedNextBusState = MEMREAD; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - MEMWRITE: if (~HREADY) ProposedNextBusState = MEMWRITE; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - INSTRREAD: if (~HREADY) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; // if (InstrReadF still high) - default: ProposedNextBusState = IDLE; + IDLE: if (AtomicMaskedM[1]) NextBusState = ATOMICREAD; + else if (DCtoAHBReadM) NextBusState = MEMREAD; // Memory has priority over instructions + else if (DCtoAHBWriteM) NextBusState = MEMWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + ATOMICREAD: if (~HREADY) NextBusState = ATOMICREAD; + else NextBusState = ATOMICWRITE; + ATOMICWRITE: if (~HREADY) NextBusState = ATOMICWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMREAD: if (~HREADY) NextBusState = MEMREAD; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMWRITE: if (~HREADY) NextBusState = MEMWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; + else NextBusState = IDLE; // if (InstrReadF still high) + default: NextBusState = IDLE; endcase - // Determine access type (important for determining whether to fault) -// (ProposedNextBusState == MMUTRANSLATE); - - // The PMA and PMP checkers can decide to squash the access - // *** this probably needs to be controlled by the caches rather than EBU dh 7/2/11 - assign NextBusState = (DSquashBusAccessM || ISquashBusAccessF) ? IDLE : ProposedNextBusState; - - // stall signals - // Note that we need to extend both stalls when MMUTRANSLATE goes to idle, - // since translation might not be complete. - // *** Ross Thompson remove this datastall -/* -----\/----- EXCLUDED -----\/----- - assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || - (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE)); - -----/\----- EXCLUDED -----/\----- */ - - // bus outputs - assign #1 GrantData = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == MEMWRITE) || - (ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE); - assign #1 AccessAddress = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0]; + assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || + (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE); + assign #1 AccessAddress = (GrantData) ? DCtoAHBPAdrM[31:0] : InstrPAdrF[31:0]; //assign #1 HADDR = (MMUTranslate) ? MMUPAdr[31:0] : AccessAddress; assign #1 HADDR = AccessAddress; generate @@ -180,11 +161,11 @@ module ahblite ( //assign MMUReady = (BusState == MMUTRANSLATE && HREADY); assign InstrRData = HRDATA; + assign DCfromAHBReadData = HRDATA; assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); assign CommitM = (BusState == MEMREAD) || (BusState == MEMWRITE) || (BusState == ATOMICREAD) || (BusState == ATOMICWRITE); // *** Bracker 6/5/21: why is this W stage? - assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE) || - ((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE)); + assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); //assign MMUReadPTE = HRDATA; // Carefully decide when to update ReadDataW // ReadDataMstored holds the most recent memory read. @@ -208,17 +189,20 @@ module ahblite ( flopr #(`XLEN) ReadDataOldWReg(clk, reset, HRDATANext, HRDATAW); // Extract and sign-extend subwords if necessary - subwordread swr(.*); + subwordread swr(.HRDATA(HRDATA), + .HADDRD(HADDRD), + .HSIZED(HSIZED), + .HRDATAMasked(HRDATAMasked)); // Handle AMO instructions if applicable generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(HRDATAW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM), + amoalu amoalu(.srca(HRDATAW), .srcb(DCtoAHBWriteData), .funct(Funct7M), .width(MemSizeM), .result(AMOResult)); - mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMaskedM[1], WriteData); + mux2 #(`XLEN) wdmux(DCtoAHBWriteData, AMOResult, AtomicMaskedM[1], WriteData); end else - assign WriteData = WriteDataM; + assign WriteData = DCtoAHBWriteData; endgenerate endmodule diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index f041fce6..1c8e84c8 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -50,7 +50,7 @@ module datapath ( input logic FWriteIntM, input logic [`XLEN-1:0] FIntResM, output logic [`XLEN-1:0] SrcAM, - output logic [`XLEN-1:0] WriteDataM, MemAdrM, + output logic [`XLEN-1:0] WriteDataM, MemAdrM, MemAdrE, // Writeback stage signals input logic StallW, FlushW, input logic FWriteIntW, @@ -120,6 +120,7 @@ module datapath ( flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM); assign MemAdrM = ALUResultM; + assign MemAdrE = ALUResultE; flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); flopenrc #(5) RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM); mux2 #(`XLEN) resultmuxM(ALUResultM, FIntResM, FWriteIntM, ResultM); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 87e21d79..39237806 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -49,7 +49,7 @@ module ieu ( input logic SquashSCW, // from LSU output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU - output logic [`XLEN-1:0] MemAdrM, WriteDataM, // Address and write data to LSU + output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU output logic [2:0] Funct3M, // size and signedness to LSU output logic [`XLEN-1:0] SrcAM, // to privilege and fpu diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 51fa0a4a..1afd92ad 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -32,12 +32,13 @@ module lsu ( input logic clk, reset, input logic StallM, FlushM, StallW, FlushW, - output logic DCacheStall, + output logic LSUStall, // Memory Stage // connected to cpu (controls) input logic [1:0] MemRWM, input logic [2:0] Funct3M, + input logic [6:0] Funct7M, input logic [1:0] AtomicM, output logic CommittedM, output logic SquashSCW, @@ -45,6 +46,7 @@ module lsu // address and write data input logic [`XLEN-1:0] MemAdrM, + input logic [`XLEN-1:0] MemAdrE, input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, @@ -60,14 +62,12 @@ module lsu // connect to ahb input logic CommitM, // should this be generated in the abh interface? - output logic [`PA_BITS-1:0] MemPAdrM, // to ahb - output logic MemReadM, MemWriteM, - output logic [1:0] AtomicMaskedM, - input logic MemAckW, // from ahb - input logic [`XLEN-1:0] HRDATAW, // from ahb - output logic [2:0] SizeFromLSU, - output logic StallWfromLSU, - + output logic [`PA_BITS-1:0] DCtoAHBPAdrM, // to ahb + output logic DCtoAHBReadM, + output logic DCtoAHBWriteM, + input logic DCfromAHBAck, // from ahb + input logic [`XLEN-1:0] DCfromAHBReadData, // from ahb + output logic [`XLEN-1:0] DCtoAHBWriteData, // to ahb // mmu management @@ -87,14 +87,9 @@ module lsu output logic DTLBHitM, // not connected - // PMA/PMP (inside mmu) signals - input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well. - input logic [2:0] HSIZE, HBURST, - input logic HWRITE, input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. - output logic DSquashBusAccessM // output logic [5:0] DHSELRegionsM ); @@ -119,6 +114,9 @@ module lsu logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. + + logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache + logic DTLBMissM; logic [`XLEN-1:0] PageTableEntryM; logic [1:0] PageTypeM; @@ -130,27 +128,21 @@ module lsu logic HPTWTranslate; logic HPTWRead; logic [1:0] MemRWMtoDCache; - logic [2:0] SizetoDCache; + logic [2:0] Funct3MtoDCache; logic [1:0] AtomicMtoDCache; logic [`XLEN-1:0] MemAdrMtoDCache; - logic [`XLEN-1:0] WriteDataMtoDCache; + logic [`XLEN-1:0] MemAdrEtoDCache; logic [`XLEN-1:0] ReadDataWfromDCache; logic StallWtoDCache; logic CommittedMfromDCache; logic SquashSCWfromDCache; logic DataMisalignedMfromDCache; logic HPTWReady; - logic LSUStall; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. + logic DCacheStall; - - // for time being until we have a dcache the AHB Lite read bus HRDATAW will be connected to the - // CPU's read data input ReadDataW. - assign ReadDataWfromDCache = HRDATAW; - - pagetablewalker pagetablewalker( .clk(clk), .reset(reset), @@ -192,32 +184,29 @@ module lsu .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), - .WriteDataM(WriteDataM), // *** Need to remove this. .StallW(StallW), .ReadDataW(ReadDataW), .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), - .DCacheStall(DCacheStall), - // LSU + .LSUStall(LSUStall), + // DCACHE .DisableTranslation(DisableTranslation), .MemRWMtoDCache(MemRWMtoDCache), - .SizetoDCache(SizetoDCache), + .Funct3MtoDCache(Funct3MtoDCache), .AtomicMtoDCache(AtomicMtoDCache), .MemAdrMtoDCache(MemAdrMtoDCache), - .WriteDataMtoDCache(WriteDataMtoDCache), // *** ?????????????? .StallWtoDCache(StallWtoDCache), .CommittedMfromDCache(CommittedMfromDCache), .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), - .DataStall(LSUStall)); - - + .DCacheStall(DCacheStall)); + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.VirtualAddress(MemAdrMtoDCache), - .Size(SizetoDCache[1:0]), + .Size(Funct3MtoDCache[1:0]), .PTE(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), @@ -227,10 +216,11 @@ module lsu .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), - .AtomicAccessM(AtomicMaskedM[1]), + //.AtomicAccessM(AtomicMaskedM[1]), + .AtomicAccessM(1'b0), .WriteAccessM(MemRWMtoDCache[0]), .ReadAccessM(MemRWMtoDCache[1]), - .SquashBusAccess(DSquashBusAccessM), + .SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), // .SelRegions(DHSELRegionsM), @@ -242,7 +232,7 @@ module lsu // Determine if an Unaligned access is taking place always_comb - case(SizetoDCache[1:0]) + case(Funct3MtoDCache[1:0]) 2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu 2'b01: DataMisalignedMfromDCache = MemAdrMtoDCache[0]; // lh, sh, lhu 2'b10: DataMisalignedMfromDCache = MemAdrMtoDCache[1] | MemAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu @@ -254,6 +244,10 @@ module lsu // Changed DataMisalignedMfromDCache to a larger combination of trap sources // NonBusTrapM is anything that the bus doesn't contribute to producing // By contrast, using TrapM results in circular logic errors +/* -----\/----- EXCLUDED -----\/----- + + // *** BUG for now leave this out. come back later after the d cache is working. July 09, 2021 + assign MemReadM = MemRWMtoDCache[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; assign MemWriteM = MemRWMtoDCache[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoDCache : 2'b00 ; @@ -292,16 +286,56 @@ module lsu assign SquashSCWfromDCache = 0; end endgenerate + -----/\----- EXCLUDED -----/\----- */ + + + // *** BUG + assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb. + + + dcache dcache(.clk(clk), + .reset(reset), + .StallM(StallM), + .StallW(StallW), + .FlushM(FlushM), + .FlushW(FlushW), + .MemRWM(MemRWMtoDCache), + .Funct3M(Funct3MtoDCache), + .Funct7M(Funct7M), + .AtomicM(AtomicMtoDCache), + .MemAdrE(MemAdrEtoDCache), // *** add to arb + .MemPAdrM(MemPAdrM), + .WriteDataM(WriteDataM), + .ReadDataW(ReadDataWfromDCache), + .DCacheStall(DCacheStall), + .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. + .DTLBMissM(DTLBMissM), + .UncachedM(1'b0), // ***connect to PMA + + // AHB connection + .AHBPAdr(DCtoAHBPAdrM), + .AHBRead(DCtoAHBReadM), + .AHBWrite(DCtoAHBWriteM), + .AHBAck(DCfromAHBAck), + .HWDATA(DCtoAHBWriteData), + .HRDATA(DCfromAHBReadData) + ); + +// assign AtomicMaskedM = 2'b00; // *** Remove from AHB + // Data stall //assign LSUStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2); - assign HPTWReady = (CurrState == STATE_READY); + // BUG *** July 09, 2021 + //assign HPTWReady = (CurrState == STATE_READY); // Ross Thompson April 22, 2021 // for now we need to handle the issue where the data memory interface repeately // requests data from memory rather than issuing a single request. +/* -----\/----- EXCLUDED -----\/----- + // *** BUG will need to modify this so we can handle the ptw. July 09, 2021 flopenl #(.TYPE(statetype)) stateReg(.clk(clk), .load(reset), @@ -331,7 +365,7 @@ module lsu end STATE_FETCH_AMO_1: begin LSUStall = 1'b1; - if (MemAckW) begin + if (DCfromAHBAck) begin NextState = STATE_FETCH_AMO_2; end else begin NextState = STATE_FETCH_AMO_1; @@ -339,9 +373,9 @@ module lsu end STATE_FETCH_AMO_2: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoDCache) begin + if (DCfromAHBAck & ~StallWtoDCache) begin NextState = STATE_FETCH_AMO_2; - end else if (MemAckW & StallWtoDCache) begin + end else if (DCfromAHBAck & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH_AMO_2; @@ -349,9 +383,9 @@ module lsu end STATE_FETCH: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoDCache) begin + if (DCfromAHBAck & ~StallWtoDCache) begin NextState = STATE_READY; - end else if (MemAckW & StallWtoDCache) begin + end else if (DCfromAHBAck & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH; @@ -378,9 +412,9 @@ module lsu end STATE_PTW_FETCH : begin LSUStall = 1'b1; - if (MemAckW & ~DTLBWriteM) begin + if (DCfromAHBAck & ~DTLBWriteM) begin NextState = STATE_PTW_READY; - end else if (MemAckW & DTLBWriteM) begin + end else if (DCfromAHBAck & DTLBWriteM) begin NextState = STATE_READY; end else begin NextState = STATE_PTW_FETCH; @@ -395,11 +429,8 @@ module lsu end endcase end // always_comb + -----/\----- EXCLUDED -----/\----- */ - // *** for now just pass through size - assign SizeFromLSU = SizetoDCache; - assign StallWfromLSU = StallWtoDCache; - endmodule diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 0c7730f1..83ab93be 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -42,29 +42,27 @@ module lsuArb input logic [2:0] Funct3M, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrM, - input logic [`XLEN-1:0] WriteDataM, input logic StallW, // to CPU output logic [`XLEN-1:0] ReadDataW, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, - output logic DCacheStall, + output logic LSUStall, // to LSU output logic DisableTranslation, output logic [1:0] MemRWMtoDCache, - output logic [2:0] SizetoDCache, + output logic [2:0] Funct3MtoDCache, output logic [1:0] AtomicMtoDCache, output logic [`XLEN-1:0] MemAdrMtoDCache, - output logic [`XLEN-1:0] WriteDataMtoDCache, output logic StallWtoDCache, // from LSU input logic CommittedMfromDCache, input logic SquashSCWfromDCache, input logic DataMisalignedMfromDCache, input logic [`XLEN-1:0] ReadDataWfromDCache, - input logic DataStall + input logic DCacheStall ); @@ -141,11 +139,10 @@ module lsuArb generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw endgenerate - mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, SizetoDCache); + mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache); assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; - assign WriteDataMtoDCache = SelPTW ? `XLEN'b0 : WriteDataM; assign StallWtoDCache = SelPTW ? 1'b0 : StallW; // demux the inputs from LSU to walker or cpu's data port. @@ -158,7 +155,7 @@ module lsuArb // *** need to rename DcacheStall and Datastall. // not clear at all. I think it should be LSUStall from the LSU, // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one). - assign HPTWStall = SelPTW ? DataStall : 1'b1; + assign HPTWStall = SelPTW ? DCacheStall : 1'b1; //assign HPTWStallD = SelPTW ? DataStall : 1'b1; /* -----\/----- EXCLUDED -----\/----- assign HPTWStallD = SelPTW ? DataStall : 1'b1; @@ -168,6 +165,6 @@ module lsuArb .q(HPTWStall)); -----/\----- EXCLUDED -----/\----- */ - assign DCacheStall = SelPTW ? 1'b1 : DataStall; // *** this is probably going to change. + assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change. endmodule diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 3b589456..80a0b32a 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -128,45 +128,36 @@ module wallypipelinedhart - // bus interface to dmem - logic MemReadM, MemWriteM; - logic [1:0] AtomicMaskedM; + // cpu lsu interface logic [2:0] Funct3M; - logic [`XLEN-1:0] MemAdrM, WriteDataM; - logic [`PA_BITS-1:0] MemPAdrM; + logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM; logic [`XLEN-1:0] ReadDataW; + logic CommittedM; + + // AHB ifu interface logic [`PA_BITS-1:0] InstrPAdrF; logic [`XLEN-1:0] InstrRData; logic InstrReadF; - logic InstrAckF, MemAckW; - logic CommitM, CommittedM; - + logic InstrAckF; + + // AHB LSU interface + logic [`PA_BITS-1:0] DCtoAHBPAdrM; + logic DCtoAHBReadM; + logic DCtoAHBWriteM; + logic DCfromAHBAck; + logic [`XLEN-1:0] DCfromAHBReadData; + logic [`XLEN-1:0] DCtoAHBWriteData; + + logic CommitM; + logic BPPredWrongE; logic BPPredDirWrongM; logic BTBPredPCWrongM; logic RASPredPCWrongM; logic BPPredClassNonCFIWrongM; - - logic [`XLEN-1:0] WriteDatatmpM; - logic [4:0] InstrClassM; - - logic [`XLEN-1:0] HRDATAW; - - // IEU vs HPTW arbitration signals to send to LSU - logic [1:0] MemRWMtoLSU; - logic [2:0] SizeToLSU; - logic [1:0] AtomicMtoLSU; - logic [`XLEN-1:0] MemAdrMtoLSU; - logic [`XLEN-1:0] WriteDataMtoLSU; - logic [`XLEN-1:0] ReadDataWFromLSU; - logic CommittedMfromLSU; - logic SquashSCWfromLSU; - logic DataMisalignedMfromLSU; - logic StallWtoLSU; - logic StallWfromLSU; - logic [2:0] SizeFromLSU; logic InstrAccessFaultF; + logic [2:0] DCtoAHBSizeM; @@ -176,43 +167,33 @@ module wallypipelinedhart ieu ieu(.*); // integer execution unit: integer register file, datapath and controller - - // mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM); - - lsu lsu(.clk(clk), .reset(reset), .StallM(StallM), .FlushM(FlushM), .StallW(StallW), .FlushW(FlushW), - // connected to arbiter (reconnect to CPU) + // CPU interface .MemRWM(MemRWM), - .Funct3M(Funct3M), + .Funct3M(Funct3M), + .Funct7M(InstrM[31:25]), .AtomicM(AtomicM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), + .MemAdrE(MemAdrE), .MemAdrM(MemAdrM), .WriteDataM(WriteDataM), .ReadDataW(ReadDataW), // connected to ahb (all stay the same) .CommitM(CommitM), - .MemPAdrM(MemPAdrM), - .MemReadM(MemReadM), - .MemWriteM(MemWriteM), - .AtomicMaskedM(AtomicMaskedM), - .MemAckW(MemAckW), - .HRDATAW(HRDATAW), - .SizeFromLSU(SizeFromLSU), // stays the same - .StallWfromLSU(StallWfromLSU), // stays the same - .DSquashBusAccessM(DSquashBusAccessM), // probalby removed after dcache implemenation? - // currently not connected (but will need to be used for lsu talking to ahb. - .HADDR(HADDR), - .HSIZE(HSIZE), - .HBURST(HBURST), - .HWRITE(HWRITE), + .DCtoAHBPAdrM(DCtoAHBPAdrM), + .DCtoAHBReadM(DCtoAHBReadM), + .DCtoAHBWriteM(DCtoAHBWriteM), + .DCfromAHBAck(DCfromAHBAck), + .DCfromAHBReadData(DCfromAHBReadData), + .DCtoAHBWriteData(DCtoAHBWriteData), // connect to csr or privilege and stay the same. .PrivilegeModeW(PrivilegeModeW), // connects to csr @@ -234,7 +215,6 @@ module wallypipelinedhart .StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege .StoreAccessFaultM(StoreAccessFaultM), // connects to privilege - // connected to hptw. Move to internal. .PCF(PCF), .ITLBMissF(ITLBMissF), .PageTableEntryF(PageTableEntryF), @@ -246,19 +226,34 @@ module wallypipelinedhart .DTLBHitM(DTLBHitM), // not connected remove - .DCacheStall(DCacheStall)) // change to DCacheStall - ; + .LSUStall(DCacheStall)); // change to DCacheStall - ahblite ebu( - //.InstrReadF(1'b0), - //.InstrRData(InstrF), // hook up InstrF later - .ISquashBusAccessF(1'b0), // *** temporary hack to disable PMP instruction fetch checking - .WriteDataM(WriteDataM), - .MemSizeM(SizeFromLSU[1:0]), .UnsignedLoadM(SizeFromLSU[2]), - .Funct7M(InstrM[31:25]), - .HRDATAW(HRDATAW), - .StallW(StallWfromLSU), + generate + if (`XLEN == 32) assign DCtoAHBSizeM = 3'b010; + else assign DCtoAHBSizeM = 3'b011; + endgenerate; + + + ahblite ebu(// IFU connections + .InstrPAdrF(InstrPAdrF), + .InstrReadF(InstrReadF), + .InstrRData(InstrRData), + .InstrAckF(InstrAckF), + // LSU connections + .DCtoAHBPAdrM(DCtoAHBPAdrM), // rename to DCtoAHBPAdrM + .DCtoAHBReadM(DCtoAHBReadM), // rename to DCtoAHBReadM + .DCtoAHBWriteM(DCtoAHBWriteM), // rename to DCtoAHBWriteM + .DCtoAHBWriteData(DCtoAHBWriteData), + .DCfromAHBReadData(DCfromAHBReadData), + .DCfromAHBAck(DCfromAHBAck), + // remove these + .MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed + .UnsignedLoadM(1'b0), + .Funct7M(7'b0), + .HRDATAW(), + .StallW(1'b0), + .AtomicMaskedM(2'b00), .*); From 4c0cee1c1907cb8a38a02a97ac8db97a7c91358f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 9 Jul 2021 15:37:16 -0500 Subject: [PATCH 006/112] Design loads in modelsim, but trap is an X. --- wally-pipelined/src/cache/DCacheMem.sv | 2 +- wally-pipelined/src/cache/dcache.sv | 17 +++++++---------- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index 70668b5d..326e1be2 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -89,6 +89,6 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 end -endmodule; // DCacheMemWay +endmodule // DCacheMemWay diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 65a0fe8b..3378ec56 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -88,7 +88,7 @@ module dcache logic [NUMWAYS-1:0] Valid, Dirty, WayHit; logic CacheHit; logic [NUMREPL_BITS-1:0] ReplacementBits [NUMLINES-1:0]; - logic [NUMREPL_BITS-1:0] NewReplacement [NUMLINES-1:0]; + logic [NUMREPL_BITS-1:0] NewReplacement; logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; @@ -184,11 +184,7 @@ module dcache end // *** TODO add replacement policy - genvar index; - generate - for(index = 0; index < NUMLINES-1; index++) - assign NewReplacement[index] = '0; - endgenerate + assign NewReplacement = '0; assign VictimWay = 4'b0001; mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0), .d1(SRAMBlockWriteEnableM ? VictimWay : '0), @@ -201,12 +197,13 @@ module dcache // ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. + genvar index; always_comb begin ReadDataBlockM = '0; VictimReadDataBlockM = '0; for(int index = 0; index < NUMWAYS; index++) begin - ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM; - VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM; + ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM[index]; + VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM[index]; end end assign VictimDirty = | VictimDirtyWay; @@ -363,7 +360,7 @@ module dcache SRAMWritePipeReg(.clk(clk), .reset(reset), .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}), - .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDirtyM, ClearDirtyM, AtomicW})); + .q({SRAMWordWriteEnableW, SetValidW, ClearValidW, SetDirtyW, ClearDirtyW, AtomicW})); // fsm state regs @@ -491,4 +488,4 @@ module dcache assign CntEn = PreCntEn & AHBAck; -endmodule; // dcache +endmodule // dcache From b1ceeb40df03052e66b09be756306a6c64b94339 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 9 Jul 2021 17:14:54 -0500 Subject: [PATCH 007/112] Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a full cache block or a word write from the CPU. --- wally-pipelined/src/cache/dcache.sv | 66 ++++++++++++++++++++++++++--- wally-pipelined/src/lsu/lsu.sv | 6 +-- 2 files changed, 62 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3378ec56..237057fc 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -69,14 +69,12 @@ module dcache localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; localparam integer LOGWPL = $clog2(WORDSPERLINE); - + localparam integer LOGXLENBYTES = $clog2(`XLEN/8); logic SelAdrM; logic [`PA_BITS-1:0] MemPAdrW; logic [INDEXLEN-1:0] SRAMAdr; - logic [NUMWAYS-1:0] WriteEnable; - logic [NUMWAYS-1:0] WriteWordEnable; logic [BLOCKLEN-1:0] SRAMWriteData; logic [BLOCKLEN-1:0] DCacheMemWriteData; logic SetValidM, ClearValidM, SetValidW, ClearValidW; @@ -95,7 +93,7 @@ module dcache logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; logic [BLOCKLEN-1:0] FinalWriteDataWordsW; logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [WORDSPERLINE-1:0] SRAMWordEnable [NUMWAYS-1:0]; + logic [WORDSPERLINE-1:0] SRAMWordEnable; logic SelMemWriteDataM, SelMemWriteDataW; logic [2:0] Funct3W; @@ -114,6 +112,7 @@ module dcache logic SelAMOWrite; logic [6:0] Funct7W; logic [INDEXLEN-1:0] AdrMuxOut; + logic [2**LOGWPL-1:0] MemPAdrDecodedW; @@ -144,6 +143,13 @@ module dcache .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SRAMWordWriteEnableW), .y(SRAMAdr)); + + oneHotDecoder #(LOGWPL) + oneHotDecoder(.bin(MemPAdrW[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), + .decoded(MemPAdrDecodedW)); + + + assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; genvar way; @@ -153,9 +159,9 @@ module dcache MemWay(.clk(clk), .reset(reset), .Adr(SRAMAdr), - .WAdr(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .WAdr(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .WriteEnable(SRAMWayWriteEnable[way]), - .WriteWordEnable(SRAMWordEnable[way]), + .WriteWordEnable(SRAMWordEnable), .WriteData(SRAMWriteData), .WriteTag(MemPAdrW[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .SetValid(SetValidW), @@ -424,6 +430,12 @@ module dcache CntReset = 1'b1; DCacheStall = 1'b1; end + // write miss valid cached + else if(MemRWM[0] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_WRITE_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end // fault else if(|MemRWM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; @@ -468,10 +480,45 @@ module dcache STATE_READ_MISS_READ_WORD: begin DCacheStall = 1'b1; - SelAdrM = 1'b1; + SelAdrM = 1'b0; NextState = STATE_READY; end + STATE_WRITE_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + AHBRead = 1'b1; + if (FetchCountFlag & AHBAck) begin + NextState = STATE_WRITE_MISS_FETCH_DONE; + end else begin + NextState = STATE_WRITE_MISS_FETCH_WDV; + end + end + + STATE_WRITE_MISS_FETCH_DONE: begin + DCacheStall = 1'b1; + if(VictimDirty) begin + NextState = STATE_WRITE_MISS_CHECK_EVICTED_DIRTY; + end else begin + NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + end + end + + STATE_WRITE_MISS_WRITE_CACHE_BLOCK: begin + SRAMBlockWriteEnableM = 1'b1; + DCacheStall = 1'b1; + NextState = STATE_WRITE_MISS_WRITE_WORD; + SelAdrM = 1'b1; + SetValidM = 1'b1; + end + + STATE_WRITE_MISS_WRITE_WORD: begin + SRAMWordWriteEnableM = 1'b1; + DCacheStall = 1'b0; + NextState = STATE_READY; + SetDirtyM = 1'b1; + end + STATE_PTW_MISS_FETCH_WDV: begin DCacheStall = 1'b1; SelAdrM = 1'b1; @@ -481,6 +528,11 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end end + + STATE_SRAM_BUSY: begin + DCacheStall = 1'b0; + NextState = STATE_READY; + end default: begin end endcase diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 1afd92ad..432645f7 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -258,9 +258,6 @@ module lsu flopr #(1) committedMreg(clk,reset,(CommittedMfromDCache | CommitM) & StallM,preCommittedM); assign CommittedMfromDCache = preCommittedM | CommitM; - // Determine if address is valid - assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; - assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; // Handle atomic load reserved / store conditional generate @@ -288,6 +285,9 @@ module lsu endgenerate -----/\----- EXCLUDED -----/\----- */ + // Determine if address is valid + assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; + assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; // *** BUG assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb. From d65c01bc292424c1ce5225fc5b1308bab3ab0ed8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 10:56:25 -0500 Subject: [PATCH 008/112] Write Hits and Write Misses without eviction are working correctly! The next step is to add eviction of dirty lines. --- wally-pipelined/src/cache/DCacheMem.sv | 3 +- wally-pipelined/src/cache/dcache.sv | 122 +++++++++++++++---------- 2 files changed, 74 insertions(+), 51 deletions(-) diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index 326e1be2..ba50f5dd 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -33,6 +33,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 input logic [$clog2(NUMLINES)-1:0] WAdr, // write address for valid and dirty only input logic WriteEnable, input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, + input logic TagWriteEnable, input logic [BLOCKLEN-1:0] WriteData, input logic [TAGLEN-1:0] WriteTag, input logic SetValid, @@ -69,7 +70,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 .Addr(Adr), .ReadData(ReadTag), .WriteData(WriteTag), - .WriteEnable(WriteEnable)); + .WriteEnable(TagWriteEnable)); always_ff @(posedge clk, posedge reset) begin diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 237057fc..b87a378d 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -59,7 +59,7 @@ module dcache ); localparam integer BLOCKLEN = 256; - localparam integer NUMLINES = 512; + localparam integer NUMLINES = 64; localparam integer NUMWAYS = 4; localparam integer NUMREPL_BITS = 3; @@ -127,7 +127,7 @@ module dcache // data path flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), - .en(~StallW), + .en(1'b1), .d(MemPAdrM), .q(MemPAdrW)); @@ -137,15 +137,18 @@ module dcache .s(SelAdrM), .y(AdrMuxOut)); - + assign SRAMAdr = AdrMuxOut; +/* -----\/----- EXCLUDED -----\/----- + mux2 #(INDEXLEN) SelAdrlMux2(.d0(AdrMuxOut), .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SRAMWordWriteEnableW), .y(SRAMAdr)); + -----/\----- EXCLUDED -----/\----- */ oneHotDecoder #(LOGWPL) - oneHotDecoder(.bin(MemPAdrW[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), + oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedW)); @@ -154,7 +157,7 @@ module dcache genvar way; generate - for(way = 0; way < NUMWAYS; way = way + 1) begin + for(way = 0; way < NUMWAYS; way = way + 1) begin :CacheWays DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN)) MemWay(.clk(clk), .reset(reset), @@ -162,12 +165,13 @@ module dcache .WAdr(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .WriteEnable(SRAMWayWriteEnable[way]), .WriteWordEnable(SRAMWordEnable), + .TagWriteEnable(SRAMBlockWriteEnableM), .WriteData(SRAMWriteData), - .WriteTag(MemPAdrW[`PA_BITS-1:OFFSETLEN+INDEXLEN]), - .SetValid(SetValidW), - .ClearValid(ClearValidW), - .SetDirty(SetDirtyW), - .ClearDirty(ClearDirtyW), + .WriteTag(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]), + .SetValid(SetValidM), + .ClearValid(ClearValidM), + .SetDirty(SetDirtyM), + .ClearDirty(ClearDirtyM), .ReadData(ReadDataBlockWayM[way]), .ReadTag(ReadTag[way]), .Valid(Valid[way]), @@ -186,13 +190,13 @@ module dcache for(int index = 0; index < NUMLINES-1; index++) ReplacementBits[index] <= '0; end - else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement; + else if (SRAMWriteEnable) ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement; end // *** TODO add replacement policy assign NewReplacement = '0; assign VictimWay = 4'b0001; - mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0), + mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0), .d1(SRAMBlockWriteEnableM ? VictimWay : '0), .s(SRAMBlockWriteEnableM), .y(SRAMWayWriteEnable)); @@ -308,39 +312,41 @@ module dcache logic CntReset; - typedef enum {STATE_READY, - STATE_READ_MISS_FETCH_WDV, - STATE_READ_MISS_FETCH_DONE, - STATE_READ_MISS_CHECK_EVICTED_DIRTY, - STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_READ_MISS_WRITE_CACHE_BLOCK, - STATE_READ_MISS_READ_WORD, - STATE_WRITE_MISS_FETCH_WDV, - STATE_WRITE_MISS_FETCH_DONE, - STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, - STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_WRITE_MISS_WRITE_CACHE_BLOCK, - STATE_WRITE_MISS_WRITE_WORD, - STATE_AMO_MISS_FETCH_WDV, - STATE_AMO_MISS_FETCH_DONE, - STATE_AMO_MISS_CHECK_EVICTED_DIRTY, - STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_AMO_MISS_WRITE_CACHE_BLOCK, - STATE_AMO_MISS_READ_WORD, - STATE_AMO_MISS_UPDATE_WORD, - STATE_AMO_MISS_WRITE_WORD, - STATE_AMO_UPDATE, - STATE_AMO_WRITE, - STATE_SRAM_BUSY, - STATE_PTW_READY, - STATE_PTW_MISS_FETCH_WDV, - STATE_PTW_MISS_FETCH_DONE, - STATE_PTW_MISS_CHECK_EVICTED_DIRTY, - STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_PTW_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_MISS_READ_SRAM, - STATE_UNCACHED_WDV, - STATE_UNCACHED_DONE} statetype; + typedef enum {STATE_READY, + STATE_READ_MISS_FETCH_WDV, + STATE_READ_MISS_FETCH_DONE, + STATE_READ_MISS_CHECK_EVICTED_DIRTY, + STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_READ_MISS_WRITE_CACHE_BLOCK, + STATE_READ_MISS_READ_WORD, + STATE_WRITE_MISS_FETCH_WDV, + STATE_WRITE_MISS_FETCH_DONE, + STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, + STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_WRITE_MISS_WRITE_CACHE_BLOCK, + STATE_WRITE_MISS_READ_WORD, + STATE_WRITE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_CHECK_EVICTED_DIRTY, + STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_AMO_MISS_WRITE_CACHE_BLOCK, + STATE_AMO_MISS_READ_WORD, + STATE_AMO_MISS_UPDATE_WORD, + STATE_AMO_MISS_WRITE_WORD, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_SRAM_BUSY, + STATE_PTW_READY, + STATE_PTW_MISS_FETCH_WDV, + STATE_PTW_MISS_FETCH_DONE, + STATE_PTW_MISS_CHECK_EVICTED_DIRTY, + STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_PTW_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_MISS_READ_SRAM, + STATE_UNCACHED_WDV, + STATE_UNCACHED_DONE, + STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -360,7 +366,7 @@ module dcache assign NextFetchCount = FetchCount + 1'b1; - assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableW; + assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; flopr #(1+4+2) SRAMWritePipeReg(.clk(clk), @@ -419,10 +425,12 @@ module dcache end // write hit valid cached else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin - NextState = STATE_READY; + SelAdrM = 1'b1; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end // read miss valid cached else if(MemRWM[1] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin @@ -488,6 +496,7 @@ module dcache DCacheStall = 1'b1; PreCntEn = 1'b1; AHBRead = 1'b1; + SelAdrM = 1'b1; if (FetchCountFlag & AHBAck) begin NextState = STATE_WRITE_MISS_FETCH_DONE; end else begin @@ -497,6 +506,7 @@ module dcache STATE_WRITE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; + SelAdrM = 1'b1; if(VictimDirty) begin NextState = STATE_WRITE_MISS_CHECK_EVICTED_DIRTY; end else begin @@ -507,16 +517,23 @@ module dcache STATE_WRITE_MISS_WRITE_CACHE_BLOCK: begin SRAMBlockWriteEnableM = 1'b1; DCacheStall = 1'b1; - NextState = STATE_WRITE_MISS_WRITE_WORD; + NextState = STATE_WRITE_MISS_READ_WORD; SelAdrM = 1'b1; SetValidM = 1'b1; end + STATE_WRITE_MISS_READ_WORD: begin + NextState = STATE_WRITE_MISS_WRITE_WORD; + DCacheStall = 1'b1; + SelAdrM = 1'b1; + end + STATE_WRITE_MISS_WRITE_WORD: begin - SRAMWordWriteEnableM = 1'b1; DCacheStall = 1'b0; - NextState = STATE_READY; + SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; + NextState = STATE_READY; + SelAdrM = 1'b1; end STATE_PTW_MISS_FETCH_WDV: begin @@ -533,6 +550,11 @@ module dcache DCacheStall = 1'b0; NextState = STATE_READY; end + + STATE_CPU_BUSY : begin + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + end default: begin end endcase From efe37ea079952dbc7b6aecd6acbae09b5dcd3637 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 15:17:40 -0500 Subject: [PATCH 009/112] Write miss with eviction works. --- wally-pipelined/src/cache/dcache.sv | 45 ++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index b87a378d..c3c6079c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -89,6 +89,7 @@ module dcache logic [NUMREPL_BITS-1:0] NewReplacement; logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; logic [BLOCKLEN-1:0] FinalWriteDataWordsW; @@ -113,8 +114,11 @@ module dcache logic [6:0] Funct7W; logic [INDEXLEN-1:0] AdrMuxOut; logic [2**LOGWPL-1:0] MemPAdrDecodedW; - - + + logic [`PA_BITS-1:0] BasePAdrM; + logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; + logic [TAGLEN-1:0] VictimTag; + flopenr #(7) Funct7WReg(.clk(clk), .reset(reset), @@ -180,8 +184,11 @@ module dcache assign ReadDataBlockWayMaskedM[way] = Valid[way] ? ReadDataBlockWayM[way] : '0; // first part of AO mux. // the cache block candiate for eviction + // *** this should be sharable with the read data muxing, but for now i'm doing the simple + // thing and makign them separate. assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0; assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; + assign VictimTagWay[way] = Valid[way] ? ReadTag[way] : '0; end endgenerate @@ -211,24 +218,30 @@ module dcache always_comb begin ReadDataBlockM = '0; VictimReadDataBlockM = '0; + VictimTag = '0; for(int index = 0; index < NUMWAYS; index++) begin ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM[index]; VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM[index]; + VictimTag = VictimTag | VictimTagWay[index]; end end assign VictimDirty = | VictimDirtyWay; - + // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can // easily build a variable input mux. generate for (index = 0; index < WORDSPERLINE; index++) begin assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)]; + assign VictimReadDataBlockSetsM[index] = VictimReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)]; end endgenerate // variable input mux assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; + + assign HWDATA = VictimReadDataBlockSetsM[FetchCount]; + // finally swr // *** BUG fix HSIZED? why was it this way? subwordread subwordread(.HRDATA(ReadDataWordM), @@ -281,11 +294,17 @@ module dcache // *** Coding style. this is just awful. The purpose is to align FetchCount to the // size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length. + + mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), + .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + .s(AHBWrite), + .y(BasePAdrM)); + generate if (`XLEN == 32) begin - assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + MemPAdrM; + assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrM; end else begin - assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + MemPAdrM; + assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrM; end endgenerate @@ -321,7 +340,7 @@ module dcache STATE_READ_MISS_READ_WORD, STATE_WRITE_MISS_FETCH_WDV, STATE_WRITE_MISS_FETCH_DONE, - STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, + STATE_WRITE_MISS_EVICT_DIRTY, STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, STATE_WRITE_MISS_WRITE_CACHE_BLOCK, STATE_WRITE_MISS_READ_WORD, @@ -507,8 +526,9 @@ module dcache STATE_WRITE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 1'b1; + CntReset = 1'b1; if(VictimDirty) begin - NextState = STATE_WRITE_MISS_CHECK_EVICTED_DIRTY; + NextState = STATE_WRITE_MISS_EVICT_DIRTY; end else begin NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; end @@ -536,6 +556,17 @@ module dcache SelAdrM = 1'b1; end + STATE_WRITE_MISS_EVICT_DIRTY: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + AHBWrite = 1'b1; + if( FetchCountFlag & AHBAck) begin + NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + end else begin + NextState = STATE_WRITE_MISS_EVICT_DIRTY; + end + end + STATE_PTW_MISS_FETCH_WDV: begin DCacheStall = 1'b1; SelAdrM = 1'b1; From 60ed023734b8987af7f2a2f42fd94cc2535ede50 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 17:48:47 -0500 Subject: [PATCH 010/112] Actually writes the correct data now on stores. --- wally-pipelined/regression/wave.do | 220 +++++++++++++++++----------- wally-pipelined/src/cache/dcache.sv | 64 +++----- 2 files changed, 152 insertions(+), 132 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 946e2d28..501f71e4 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -20,14 +20,14 @@ add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPa add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -105,7 +105,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 @@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -213,13 +213,8 @@ add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState -add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState -add wave -noupdate -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM -add wave -noupdate -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK @@ -240,19 +235,77 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HRDATAW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/StallW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetValidW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetDirtyW +add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemPAdrM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/ReadDataW +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/WriteDataM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/StallW +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/LSUStall add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -280,45 +333,40 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUTranslate -add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/MMUReadPTE -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group ptwalker -divider data -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr -add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE -add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/lsu/arbiter/MemAdrMtoLSU +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM +add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group ptwalker -divider data +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -expand -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -343,17 +391,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/PCF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {16658 ns} 1} {{Cursor 4} {16655 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 4} {2797 ns} 0} {{Cursor 6} {3275 ns} 0} {{Cursor 8} {3905 ns} 0} {{Cursor 9} {4358 ns} 0} {{Cursor 10} {5007 ns} 0} {{Cursor 11} {57795 ns} 0} +quietly wave cursor active 6 configure wave -namecolwidth 250 -configure wave -valuecolwidth 189 +configure wave -valuecolwidth 273 configure wave -justifyvalue left configure wave -signalnamewidth 1 configure wave -snapdistance 10 @@ -366,4 +412,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {16565 ns} {16719 ns} +WaveRestoreZoom {57593 ns} {57969 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index c3c6079c..41138d15 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -73,12 +73,11 @@ module dcache logic SelAdrM; - logic [`PA_BITS-1:0] MemPAdrW; logic [INDEXLEN-1:0] SRAMAdr; logic [BLOCKLEN-1:0] SRAMWriteData; logic [BLOCKLEN-1:0] DCacheMemWriteData; - logic SetValidM, ClearValidM, SetValidW, ClearValidW; - logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; + logic SetValidM, ClearValidM; + logic SetDirtyM, ClearDirtyM; logic [BLOCKLEN-1:0] ReadDataBlockWayM [NUMWAYS-1:0]; logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; logic [BLOCKLEN-1:0] VictimReadDataBLockWayMaskedM [NUMWAYS-1:0]; @@ -91,11 +90,11 @@ module dcache logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; - logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; - logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; + logic [BLOCKLEN-1:0] FinalWriteDataWordsM; logic [LOGWPL:0] FetchCount, NextFetchCount; logic [WORDSPERLINE-1:0] SRAMWordEnable; - logic SelMemWriteDataM, SelMemWriteDataW; + logic SelMemWriteDataM; logic [2:0] Funct3W; logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; @@ -112,7 +111,6 @@ module dcache logic VictimDirty; logic SelAMOWrite; logic [6:0] Funct7W; - logic [INDEXLEN-1:0] AdrMuxOut; logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [`PA_BITS-1:0] BasePAdrM; @@ -130,26 +128,12 @@ module dcache // data path - flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), - .en(1'b1), - .d(MemPAdrM), - .q(MemPAdrW)); - mux2 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SelAdrM), - .y(AdrMuxOut)); + .y(SRAMAdr)); - assign SRAMAdr = AdrMuxOut; -/* -----\/----- EXCLUDED -----\/----- - - mux2 #(INDEXLEN) - SelAdrlMux2(.d0(AdrMuxOut), - .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .s(SRAMWordWriteEnableW), - .y(SRAMAdr)); - -----/\----- EXCLUDED -----/\----- */ oneHotDecoder #(LOGWPL) oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), @@ -185,7 +169,7 @@ module dcache // the cache block candiate for eviction // *** this should be sharable with the read data muxing, but for now i'm doing the simple - // thing and makign them separate. + // thing and making them separate. assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0; assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; assign VictimTagWay[way] = Valid[way] ? ReadTag[way] : '0; @@ -255,30 +239,20 @@ module dcache .q(ReadDataW)); // write path - flopen #(`XLEN) WriteDataWReg(.clk(clk), - .en(~StallW), - .d(WriteDataM), - .q(WriteDataW)); - - flopr #(3) Funct3WReg(.clk(clk), - .reset(reset), - .d(Funct3M), - .q(Funct3W)); - - subwordwrite subwordwrite(.HRDATA(ReadDataW), + subwordwrite subwordwrite(.HRDATA(FinalReadDataWordM), .HADDRD(MemPAdrM[2:0]), - .HSIZED({Funct3W[2], 1'b0, Funct3W[1:0]}), - .HWDATAIN(WriteDataW), - .HWDATA(FinalWriteDataW)); + .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), + .HWDATAIN(WriteDataM), + .HWDATA(FinalWriteDataM)); generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W[1:0]), + amoalu amoalu(.srca(FinalReadDataWordM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]), .result(AMOResult)); - mux2 #(`XLEN) wdmux(FinalWriteDataW, AMOResult, SelAMOWrite & AtomicW[1], FinalAMOWriteDataW); + mux2 #(`XLEN) wdmux(FinalWriteDataM, AMOResult, SelAMOWrite & AtomicM[1], FinalAMOWriteDataM); end else - assign FinalAMOWriteDataW = FinalWriteDataW; + assign FinalAMOWriteDataM = FinalWriteDataM; endgenerate @@ -312,11 +286,11 @@ module dcache // mux between the CPU's write and the cache fetch. generate for(index = 0; index < WORDSPERLINE; index++) begin - assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataW; + assign FinalWriteDataWordsM[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataM; end endgenerate - mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsW), + mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsM), .d1(DCacheMemWriteData), .s(SRAMBlockWriteEnableM), .y(SRAMWriteData)); @@ -387,11 +361,11 @@ module dcache assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; - flopr #(1+4+2) + flopr #(1) SRAMWritePipeReg(.clk(clk), .reset(reset), - .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}), - .q({SRAMWordWriteEnableW, SetValidW, ClearValidW, SetDirtyW, ClearDirtyW, AtomicW})); + .d({SRAMWordWriteEnableM}), + .q({SRAMWordWriteEnableW})); // fsm state regs From fed7042fd962edc0091b090e29ff7182e736603b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 22:15:44 -0500 Subject: [PATCH 011/112] Loads are working. There is a bug when the icache stalls 1 cycle before the d cache. --- wally-pipelined/src/cache/dcache.sv | 101 ++++++++++------------------ 1 file changed, 37 insertions(+), 64 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 41138d15..9b236596 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -312,13 +312,14 @@ module dcache STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, STATE_READ_MISS_WRITE_CACHE_BLOCK, STATE_READ_MISS_READ_WORD, - STATE_WRITE_MISS_FETCH_WDV, - STATE_WRITE_MISS_FETCH_DONE, - STATE_WRITE_MISS_EVICT_DIRTY, - STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_WRITE_MISS_WRITE_CACHE_BLOCK, - STATE_WRITE_MISS_READ_WORD, - STATE_WRITE_MISS_WRITE_WORD, + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_EVICT_DIRTY, + STATE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_MISS_WRITE_CACHE_BLOCK, + STATE_MISS_READ_WORD, + STATE_MISS_READ_WORD_DELAY, + STATE_MISS_WRITE_WORD, STATE_AMO_MISS_FETCH_WDV, STATE_AMO_MISS_FETCH_DONE, STATE_AMO_MISS_CHECK_EVICTED_DIRTY, @@ -425,15 +426,9 @@ module dcache if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end - // read miss valid cached - else if(MemRWM[1] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_READ_MISS_FETCH_WDV; - CntReset = 1'b1; - DCacheStall = 1'b1; - end - // write miss valid cached - else if(MemRWM[0] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_WRITE_MISS_FETCH_WDV; + // read or write miss valid cached + else if((|MemRWM) & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; end @@ -452,77 +447,55 @@ module dcache SelAMOWrite = 1'b1; end - STATE_READ_MISS_FETCH_WDV: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBRead = 1'b1; - if (FetchCountFlag & AHBAck) begin - NextState = STATE_READ_MISS_FETCH_DONE; - end else begin - NextState = STATE_READ_MISS_FETCH_WDV; - end - end - - STATE_READ_MISS_FETCH_DONE: begin - DCacheStall = 1'b1; - if(VictimDirty) begin - NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; - end else begin - NextState = STATE_READ_MISS_WRITE_CACHE_BLOCK; - end - end - - STATE_READ_MISS_WRITE_CACHE_BLOCK: begin - SRAMBlockWriteEnableM = 1'b1; - DCacheStall = 1'b1; - NextState = STATE_READ_MISS_READ_WORD; - SelAdrM = 1'b1; - end - - STATE_READ_MISS_READ_WORD: begin - DCacheStall = 1'b1; - SelAdrM = 1'b0; - NextState = STATE_READY; - end - - STATE_WRITE_MISS_FETCH_WDV: begin + STATE_MISS_FETCH_WDV: begin DCacheStall = 1'b1; PreCntEn = 1'b1; AHBRead = 1'b1; SelAdrM = 1'b1; if (FetchCountFlag & AHBAck) begin - NextState = STATE_WRITE_MISS_FETCH_DONE; + NextState = STATE_MISS_FETCH_DONE; end else begin - NextState = STATE_WRITE_MISS_FETCH_WDV; + NextState = STATE_MISS_FETCH_WDV; end end - STATE_WRITE_MISS_FETCH_DONE: begin + STATE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 1'b1; CntReset = 1'b1; if(VictimDirty) begin - NextState = STATE_WRITE_MISS_EVICT_DIRTY; + NextState = STATE_MISS_EVICT_DIRTY; end else begin - NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + NextState = STATE_MISS_WRITE_CACHE_BLOCK; end end - STATE_WRITE_MISS_WRITE_CACHE_BLOCK: begin + STATE_MISS_WRITE_CACHE_BLOCK: begin SRAMBlockWriteEnableM = 1'b1; DCacheStall = 1'b1; - NextState = STATE_WRITE_MISS_READ_WORD; + NextState = STATE_MISS_READ_WORD; SelAdrM = 1'b1; SetValidM = 1'b1; end - STATE_WRITE_MISS_READ_WORD: begin - NextState = STATE_WRITE_MISS_WRITE_WORD; - DCacheStall = 1'b1; + STATE_MISS_READ_WORD: begin SelAdrM = 1'b1; + DCacheStall = 1'b1; + if (MemRWM[1]) begin + NextState = STATE_MISS_READ_WORD_DELAY; + // delay state is required as the read signal MemRWM[1] is still high when we + // return to the ready state because the cache is stalling the cpu. + end else begin + NextState = STATE_MISS_WRITE_WORD; + end end - STATE_WRITE_MISS_WRITE_WORD: begin + STATE_MISS_READ_WORD_DELAY: begin + SelAdrM = 1'b1; + NextState = STATE_READY; + end + + STATE_MISS_WRITE_WORD: begin DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; @@ -530,14 +503,14 @@ module dcache SelAdrM = 1'b1; end - STATE_WRITE_MISS_EVICT_DIRTY: begin + STATE_MISS_EVICT_DIRTY: begin DCacheStall = 1'b1; PreCntEn = 1'b1; AHBWrite = 1'b1; if( FetchCountFlag & AHBAck) begin - NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin - NextState = STATE_WRITE_MISS_EVICT_DIRTY; + NextState = STATE_MISS_EVICT_DIRTY; end end From f26d635614be08bc780e6c4d7b72a12d139e9b64 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 22:34:47 -0500 Subject: [PATCH 012/112] Fixed the spurious AHB requests to address 0. Somehow by not having a default (else) in the fsm branch selection for STATE_READY in the d cache it was possible to take an invalid branch through the fsm. --- wally-pipelined/src/cache/dcache.sv | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 9b236596..2b199609 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -370,6 +370,7 @@ module dcache // fsm state regs +/* -----\/----- EXCLUDED -----\/----- flopenl #(.TYPE(statetype)) FSMReg(.clk(clk), .load(reset), @@ -377,6 +378,12 @@ module dcache .val(STATE_READY), .d(NextState), .q(CurrState)); + -----/\----- EXCLUDED -----/\----- */ + + always_ff @(posedge clk, posedge reset) + if (reset) CurrState <= #1 STATE_READY; + else CurrState <= #1 NextState; + // next state logic and some state ouputs. always_comb begin @@ -436,7 +443,9 @@ module dcache else if(|MemRWM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; end + else NextState = STATE_READY; end + STATE_AMO_UPDATE: begin NextState = STATE_AMO_WRITE; SaveSRAMRead = 1'b1; From 1cc258ade14f94e30556cd9d8266c75f39c9b97f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 12 Jul 2021 14:22:13 -0500 Subject: [PATCH 013/112] Progress towards the test bench flush. --- wally-pipelined/regression/wave.do | 97 ++++--- wally-pipelined/src/cache/DCacheMem.sv | 2 +- .../testbench/testbench-imperas.sv | 242 +++++++++++++++++- 3 files changed, 278 insertions(+), 63 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 501f71e4..68705908 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -250,25 +250,25 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM @@ -280,7 +280,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall @@ -295,8 +294,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetValidW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetDirtyW add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM @@ -396,8 +393,8 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {2797 ns} 0} {{Cursor 6} {3275 ns} 0} {{Cursor 8} {3905 ns} 0} {{Cursor 9} {4358 ns} 0} {{Cursor 10} {5007 ns} 0} {{Cursor 11} {57795 ns} 0} -quietly wave cursor active 6 +WaveRestoreCursors {{Cursor 12} {57781 ns} 0} {{Cursor 13} {7061 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 273 configure wave -justifyvalue left @@ -412,4 +409,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {57593 ns} {57969 ns} +WaveRestoreZoom {57704 ns} {58248 ns} diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index ba50f5dd..17591abe 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -53,7 +53,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 genvar words; generate - for(words = 0; words < BLOCKLEN/`XLEN; words++) begin + for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES)) CacheDataMem(.clk(clk), diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index a4daf7f3..cec962f5 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -44,14 +44,14 @@ module testbench(); logic [31:0] InstrW; logic [`XLEN-1:0] meminit; - //string tests32mmu[] = '{ - //"rv32mmu/WALLY-MMU-SV32", "3000" - // }; + string tests32mmu[] = '{ + "rv32mmu/WALLY-MMU-SV32", "3000" + }; - //string tests64mmu[] = '{ - //"rv64mmu/WALLY-MMU-SV48", "3000", - //"rv64mmu/WALLY-MMU-SV39", "3000" - //}; + string tests64mmu[] = '{ + "rv64mmu/WALLY-MMU-SV48", "3000", + "rv64mmu/WALLY-MMU-SV39", "3000" + }; string tests32f[] = '{ @@ -216,6 +216,7 @@ string tests32f[] = '{ string tests64i[] = '{ //"rv64i/WALLY-PIPELINE-100K", "f7ff0", + //"rv64i/WALLY-LOAD", "11bf0", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", @@ -286,7 +287,7 @@ string tests32f[] = '{ "rv64i/WALLY-SLLI", "3000", "rv64i/WALLY-SRLI", "3000", "rv64i/WALLY-SRAI", "3000", - "rv64i/WALLY-LOAD", "11bf0", + "rv64i/WALLY-JAL", "4000", "rv64i/WALLY-JALR", "3000", "rv64i/WALLY-STORE", "3000", @@ -513,6 +514,9 @@ string tests32f[] = '{ logic HCLK, HRESETn; logic [`XLEN-1:0] PCW; + logic DCacheFlushDone, DCacheFlushStart; + + logic [`XLEN-1:0] debug; assign debug = dut.uncore.dtim.RAM[536872960]; @@ -540,9 +544,10 @@ string tests32f[] = '{ else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; if (`A_SUPPORTED) tests = {tests, tests64a}; - //if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; + if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; + tests = {tests64i, tests}; end //tests = {tests64a, tests}; end else begin // RV32 @@ -625,9 +630,9 @@ string tests32f[] = '{ // check results always @(negedge clk) begin - if (dut.hart.priv.EcallFaultM && - (dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin + if (DCacheFlushDone) begin $display("Code ended with ecall with gp = 1"); + #60; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests for(i=0; i Date: Mon, 12 Jul 2021 15:13:27 -0500 Subject: [PATCH 014/112] Now updates the dtim with the dirty data in the dcache. Simulation is showing issues. It lookslike the cache is not evicting the correct data. --- .../testbench/testbench-imperas.sv | 46 +++++++++++-------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index cec962f5..061e5a6c 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -1022,12 +1022,35 @@ module DCacheFlushFSM else CurrState = NextState; end + integer adr; + integer tag; + integer index; + integer way; + integer word; + logic dirty, valid; + logic [`XLEN-1:0] data; + always_comb begin case (CurrState) IDLE: if(start) NextState = READ; else NextState = IDLE; READ: begin force testbench.dut.hart.lsu.dcache.SRAMAdr = count; + index = count / numways; + way = count % numways; + tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; + dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; + valid = testbench.dut.hart.lsu.dcache.Valid[way]; + adr = (tag << tagstart) + (index << logblockbytelen); + data = testbench.dut.hart.lsu.dcache.FinalReadDataWordM; + if (valid & dirty) begin + $display("Index Way Tag V D %03x %d %016x %d %d %016x %016x", index, way, tag, valid, dirty, adr, data); + force dut.uncore.dtim.A = adr; + force dut.uncore.dtim.HWDATA = data; + force dut.uncore.dtim.memwrite = 1; + force dut.uncore.dtim.risingHREADYTim = 1; + end + if(CountFlag) begin NextState = DONE; end else begin @@ -1036,6 +1059,10 @@ module DCacheFlushFSM end DONE: begin release testbench.dut.hart.lsu.dcache.SRAMAdr; + release dut.uncore.dtim.A; + release dut.uncore.dtim.HWDATA; + release dut.uncore.dtim.memwrite; + release dut.uncore.dtim.risingHREADYTim; NextState = DONE; end default: NextState = IDLE; @@ -1046,26 +1073,7 @@ module DCacheFlushFSM assign CntEn = CurrState == READ; - integer adr; - integer tag; - integer index; - integer way; - integer word; - - logic dirty, valid; - always_comb begin - if (CurrState == READ) begin - assign index = count / numways; - assign way = count % numways; - assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; - assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; - assign valid = testbench.dut.hart.lsu.dcache.Valid[way]; - assign adr = tag << (tagstart) + index; - - $display("Index Way Tag V D %03x %d %016x %d %d %016x", index, way, tag, valid, dirty, adr); - end - end endmodule From 49f6eec57980f0f8ceb5c0b39d8bb4e42f7b3ee0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 12 Jul 2021 23:46:32 -0500 Subject: [PATCH 015/112] Team work on solving the dcache data inconsistency problem. --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- wally-pipelined/regression/wave.do | 153 ++++++++++-------- wally-pipelined/src/cache/dcache.sv | 1 + .../testbench/testbench-imperas.sv | 143 +++++++--------- 4 files changed, 146 insertions(+), 153 deletions(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 44a90e1c..74519689 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h07FFFFFF +`define TIM_RANGE 56'h0007FFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 68705908..b2b477ba 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -expand -group alu -divider internals -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu -divider internals +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -258,31 +258,29 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW @@ -392,11 +390,34 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436996]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436997]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436998]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436999]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437000]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437011]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437012]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437268]} +add wave -noupdate /testbench/dut/uncore/dtim/RAM +add wave -noupdate /testbench/dut/uncore/dtim/A +add wave -noupdate /testbench/dut/uncore/dtim/HWDATA +add wave -noupdate /testbench/dut/uncore/dtim/memwrite +add wave -noupdate /testbench/dut/uncore/dtim/memread +add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate /testbench/dut/uncore/dtim/HCLK +add wave -noupdate /testbench/dut/hart/clk +add wave -noupdate /testbench/DCacheFlushFSM/CacheData +add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM +add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr +add wave -noupdate /testbench/DCacheFlushFSM/CacheData +add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty +add wave -noupdate /testbench/DCacheFlushFSM/CacheTag +add wave -noupdate /testbench/DCacheFlushFSM/CacheValid TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {57781 ns} 0} {{Cursor 13} {7061 ns} 0} +WaveRestoreCursors {{Cursor 12} {63874 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 -configure wave -valuecolwidth 273 +configure wave -valuecolwidth 297 configure wave -justifyvalue left configure wave -signalnamewidth 1 configure wave -snapdistance 10 @@ -409,4 +430,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {57704 ns} {58248 ns} +WaveRestoreZoom {0 ns} {67394 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 2b199609..a5443417 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -516,6 +516,7 @@ module dcache DCacheStall = 1'b1; PreCntEn = 1'b1; AHBWrite = 1'b1; + SelAdrM = 1'b1; if( FetchCountFlag & AHBAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 061e5a6c..b9b14558 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -630,10 +630,14 @@ string tests32f[] = '{ // check results always @(negedge clk) begin - if (DCacheFlushDone) begin + if (dut.hart.priv.EcallFaultM && + (dut.hart.ieu.dp.regf.rf[3] == 1 || + (dut.hart.ieu.dp.regf.we3 && + dut.hart.ieu.dp.regf.a3 == 3 && + dut.hart.ieu.dp.regf.wd3 == 1))) begin $display("Code ended with ecall with gp = 1"); - #60; // give time for instructions in pipeline to finish + #600; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests for(i=0; i>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)]; - logic [lognumways + lognumlines - 1 : 0] count, countNext; - - flopenr #(lognumlines + lognumways) - FetchCountReg(.clk(clk), - .reset(reset), - .en(CntEn), - .d(countNext), - .q(count)); - - assign countNext = count + 1; - assign CountFlag = count == '1; - - always_ff @(posedge clk, posedge reset) begin - if(reset) CurrState = IDLE; - else CurrState = NextState; - end - - integer adr; - integer tag; - integer index; - integer way; - integer word; - logic dirty, valid; - logic [`XLEN-1:0] data; - - always_comb begin - case (CurrState) - IDLE: if(start) NextState = READ; - else NextState = IDLE; - READ: begin - force testbench.dut.hart.lsu.dcache.SRAMAdr = count; - index = count / numways; - way = count % numways; - tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; - dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; - valid = testbench.dut.hart.lsu.dcache.Valid[way]; - adr = (tag << tagstart) + (index << logblockbytelen); - data = testbench.dut.hart.lsu.dcache.FinalReadDataWordM; - if (valid & dirty) begin - $display("Index Way Tag V D %03x %d %016x %d %d %016x %016x", index, way, tag, valid, dirty, adr, data); - force dut.uncore.dtim.A = adr; - force dut.uncore.dtim.HWDATA = data; - force dut.uncore.dtim.memwrite = 1; - force dut.uncore.dtim.risingHREADYTim = 1; - end - - if(CountFlag) begin - NextState = DONE; - end else begin - NextState = READ; + generate + for(index = 0; index < numlines; index++) begin + for(way = 0; way < numways; way++) begin + assign CacheTag[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index]; + assign CacheValid[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index]; + assign CacheDirty[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index]; + for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin + assign CacheData[way][index][cacheWord] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index]; + assign CacheAdr[way][index][cacheWord] = ((CacheTag[way][index] << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8))); end end - DONE: begin - release testbench.dut.hart.lsu.dcache.SRAMAdr; - release dut.uncore.dtim.A; - release dut.uncore.dtim.HWDATA; - release dut.uncore.dtim.memwrite; - release dut.uncore.dtim.risingHREADYTim; - NextState = DONE; - end - default: NextState = IDLE; - endcase - end - - assign done = CurrState == DONE; - assign CntEn = CurrState == READ; + end + endgenerate + integer i, j, k; - + always @(posedge clk) begin + if (start) begin #1 + for(i = 0; i < numlines; i++) begin + for(j = 0; j < numways; j++) begin + for(k = 0; k < numwords; k++) begin + $display("Help me!") + ShadowRAM[CacheAdr[j][i][k]] = CacheData[j][i][k]; + end + end + end + end + end + + endmodule @@ -1167,20 +1138,20 @@ task FlushDCache; logic [`XLEN-1:0] CacheData; assign value = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[0]; - - for(index = 0; index < numlines; index++) begin - for(way = 0; way < numways; way++) begin - for(word = 0; word < numwords; word++) begin - assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index]; - - path = $sformatf(GenericCacheDataMem, way, word, index); - // I guess you cannot do this conversion. - //assign CacheData = path; - $display("%x", path); - $display(CacheData); + + for(index = 0; index < numlines; index++) begin + for(way = 0; way < numways; way++) begin + for(word = 0; word < numwords; word++) begin + assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index]; + + path = $sformatf(GenericCacheDataMem, way, word, index); + // I guess you cannot do this conversion. + //assign CacheData = path; + $display("%x", path); + $display(CacheData); + end end end - end $display("%x", value); From e594eb540dd8ba21e402efbeaa892ddec8e5707e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 10:03:47 -0500 Subject: [PATCH 016/112] Got the shadow ram cache flush working. --- wally-pipelined/regression/wave.do | 9 ++++++--- .../testbench/testbench-imperas.sv | 19 +++++++++++++------ 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index b2b477ba..753e5195 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -402,19 +402,22 @@ add wave -noupdate /testbench/dut/uncore/dtim/RAM add wave -noupdate /testbench/dut/uncore/dtim/A add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/memwrite +add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memread add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate /testbench/dut/uncore/dtim/HCLK add wave -noupdate /testbench/dut/hart/clk add wave -noupdate /testbench/DCacheFlushFSM/CacheData -add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr add wave -noupdate /testbench/DCacheFlushFSM/CacheData add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty add wave -noupdate /testbench/DCacheFlushFSM/CacheTag add wave -noupdate /testbench/DCacheFlushFSM/CacheValid +add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/clk +add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/start +add wave -noupdate -expand -group shadowram -color Orchid /testbench/DCacheFlushFSM/ShadowRAM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {63874 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} +WaveRestoreCursors {{Cursor 12} {63589 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -430,4 +433,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {67394 ns} +WaveRestoreZoom {63529 ns} {63661 ns} diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index b9b14558..fa43c560 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -630,11 +630,14 @@ string tests32f[] = '{ // check results always @(negedge clk) begin +/* -----\/----- EXCLUDED -----\/----- if (dut.hart.priv.EcallFaultM && (dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin + -----/\----- EXCLUDED -----/\----- */ + if (DCacheFlushDone) begin $display("Code ended with ecall with gp = 1"); #600; // give time for instructions in pipeline to finish @@ -1035,16 +1038,20 @@ module DCacheFlushFSM if (start) begin #1 for(i = 0; i < numlines; i++) begin for(j = 0; j < numways; j++) begin - for(k = 0; k < numwords; k++) begin - $display("Help me!") - ShadowRAM[CacheAdr[j][i][k]] = CacheData[j][i][k]; - end + if (CacheValid[j][i] && CacheDirty[j][i]) begin + for(k = 0; k < numwords; k++) begin + ShadowRAM[CacheAdr[j][i][k]/8] = CacheData[j][i][k]; + end + end end end end end - - + + + flop #(1) doneReg(.clk(clk), + .d(start), + .q(done)); endmodule From 3951eb56f56eeb681959d0c46496d5fa730d63cd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 10:55:57 -0500 Subject: [PATCH 017/112] Modularized the shadow memory to reduce performance hit. --- .../testbench/testbench-imperas.sv | 161 +++++------------- 1 file changed, 44 insertions(+), 117 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index fa43c560..25cb1ef6 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -1009,10 +1009,9 @@ module DCacheFlushFSM genvar index, way, cacheWord; logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0]; - logic CacheValid [numways-1:0] [numlines-1:0]; - logic CacheDirty [numways-1:0] [numlines-1:0]; - + logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0]; + logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0]; + logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0]; logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0]; genvar adr; @@ -1021,26 +1020,37 @@ module DCacheFlushFSM generate for(index = 0; index < numlines; index++) begin for(way = 0; way < numways; way++) begin - assign CacheTag[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index]; - assign CacheValid[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index]; - assign CacheDirty[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index]; for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin - assign CacheData[way][index][cacheWord] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index]; - assign CacheAdr[way][index][cacheWord] = ((CacheTag[way][index] << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8))); + copyShadow #(.tagstart(tagstart)) + copyShadow(.clk, + .start, + .tag(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index]), + .valid(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index]), + .dirty(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index]), + .data(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index]), + .Adr(((testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index] << tagstart) + + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)))), + .CacheData(CacheData[way][index][cacheWord]), + .CacheAdr(CacheAdr[way][index][cacheWord]), + .CacheTag(CacheTag[way][index][cacheWord]), + .CacheValid(CacheValid[way][index][cacheWord]), + .CacheDirty(CacheDirty[way][index][cacheWord])); end end end endgenerate + integer i, j, k; always @(posedge clk) begin if (start) begin #1 + #1 for(i = 0; i < numlines; i++) begin for(j = 0; j < numways; j++) begin - if (CacheValid[j][i] && CacheDirty[j][i]) begin - for(k = 0; k < numwords; k++) begin - ShadowRAM[CacheAdr[j][i][k]/8] = CacheData[j][i][k]; + for(k = 0; k < numwords; k++) begin + if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin + ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; end end end @@ -1054,114 +1064,31 @@ module DCacheFlushFSM .q(done)); endmodule - -task FlushDCache; - // takes no inputs or ouptuts but controls logics in the d cache. - - // two possible implementations. - // 1) Can directly read/set the cache SRAM and the dtim. - // The problem here is the structure of the cache is - // not really easily known. - // 2) Use the cache's interface to read out blocks. - // The problem is we must do this over clock cycles. - // Honestly not sure which is easier. - // I don't think method 1 is possible because verilog cannot convert a string into - // an object's hierarchy or it is not possible because verilog cannot use - // variable index inside a generate block. - - // path to d cache parameterization - //sim:/testbench/dut/hart/lsu/dcache/NUMLINES - //sim:/testbench/dut/hart/lsu/dcache/NUMWAYS - //sim:/testbench/dut/hart/lsu/dcache/BLOCKBYTELEN - - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits - - static string GenericCacheDataMem = "testbench.dut.hart.lsu.dcache.CacheWays[%0d].MemWay.word[%0d].CacheDataMem.StoredData[%0d]"; - static string GenericCacheTagMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.CacheTagMem.StoredData[%d]"; - static string GenericCacheValidMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.ValidBits[%d]"; - static string GenericCacheDirtyMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.DirtyBits[%d]"; - +module copyShadow + #(parameter tagstart) + (input logic clk, + input logic start, + input logic [`PA_BITS-1:tagstart] tag, + input logic valid, dirty, + input logic [`XLEN-1:0] data, + input logic [`PA_BITS-1:tagstart] Adr, + output logic [`XLEN-1:0] CacheData, + output logic [`PA_BITS-1:0] CacheAdr, + output logic [`XLEN-1:0] CacheTag, + output logic CacheValid, + output logic CacheDirty); - const integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES; - const integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS; - const integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN; - const integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN; - const integer lognumlines = $clog2(numlines); - const integer logblockbytelen = $clog2(blockbytelen); - const integer tagstart = lognumlines + logblockbytelen; - - - - // drive SRAMAdr - //sim:/testbench/dut/hart/lsu/dcache/SRAMAdr - // Read ReadTag and then mux out on the NUMWAYS - //sim:/testbench/dut/hart/lsu/dcache/ReadTag - //sim:/testbench/dut/hart/lsu/dcache/Valid - //sim:/testbench/dut/hart/lsu/dcache/Dirty - - // if Valid and Dirty we write to dtim - - logic [`PA_BITS-1:0] FullAdr; - - integer adr; - integer tag; - integer index; - integer way; - integer word; - - logic dirty, valid; - - logic [`XLEN-1:0] value; - - - - -/* -----\/----- EXCLUDED -----\/----- - $display("%d %d", tagstart, logblockbytelen); - - - for(adr = 0; adr < numways * numlines; adr++) begin - assign way = adr % numways; - assign index = adr / numways; - force testbench.dut.hart.lsu.dcache.SRAMAdr = index; - assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; - assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; - assign valid = testbench.dut.hart.lsu.dcache.Valid[way]; - assign FullAdr = tag< Date: Tue, 13 Jul 2021 11:18:54 -0500 Subject: [PATCH 018/112] restored rv64ic config back to full sized dtim. --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 74519689..44a90e1c 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h0007FFFF +`define TIM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF From 224e3b299196252cc32c64e6022a72e52e8a2cba Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 11:21:44 -0500 Subject: [PATCH 019/112] Fixed subword write. subword read should not feed into subword write. --- wally-pipelined/src/cache/dcache.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index a5443417..f36a962c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -239,7 +239,7 @@ module dcache .q(ReadDataW)); // write path - subwordwrite subwordwrite(.HRDATA(FinalReadDataWordM), + subwordwrite subwordwrite(.HRDATA(ReadDataWordM), .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HWDATAIN(WriteDataM), From 47e16f56293c152b36ae07be534a5d5097987dcd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 12:46:20 -0500 Subject: [PATCH 020/112] Fixed back to back store issue. Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals. --- wally-pipelined/src/cache/dcache.sv | 15 ++++++++++++--- wally-pipelined/src/ieu/controller.sv | 3 ++- wally-pipelined/src/ieu/ieu.sv | 3 ++- wally-pipelined/src/lsu/lsu.sv | 4 ++++ wally-pipelined/src/wally/wallypipelinedhart.sv | 4 ++++ 5 files changed, 24 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index f36a962c..d4391cc6 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -34,9 +34,11 @@ module dcache input logic FlushW, // cpu side + input logic [1:0] MemRWE, input logic [1:0] MemRWM, input logic [2:0] Funct3M, input logic [6:0] Funct7M, + input logic [1:0] AtomicE, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address @@ -299,6 +301,7 @@ module dcache // control path *** eventually move to own module. logic AnyCPUReqM; + logic AnyCPUReqE; logic FetchCountFlag; logic PreCntEn; logic CntEn; @@ -349,6 +352,7 @@ module dcache assign AnyCPUReqM = |MemRWM | (|AtomicM); + assign AnyCPUReqE = |MemRWE | (|AtomicE); assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); flopenr #(LOGWPL+1) @@ -406,7 +410,7 @@ module dcache case (CurrState) STATE_READY: begin // sram busy - if (AnyCPUReqM & SRAMWordWriteEnableW) begin + if (AnyCPUReqE & SRAMWordWriteEnableM) begin NextState = STATE_SRAM_BUSY; DCacheStall = 1'b1; end @@ -505,11 +509,16 @@ module dcache end STATE_MISS_WRITE_WORD: begin - DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; - NextState = STATE_READY; SelAdrM = 1'b1; + if (AnyCPUReqE & SRAMWordWriteEnableM) begin + NextState = STATE_SRAM_BUSY; + DCacheStall = 1'b1; + end else begin + NextState = STATE_READY; + DCacheStall = 1'b0; + end end STATE_MISS_EVICT_DIRTY: begin diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 16fd5a8f..09715a4b 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -52,6 +52,7 @@ module controller( output logic [1:0] MemRWM, output logic CSRReadM, CSRWriteM, PrivilegedM, output logic SCE, + output logic [1:0] AtomicE, output logic [1:0] AtomicM, output logic [2:0] Funct3M, output logic RegWriteM, // for Hazard Unit @@ -84,7 +85,7 @@ module controller( logic TargetSrcD, W64D, MulDivD; logic CSRZeroSrcD; logic CSRReadD; - logic [1:0] AtomicD, AtomicE; + logic [1:0] AtomicD; logic CSRWriteD, CSRWriteE; logic InstrValidD, InstrValidE; logic PrivilegedD, PrivilegedE; diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 39237806..8cac0937 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -47,7 +47,9 @@ module ieu ( // Memory stage interface input logic DataMisalignedM, // from LSU input logic SquashSCW, // from LSU + output logic [1:0] MemRWE, // read/write control goes to LSU output logic [1:0] MemRWM, // read/write control goes to LSU + output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU @@ -86,7 +88,6 @@ module ieu ( logic RegWriteM, RegWriteW; logic MemReadE, CSRReadE; logic JumpE; - logic [1:0] MemRWE; controller c(.*); datapath dp(.*); diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 432645f7..29190c3c 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -37,9 +37,11 @@ module lsu // connected to cpu (controls) input logic [1:0] MemRWM, + input logic [1:0] MemRWE, input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic [1:0] AtomicM, + input logic [1:0] AtomicE, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, @@ -299,10 +301,12 @@ module lsu .StallW(StallW), .FlushM(FlushM), .FlushW(FlushW), + .MemRWE(MemRWE), // *** add to arb .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), .AtomicM(AtomicMtoDCache), + .AtomicE(AtomicE), // *** add to arb .MemAdrE(MemAdrEtoDCache), // *** add to arb .MemPAdrM(MemPAdrM), .WriteDataM(WriteDataM), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 80a0b32a..5bcd4697 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -63,6 +63,7 @@ module wallypipelinedhart // new signals that must connect through DP logic MulDivE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; + logic [1:0] AtomicE; logic [1:0] AtomicM; logic [`XLEN-1:0] SrcAE, SrcBE; logic [`XLEN-1:0] SrcAM; @@ -73,6 +74,7 @@ module wallypipelinedhart logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; + logic [1:0] MemRWE; logic [1:0] MemRWM; logic InstrValidM, InstrValidW; logic InstrMisalignedFaultM; @@ -174,9 +176,11 @@ module wallypipelinedhart .StallW(StallW), .FlushW(FlushW), // CPU interface + .MemRWE(MemRWE), .MemRWM(MemRWM), .Funct3M(Funct3M), .Funct7M(InstrM[31:25]), + .AtomicE(AtomicE), .AtomicM(AtomicM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), From afc1bc9c382ded5ab7d28c406c4ddee6a6e9d668 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 13:20:50 -0500 Subject: [PATCH 021/112] Moved StoreStall into the hazard unit instead of in the d cache. --- wally-pipelined/regression/wave.do | 69 +++++++------------ wally-pipelined/src/cache/dcache.sv | 40 ++--------- wally-pipelined/src/hazard/hazard.sv | 4 +- wally-pipelined/src/ieu/controller.sv | 7 +- wally-pipelined/src/ieu/ieu.sv | 3 +- wally-pipelined/src/lsu/lsu.sv | 4 -- .../src/wally/wallypipelinedhart.sv | 4 +- 7 files changed, 38 insertions(+), 93 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 753e5195..eba2ff09 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -239,6 +239,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testben add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/AnyCPUReqE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM @@ -258,12 +259,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay @@ -390,34 +393,8 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436996]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436997]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436998]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436999]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437000]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437011]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437012]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437268]} -add wave -noupdate /testbench/dut/uncore/dtim/RAM -add wave -noupdate /testbench/dut/uncore/dtim/A -add wave -noupdate /testbench/dut/uncore/dtim/HWDATA -add wave -noupdate /testbench/dut/uncore/dtim/memwrite -add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim -add wave -noupdate /testbench/dut/uncore/dtim/memread -add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate /testbench/dut/uncore/dtim/HCLK -add wave -noupdate /testbench/dut/hart/clk -add wave -noupdate /testbench/DCacheFlushFSM/CacheData -add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr -add wave -noupdate /testbench/DCacheFlushFSM/CacheData -add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty -add wave -noupdate /testbench/DCacheFlushFSM/CacheTag -add wave -noupdate /testbench/DCacheFlushFSM/CacheValid -add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/clk -add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/start -add wave -noupdate -expand -group shadowram -color Orchid /testbench/DCacheFlushFSM/ShadowRAM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {63589 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} +WaveRestoreCursors {{Cursor 12} {1053664 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -433,4 +410,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {63529 ns} {63661 ns} +WaveRestoreZoom {1053586 ns} {1053736 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index d4391cc6..64ed5367 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -34,11 +34,9 @@ module dcache input logic FlushW, // cpu side - input logic [1:0] MemRWE, input logic [1:0] MemRWM, input logic [2:0] Funct3M, input logic [6:0] Funct7M, - input logic [1:0] AtomicE, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address @@ -301,7 +299,6 @@ module dcache // control path *** eventually move to own module. logic AnyCPUReqM; - logic AnyCPUReqE; logic FetchCountFlag; logic PreCntEn; logic CntEn; @@ -333,7 +330,6 @@ module dcache STATE_AMO_MISS_WRITE_WORD, STATE_AMO_UPDATE, STATE_AMO_WRITE, - STATE_SRAM_BUSY, STATE_PTW_READY, STATE_PTW_MISS_FETCH_WDV, STATE_PTW_MISS_FETCH_DONE, @@ -352,7 +348,6 @@ module dcache assign AnyCPUReqM = |MemRWM | (|AtomicM); - assign AnyCPUReqE = |MemRWE | (|AtomicE); assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); flopenr #(LOGWPL+1) @@ -373,17 +368,6 @@ module dcache .q({SRAMWordWriteEnableW})); - // fsm state regs -/* -----\/----- EXCLUDED -----\/----- - flopenl #(.TYPE(statetype)) - FSMReg(.clk(clk), - .load(reset), - .en(1'b1), - .val(STATE_READY), - .d(NextState), - .q(CurrState)); - -----/\----- EXCLUDED -----/\----- */ - always_ff @(posedge clk, posedge reset) if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; @@ -409,13 +393,8 @@ module dcache case (CurrState) STATE_READY: begin - // sram busy - if (AnyCPUReqE & SRAMWordWriteEnableM) begin - NextState = STATE_SRAM_BUSY; - DCacheStall = 1'b1; - end // TLB Miss - else if(AnyCPUReqM & DTLBMissM) begin + if(AnyCPUReqM & DTLBMissM) begin NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit @@ -434,6 +413,7 @@ module dcache DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end @@ -444,7 +424,7 @@ module dcache DCacheStall = 1'b1; end // fault - else if(|MemRWM & FaultM & ~DTLBMissM) begin + else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; end else NextState = STATE_READY; @@ -512,13 +492,8 @@ module dcache SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; SelAdrM = 1'b1; - if (AnyCPUReqE & SRAMWordWriteEnableM) begin - NextState = STATE_SRAM_BUSY; - DCacheStall = 1'b1; - end else begin - NextState = STATE_READY; - DCacheStall = 1'b0; - end + NextState = STATE_READY; + DCacheStall = 1'b0; end STATE_MISS_EVICT_DIRTY: begin @@ -543,11 +518,6 @@ module dcache end end - STATE_SRAM_BUSY: begin - DCacheStall = 1'b0; - NextState = STATE_READY; - end - STATE_CPU_BUSY : begin if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index f5552106..331fc326 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -30,7 +30,7 @@ module hazard( input logic reset, // Detect hazards input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, - input logic LoadStallD, MulDivStallD, CSRRdStallD, + input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, input logic DCacheStall, ICacheStallF, input logic FPUStallD, FStallD, input logic DivBusyE,FDivBusyE, @@ -56,7 +56,7 @@ module hazard( // If any stages are stalled, the first stage that isn't stalled must flush. assign StallFCause = CSRWritePendingDEM && ~(TrapM | RetM | BPPredWrongE); - assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous + assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallECause = DivBusyE | FDivBusyE; assign StallMCause = 0; assign StallWCause = DCacheStall | ICacheStallF; diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 09715a4b..87976736 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -63,7 +63,8 @@ module controller( output logic [2:0] ResultSrcW, output logic InstrValidW, // Stall during CSRs - output logic CSRWritePendingDEM + output logic CSRWritePendingDEM, + output logic StoreStallD ); logic [6:0] OpD; @@ -219,5 +220,7 @@ module controller( {RegWriteM, ResultSrcM, InstrValidM}, {RegWriteW, ResultSrcW, InstrValidW}); - assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM; + assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM; + + assign StoreStallD = MemRWE[0] & (|MemRWD | |AtomicD); endmodule diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 8cac0937..95761c36 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -71,7 +71,8 @@ module ieu ( input logic DivDoneE, input logic DivBusyE, output logic CSRReadM, CSRWriteM, PrivilegedM, - output logic CSRWritePendingDEM + output logic CSRWritePendingDEM, + output logic StoreStallD ); logic [2:0] ImmSrcD; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 29190c3c..432645f7 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -37,11 +37,9 @@ module lsu // connected to cpu (controls) input logic [1:0] MemRWM, - input logic [1:0] MemRWE, input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic [1:0] AtomicM, - input logic [1:0] AtomicE, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, @@ -301,12 +299,10 @@ module lsu .StallW(StallW), .FlushM(FlushM), .FlushW(FlushW), - .MemRWE(MemRWE), // *** add to arb .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), .AtomicM(AtomicMtoDCache), - .AtomicE(AtomicE), // *** add to arb .MemAdrE(MemAdrEtoDCache), // *** add to arb .MemPAdrM(MemPAdrM), .WriteDataM(WriteDataM), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 5bcd4697..f094df60 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -91,7 +91,7 @@ module wallypipelinedhart logic DivDoneE; logic DivBusyE; logic RegWriteD; - logic LoadStallD, MulDivStallD, CSRRdStallD; + logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD; logic SquashSCM, SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; @@ -176,11 +176,9 @@ module wallypipelinedhart .StallW(StallW), .FlushW(FlushW), // CPU interface - .MemRWE(MemRWE), .MemRWM(MemRWM), .Funct3M(Funct3M), .Funct7M(InstrM[31:25]), - .AtomicE(AtomicE), .AtomicM(AtomicM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), From 32f27cfecf8a6425feae5c2b5d07c768c982f3a6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 14:19:04 -0500 Subject: [PATCH 022/112] Dcache AHB address generation was wrong. Needed to zero the offset. --- wally-pipelined/regression/wave.do | 65 ++++++++++++++--------------- wally-pipelined/src/cache/dcache.sv | 7 ++-- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index eba2ff09..da660f1c 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -209,9 +209,6 @@ add wave -noupdate -group icache -expand -group memory -group {tag write} /testb add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF -add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA -add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked -add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM @@ -220,7 +217,6 @@ add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/har add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA -add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATANext add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR @@ -239,7 +235,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testben add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/AnyCPUReqE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM @@ -259,42 +254,41 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM @@ -393,9 +387,14 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate /testbench/dut/uncore/dtim/HWADDR +add wave -noupdate /testbench/dut/uncore/dtim/A +add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim +add wave -noupdate /testbench/dut/uncore/dtim/memwrite +add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1053664 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 12} {1303660 ns} 0} {{Cursor 4} {1303875 ns} 0} {{Cursor 5} {1304387 ns} 0} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -410,4 +409,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1053586 ns} {1053736 ns} +WaveRestoreZoom {1304315 ns} {1304659 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 64ed5367..dee05b12 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -268,7 +268,7 @@ module dcache // *** Coding style. this is just awful. The purpose is to align FetchCount to the // size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length. - + // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .s(AHBWrite), @@ -276,9 +276,9 @@ module dcache generate if (`XLEN == 32) begin - assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrM; + assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; end else begin - assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrM; + assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; end endgenerate @@ -469,6 +469,7 @@ module dcache NextState = STATE_MISS_READ_WORD; SelAdrM = 1'b1; SetValidM = 1'b1; + ClearDirtyM = 1'b1; end STATE_MISS_READ_WORD: begin From 3c1a717399afd227e0b1b6de226965c4077a656a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 14:21:29 -0500 Subject: [PATCH 023/112] Fixed the fetch buffer accidental overwrite on eviction. --- wally-pipelined/regression/wave.do | 23 ++++++++++++----------- wally-pipelined/src/cache/dcache.sv | 2 +- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index da660f1c..bc290a92 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -238,6 +238,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} @@ -254,14 +255,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay @@ -393,8 +394,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1303660 ns} 0} {{Cursor 4} {1303875 ns} 0} {{Cursor 5} {1304387 ns} 0} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 12} {1303743 ns} 0} {{Cursor 4} {1304324 ns} 0} {{Cursor 5} {1303977 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -409,4 +410,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1304315 ns} {1304659 ns} +WaveRestoreZoom {1303670 ns} {1304014 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index dee05b12..9fe98b74 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -260,7 +260,7 @@ module dcache generate for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer flopen #(`XLEN) fb(.clk(clk), - .en(AHBAck & (index == FetchCount)), + .en(AHBAck & AHBRead & (index == FetchCount)), .d(HRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); end From baa2b5d15f793ccde2fae00d13885a29b3bb2a86 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 14:51:42 -0500 Subject: [PATCH 024/112] Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. --- wally-pipelined/regression/wave.do | 6 +++--- wally-pipelined/src/cache/dcache.sv | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index bc290a92..807eacba 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -394,8 +394,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1303743 ns} 0} {{Cursor 4} {1304324 ns} 0} {{Cursor 5} {1303977 ns} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 12} {1978950 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {2053811 ns} 0} +quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -410,4 +410,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1303670 ns} {1304014 ns} +WaveRestoreZoom {1979564 ns} {1979828 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 9fe98b74..3bcd4719 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -401,11 +401,17 @@ module dcache else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end // read hit valid cached else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_READY; DCacheStall = 1'b0; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end // write hit valid cached else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin From 3e57c899a2f13b423bcebd8db6336fa5c5f84792 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 17:24:59 -0500 Subject: [PATCH 025/112] Partially working changes to support uncached memory access. Not sure what CommitedM is. --- wally-pipelined/regression/wave.do | 77 ++++++++++--------- wally-pipelined/src/cache/dcache.sv | 47 ++++++++--- wally-pipelined/src/ifu/ifu.sv | 3 + wally-pipelined/src/lsu/lsu.sv | 25 ++++-- wally-pipelined/src/mmu/mmu.sv | 2 +- .../src/wally/wallypipelinedhart.sv | 5 +- .../testbench/testbench-imperas.sv | 1 - 7 files changed, 103 insertions(+), 57 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 807eacba..f53880fd 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -239,22 +239,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM @@ -272,8 +272,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM @@ -290,6 +288,15 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM @@ -312,20 +319,20 @@ add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR @@ -394,8 +401,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1978950 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {2053811 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -410,4 +417,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1979564 ns} {1979828 ns} +WaveRestoreZoom {4642 ns} {4816 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3bcd4719..f33385df 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -48,7 +48,7 @@ module dcache // inputs from TLB and PMA/P input logic FaultM, input logic DTLBMissM, - input logic UncachedM, + input logic CacheableM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -114,6 +114,8 @@ module dcache logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [`PA_BITS-1:0] BasePAdrM; + logic [OFFSETLEN-1:0] BasePAdrOffsetM; + logic [`PA_BITS-1:0] BasePAdrMaskedM; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; @@ -224,7 +226,7 @@ module dcache // variable input mux assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; - assign HWDATA = VictimReadDataBlockSetsM[FetchCount]; + assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM; // finally swr // *** BUG fix HSIZED? why was it this way? @@ -271,14 +273,17 @@ module dcache // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .s(AHBWrite), + .s(AHBWrite & CacheableM), .y(BasePAdrM)); + + assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; + assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; generate if (`XLEN == 32) begin - assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; + assign AHBPAdr = ({{`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrMaskedM; end else begin - assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; + assign AHBPAdr = ({{`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrMaskedM; end endgenerate @@ -339,6 +344,8 @@ module dcache STATE_PTW_MISS_READ_SRAM, STATE_UNCACHED_WDV, STATE_UNCACHED_DONE, + STATE_UNCACHED_WRITE, + STATE_UNCACHED_WRITE_DONE, STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -398,7 +405,7 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit - else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; @@ -406,7 +413,7 @@ module dcache else NextState = STATE_READY; end // read hit valid cached - else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -414,7 +421,7 @@ module dcache else NextState = STATE_READY; end // write hit valid cached - else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin SelAdrM = 1'b1; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; @@ -424,11 +431,19 @@ module dcache else NextState = STATE_READY; end // read or write miss valid cached - else if((|MemRWM) & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; end + // uncached write + else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_WRITE; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBWrite = 1'b1; + + end // fault else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; @@ -529,6 +544,20 @@ module dcache if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end + + STATE_UNCACHED_WRITE : begin + DCacheStall = 1'b1; + AHBWrite = 1'b1; + if(AHBAck) begin + NextState = STATE_UNCACHED_WRITE_DONE; + end else begin + NextState = STATE_UNCACHED_WRITE; + end + end + + STATE_UNCACHED_WRITE_DONE: begin + NextState = STATE_READY; + end default: begin end endcase diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index e306efa4..af5686d5 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -136,6 +136,9 @@ module ifu ( .LoadAccessFaultM(), .StoreAccessFaultM(), .DisableTranslation(1'b0), + .Cacheable(), + .Idempotent(), + .AtomicAllowed(), .*); diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 432645f7..9ed573a9 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -62,12 +62,13 @@ module lsu // connect to ahb input logic CommitM, // should this be generated in the abh interface? - output logic [`PA_BITS-1:0] DCtoAHBPAdrM, // to ahb + output logic [`PA_BITS-1:0] DCtoAHBPAdrM, output logic DCtoAHBReadM, output logic DCtoAHBWriteM, - input logic DCfromAHBAck, // from ahb - input logic [`XLEN-1:0] DCfromAHBReadData, // from ahb - output logic [`XLEN-1:0] DCtoAHBWriteData, // to ahb + input logic DCfromAHBAck, + input logic [`XLEN-1:0] DCfromAHBReadData, + output logic [`XLEN-1:0] DCtoAHBWriteData, + output logic [2:0] DCtoAHBSizeM, // mmu management @@ -140,8 +141,8 @@ module lsu logic HPTWReady; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. logic DCacheStall; - - + + logic CacheableM; pagetablewalker pagetablewalker( .clk(clk), @@ -223,9 +224,19 @@ module lsu .SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), + .Cacheable(CacheableM), + .Idempotent(), + .AtomicAllowed(), // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + + generate + if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache; + else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache; + endgenerate; + + // Specify which type of page fault is occurring assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoDCache[1]; assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoDCache[0]; @@ -310,7 +321,7 @@ module lsu .DCacheStall(DCacheStall), .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. .DTLBMissM(DTLBMissM), - .UncachedM(1'b0), // ***connect to PMA + .CacheableM(CacheableM), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 9372f473..d71cbe81 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -60,6 +60,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, + output logic Cacheable, Idempotent, AtomicAllowed, // Faults output logic TLBPageFault, @@ -76,7 +77,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries ); logic PMPSquashBusAccess, PMASquashBusAccess; - logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here. // Translation lookaside buffer logic PMAInstrAccessFaultF, PMPInstrAccessFaultF; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index f094df60..55c8959f 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -196,6 +196,7 @@ module wallypipelinedhart .DCfromAHBAck(DCfromAHBAck), .DCfromAHBReadData(DCfromAHBReadData), .DCtoAHBWriteData(DCtoAHBWriteData), + .DCtoAHBSizeM(DCtoAHBSizeM), // connect to csr or privilege and stay the same. .PrivilegeModeW(PrivilegeModeW), // connects to csr @@ -231,10 +232,6 @@ module wallypipelinedhart .LSUStall(DCacheStall)); // change to DCacheStall - generate - if (`XLEN == 32) assign DCtoAHBSizeM = 3'b010; - else assign DCtoAHBSizeM = 3'b011; - endgenerate; ahblite ebu(// IFU connections diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 25cb1ef6..654c34fb 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -547,7 +547,6 @@ string tests32f[] = '{ if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - tests = {tests64i, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From e8bf502bc270241b2bca9da0200f07855f9a5559 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 22:43:42 -0500 Subject: [PATCH 026/112] Added CommitedM to data cache output. --- wally-pipelined/src/cache/dcache.sv | 20 +++++++++++++------- wally-pipelined/src/lsu/lsu.sv | 6 +++--- wally-pipelined/src/lsu/lsuArb.sv | 3 --- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index f33385df..9f2c0652 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -44,6 +44,7 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, output logic DCacheStall, + output logic CommittedM, // inputs from TLB and PMA/P input logic FaultM, @@ -311,12 +312,6 @@ module dcache typedef enum {STATE_READY, - STATE_READ_MISS_FETCH_WDV, - STATE_READ_MISS_FETCH_DONE, - STATE_READ_MISS_CHECK_EVICTED_DIRTY, - STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_READ_MISS_WRITE_CACHE_BLOCK, - STATE_READ_MISS_READ_WORD, STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_DONE, STATE_MISS_EVICT_DIRTY, @@ -397,7 +392,8 @@ module dcache AHBRead = 1'b0; AHBWrite = 1'b0; SelAMOWrite = 1'b0; - + CommittedM = 1'b0; + case (CurrState) STATE_READY: begin // TLB Miss @@ -466,6 +462,8 @@ module dcache PreCntEn = 1'b1; AHBRead = 1'b1; SelAdrM = 1'b1; + CommittedM = 1'b1; + if (FetchCountFlag & AHBAck) begin NextState = STATE_MISS_FETCH_DONE; end else begin @@ -477,6 +475,7 @@ module dcache DCacheStall = 1'b1; SelAdrM = 1'b1; CntReset = 1'b1; + CommittedM = 1'b1; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; end else begin @@ -491,11 +490,13 @@ module dcache SelAdrM = 1'b1; SetValidM = 1'b1; ClearDirtyM = 1'b1; + CommittedM = 1'b1; end STATE_MISS_READ_WORD: begin SelAdrM = 1'b1; DCacheStall = 1'b1; + CommittedM = 1'b1; if (MemRWM[1]) begin NextState = STATE_MISS_READ_WORD_DELAY; // delay state is required as the read signal MemRWM[1] is still high when we @@ -508,6 +509,7 @@ module dcache STATE_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; NextState = STATE_READY; + CommittedM = 1'b1; end STATE_MISS_WRITE_WORD: begin @@ -516,6 +518,7 @@ module dcache SelAdrM = 1'b1; NextState = STATE_READY; DCacheStall = 1'b0; + CommittedM = 1'b1; end STATE_MISS_EVICT_DIRTY: begin @@ -523,6 +526,7 @@ module dcache PreCntEn = 1'b1; AHBWrite = 1'b1; SelAdrM = 1'b1; + CommittedM = 1'b1; if( FetchCountFlag & AHBAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin @@ -548,6 +552,7 @@ module dcache STATE_UNCACHED_WRITE : begin DCacheStall = 1'b1; AHBWrite = 1'b1; + CommittedM = 1'b1; if(AHBAck) begin NextState = STATE_UNCACHED_WRITE_DONE; end else begin @@ -556,6 +561,7 @@ module dcache end STATE_UNCACHED_WRITE_DONE: begin + CommittedM = 1'b1; NextState = STATE_READY; end default: begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 9ed573a9..7a02ff2f 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -99,7 +99,9 @@ module lsu logic DTLBPageFaultM; logic MemAccessM; +/* -----\/----- EXCLUDED -----\/----- logic preCommittedM; + -----/\----- EXCLUDED -----/\----- */ typedef enum {STATE_READY, STATE_FETCH, @@ -135,7 +137,6 @@ module lsu logic [`XLEN-1:0] MemAdrEtoDCache; logic [`XLEN-1:0] ReadDataWfromDCache; logic StallWtoDCache; - logic CommittedMfromDCache; logic SquashSCWfromDCache; logic DataMisalignedMfromDCache; logic HPTWReady; @@ -187,7 +188,6 @@ module lsu .MemAdrM(MemAdrM), .StallW(StallW), .ReadDataW(ReadDataW), - .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), .LSUStall(LSUStall), @@ -198,7 +198,6 @@ module lsu .AtomicMtoDCache(AtomicMtoDCache), .MemAdrMtoDCache(MemAdrMtoDCache), .StallWtoDCache(StallWtoDCache), - .CommittedMfromDCache(CommittedMfromDCache), .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), @@ -319,6 +318,7 @@ module lsu .WriteDataM(WriteDataM), .ReadDataW(ReadDataWfromDCache), .DCacheStall(DCacheStall), + .CommittedM(CommittedM), .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 83ab93be..62d8b35a 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -45,7 +45,6 @@ module lsuArb input logic StallW, // to CPU output logic [`XLEN-1:0] ReadDataW, - output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, output logic LSUStall, @@ -58,7 +57,6 @@ module lsuArb output logic [`XLEN-1:0] MemAdrMtoDCache, output logic StallWtoDCache, // from LSU - input logic CommittedMfromDCache, input logic SquashSCWfromDCache, input logic DataMisalignedMfromDCache, input logic [`XLEN-1:0] ReadDataWfromDCache, @@ -149,7 +147,6 @@ module lsuArb assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux - assign CommittedM = SelPTW ? 1'b0 : CommittedMfromDCache; assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache; assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. From 9b756d6a94a250f2034fc0be0a8133909ee0b52e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 23:03:09 -0500 Subject: [PATCH 027/112] Implemented uncached reads. --- wally-pipelined/regression/wave.do | 4 +-- wally-pipelined/src/cache/dcache.sv | 42 +++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index f53880fd..f0bba807 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -401,7 +401,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} +WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -417,4 +417,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4642 ns} {4816 ns} +WaveRestoreZoom {5566 ns} {5750 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 9f2c0652..ba73f73a 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -90,7 +90,7 @@ module dcache logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; + logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM, ReadDataWordMuxM; logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; logic [BLOCKLEN-1:0] FinalWriteDataWordsM; logic [LOGWPL:0] FetchCount, NextFetchCount; @@ -111,6 +111,7 @@ module dcache logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic VictimDirty; logic SelAMOWrite; + logic SelUncached; logic [6:0] Funct7W; logic [2**LOGWPL-1:0] MemPAdrDecodedW; @@ -229,12 +230,18 @@ module dcache assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM; + mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), + .d1(DCacheMemWriteData[`XLEN-1:0]), + .s(SelUncached), + .y(ReadDataWordMuxM)); + // finally swr // *** BUG fix HSIZED? why was it this way? - subwordread subwordread(.HRDATA(ReadDataWordM), + subwordread subwordread(.HRDATA(ReadDataWordMuxM), .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HRDATAMasked(FinalReadDataWordM)); + flopen #(`XLEN) ReadDataWReg(.clk(clk), .en(~StallW), @@ -337,10 +344,10 @@ module dcache STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, STATE_PTW_MISS_WRITE_CACHE_BLOCK, STATE_PTW_MISS_READ_SRAM, - STATE_UNCACHED_WDV, - STATE_UNCACHED_DONE, STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, + STATE_UNCACHED_READ, + STATE_UNCACHED_READ_DONE, STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -393,6 +400,7 @@ module dcache AHBWrite = 1'b0; SelAMOWrite = 1'b0; CommittedM = 1'b0; + SelUncached = 1'b0; case (CurrState) STATE_READY: begin @@ -438,7 +446,13 @@ module dcache CntReset = 1'b1; DCacheStall = 1'b1; AHBWrite = 1'b1; - + end + // uncached read + else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_READ; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBRead = 1'b1; end // fault else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin @@ -560,10 +574,28 @@ module dcache end end + STATE_UNCACHED_READ : begin + DCacheStall = 1'b1; + AHBRead = 1'b1; + CommittedM = 1'b1; + if(AHBAck) begin + NextState = STATE_UNCACHED_READ_DONE; + end else begin + NextState = STATE_UNCACHED_READ; + end + end + STATE_UNCACHED_WRITE_DONE: begin CommittedM = 1'b1; NextState = STATE_READY; end + + STATE_UNCACHED_READ_DONE: begin + CommittedM = 1'b1; + SelUncached = 1'b1; + NextState = STATE_READY; + end + default: begin end endcase From f4295ff097674a55294b08c207a0fc428cc4d40a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 15:00:33 -0500 Subject: [PATCH 028/112] Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. This solves the committedM issue. --- wally-pipelined/src/cache/dcache.sv | 19 +++++---- wally-pipelined/src/lsu/lsu.sv | 5 ++- wally-pipelined/src/privileged/privileged.sv | 2 + wally-pipelined/src/privileged/trap.sv | 42 +++++++++++-------- .../src/wally/wallypipelinedhart.sv | 6 ++- 5 files changed, 45 insertions(+), 29 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index ba73f73a..0efbcf41 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -44,10 +44,11 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, output logic DCacheStall, - output logic CommittedM, + output logic CommittedM, // inputs from TLB and PMA/P - input logic FaultM, + input logic ExceptionM, + input logic PendingInterruptM, input logic DTLBMissM, input logic CacheableM, // ahb side @@ -409,7 +410,7 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit - else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; @@ -417,7 +418,7 @@ module dcache else NextState = STATE_READY; end // read hit valid cached - else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -425,7 +426,7 @@ module dcache else NextState = STATE_READY; end // write hit valid cached - else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin SelAdrM = 1'b1; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; @@ -435,27 +436,27 @@ module dcache else NextState = STATE_READY; end // read or write miss valid cached - else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; end // uncached write - else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin NextState = STATE_UNCACHED_WRITE; CntReset = 1'b1; DCacheStall = 1'b1; AHBWrite = 1'b1; end // uncached read - else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin NextState = STATE_UNCACHED_READ; CntReset = 1'b1; DCacheStall = 1'b1; AHBRead = 1'b1; end // fault - else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin + else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin NextState = STATE_READY; end else NextState = STATE_READY; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 7a02ff2f..71113fbd 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -40,6 +40,8 @@ module lsu input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic [1:0] AtomicM, + input logic ExceptionM, + input logic PendingInterruptM, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, @@ -319,7 +321,8 @@ module lsu .ReadDataW(ReadDataWfromDCache), .DCacheStall(DCacheStall), .CommittedM(CommittedM), - .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. + .ExceptionM(ExceptionM), + .PendingInterruptM(PendingInterruptM), .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index e80c0b85..fcc225db 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -64,6 +64,8 @@ module privileged ( input logic LoadAccessFaultM, input logic StoreAccessFaultM, + output logic ExceptionM, + output logic PendingInterruptM, output logic IllegalFPUInstrE, output logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] SATP_REGW, diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 9eec51c2..7462353d 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -27,23 +27,26 @@ `include "wally-config.vh" module trap ( - input logic clk, reset, - input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, - input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, - input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM, - input logic LoadPageFaultM, StorePageFaultM, - input logic mretM, sretM, uretM, - input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, - input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, - input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, - input logic STATUS_MIE, STATUS_SIE, - input logic [`XLEN-1:0] PCM, - input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, - input logic [31:0] InstrM, - input logic StallW, - input logic InstrValidM, CommittedM, - output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM, - output logic InterruptM, + input logic clk, reset, + input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, + input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, + input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM, + input logic LoadPageFaultM, StorePageFaultM, + input logic mretM, sretM, uretM, + input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, + input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, + input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, + input logic STATUS_MIE, STATUS_SIE, + input logic [`XLEN-1:0] PCM, + input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, + input logic [31:0] InstrM, + input logic StallW, + input logic InstrValidM, CommittedM, + output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM, + output logic InterruptM, + output logic ExceptionM, + output logic PendingInterruptM, + output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM @@ -59,7 +62,10 @@ module trap ( assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9 assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); - assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM; + assign PendingInterruptM = (|PendingIntsM) & InstrValidM; + assign InterruptM = PendingInterruptM & ~CommittedM; + assign ExceptionM = BusTrapM | NonBusTrapM; + // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 55c8959f..e0337bc3 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -161,6 +161,8 @@ module wallypipelinedhart logic InstrAccessFaultF; logic [2:0] DCtoAHBSizeM; + logic ExceptionM; + logic PendingInterruptM; ifu ifu(.InstrInF(InstrRData), @@ -179,7 +181,9 @@ module wallypipelinedhart .MemRWM(MemRWM), .Funct3M(Funct3M), .Funct7M(InstrM[31:25]), - .AtomicM(AtomicM), + .AtomicM(AtomicM), + .ExceptionM(ExceptionM), + .PendingInterruptM(PendingInterruptM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), From d78e31e9dfa23ad69b3cc90b7f0ae19cb92c3cba Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 15:46:52 -0500 Subject: [PATCH 029/112] Forgot to include one hot decoder. --- wally-pipelined/src/generic/oneHotDecoder.sv | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 wally-pipelined/src/generic/oneHotDecoder.sv diff --git a/wally-pipelined/src/generic/oneHotDecoder.sv b/wally-pipelined/src/generic/oneHotDecoder.sv new file mode 100644 index 00000000..08bd2e01 --- /dev/null +++ b/wally-pipelined/src/generic/oneHotDecoder.sv @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// oneHotDecoder.sv +// +// Written: ross1728@gmail.com July 09, 2021 +// Modified: +// +// Purpose: Bin to one hot decoder. Power of 2 only. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module oneHotDecoder + #(parameter WIDTH = 2) + (input logic [WIDTH-1:0] bin, + output logic [2**WIDTH-1:0] decoded + ); + + always_comb begin + decoded = '0; + decoded[bin] = 1'b1; + end + +endmodule From adce8000419aea73340c34cd3509ac42f07d3db9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 15:47:38 -0500 Subject: [PATCH 030/112] Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. --- wally-pipelined/src/cache/dcache.sv | 97 ++++++++++++++++------------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 0efbcf41..b7665fa8 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -121,6 +121,50 @@ module dcache logic [`PA_BITS-1:0] BasePAdrMaskedM; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; + + logic ReadDataWEn; + + logic AnyCPUReqM; + logic FetchCountFlag; + logic PreCntEn; + logic CntEn; + logic CntReset; + logic CPUBusy, PreviousCPUBusy; + + + typedef enum {STATE_READY, + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_EVICT_DIRTY, + STATE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_MISS_WRITE_CACHE_BLOCK, + STATE_MISS_READ_WORD, + STATE_MISS_READ_WORD_DELAY, + STATE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_CHECK_EVICTED_DIRTY, + STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_AMO_MISS_WRITE_CACHE_BLOCK, + STATE_AMO_MISS_READ_WORD, + STATE_AMO_MISS_UPDATE_WORD, + STATE_AMO_MISS_WRITE_WORD, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_PTW_READY, + STATE_PTW_MISS_FETCH_WDV, + STATE_PTW_MISS_FETCH_DONE, + STATE_PTW_MISS_CHECK_EVICTED_DIRTY, + STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_PTW_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_MISS_READ_SRAM, + STATE_UNCACHED_WRITE, + STATE_UNCACHED_WRITE_DONE, + STATE_UNCACHED_READ, + STATE_UNCACHED_READ_DONE, + STATE_CPU_BUSY} statetype; + + statetype CurrState, NextState; flopenr #(7) Funct7WReg(.clk(clk), @@ -242,10 +286,19 @@ module dcache .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HRDATAMasked(FinalReadDataWordM)); - + // This is a confusing point. + // The final read data should be updated only if the CPU's StallW is low + // which means the CPU is ready to take data. Or if the CPU just became + // busy. Then when we exit CPU_BUSY we want to ensure the data is not + // updated, this is ~PreviousCPUBusy. + assign CPUBusy = CurrState == STATE_CPU_BUSY; + flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy)); + + assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | (NextState == STATE_CPU_BUSY & CurrState == STATE_READY); + flopen #(`XLEN) ReadDataWReg(.clk(clk), - .en(~StallW), + .en(ReadDataWEn), .d(FinalReadDataWordM), .q(ReadDataW)); @@ -312,46 +365,6 @@ module dcache // control path *** eventually move to own module. - logic AnyCPUReqM; - logic FetchCountFlag; - logic PreCntEn; - logic CntEn; - logic CntReset; - - - typedef enum {STATE_READY, - STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, - STATE_MISS_EVICT_DIRTY, - STATE_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_MISS_WRITE_CACHE_BLOCK, - STATE_MISS_READ_WORD, - STATE_MISS_READ_WORD_DELAY, - STATE_MISS_WRITE_WORD, - STATE_AMO_MISS_FETCH_WDV, - STATE_AMO_MISS_FETCH_DONE, - STATE_AMO_MISS_CHECK_EVICTED_DIRTY, - STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_AMO_MISS_WRITE_CACHE_BLOCK, - STATE_AMO_MISS_READ_WORD, - STATE_AMO_MISS_UPDATE_WORD, - STATE_AMO_MISS_WRITE_WORD, - STATE_AMO_UPDATE, - STATE_AMO_WRITE, - STATE_PTW_READY, - STATE_PTW_MISS_FETCH_WDV, - STATE_PTW_MISS_FETCH_DONE, - STATE_PTW_MISS_CHECK_EVICTED_DIRTY, - STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_PTW_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_MISS_READ_SRAM, - STATE_UNCACHED_WRITE, - STATE_UNCACHED_WRITE_DONE, - STATE_UNCACHED_READ, - STATE_UNCACHED_READ_DONE, - STATE_CPU_BUSY} statetype; - - statetype CurrState, NextState; localparam FetchCountThreshold = WORDSPERLINE - 1; From e91501985cc00ac3b4e6176b127065eb1c19ad1f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 16:18:09 -0500 Subject: [PATCH 031/112] Routed CommittedM and PendingInterruptM through the lsu arb. --- wally-pipelined/regression/wave.do | 147 ++++++++++-------- wally-pipelined/src/lsu/lsu.sv | 12 +- wally-pipelined/src/lsu/lsuArb.sv | 24 +-- .../testbench/testbench-imperas.sv | 4 +- 4 files changed, 102 insertions(+), 85 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index f0bba807..e34eb866 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,44 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -130,6 +137,7 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -147,12 +155,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/hart/PCF -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/hart/PCE -add wave -noupdate -group PCS /testbench/dut/hart/PCM -add wave -noupdate -group PCS /testbench/PCW +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE @@ -239,22 +247,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM @@ -278,6 +286,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW @@ -333,20 +342,20 @@ add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPi add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead @@ -401,7 +410,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} +WaveRestoreCursors {{Cursor 12} {718836 ns} 0} {{Cursor 4} {8790617 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -417,4 +426,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {5566 ns} {5750 ns} +WaveRestoreZoom {718645 ns} {719057 ns} diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 71113fbd..882c2dcd 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -146,6 +146,10 @@ module lsu logic DCacheStall; logic CacheableM; + + logic CommittedMfromDCache; + logic PendingInterruptMtoDCache; + pagetablewalker pagetablewalker( .clk(clk), @@ -188,6 +192,8 @@ module lsu .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), + .CommittedM(CommittedM), + .PendingInterruptM(PendingInterruptM), .StallW(StallW), .ReadDataW(ReadDataW), .SquashSCW(SquashSCW), @@ -203,6 +209,8 @@ module lsu .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), + .CommittedMfromDCache(CommittedMfromDCache), + .PendingInterruptMtoDCache(PendingInterruptMtoDCache), .DCacheStall(DCacheStall)); @@ -320,9 +328,9 @@ module lsu .WriteDataM(WriteDataM), .ReadDataW(ReadDataWfromDCache), .DCacheStall(DCacheStall), - .CommittedM(CommittedM), + .CommittedM(CommittedMfromDCache), .ExceptionM(ExceptionM), - .PendingInterruptM(PendingInterruptM), + .PendingInterruptM(PendingInterruptMtoDCache), .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 62d8b35a..08024d0b 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -43,20 +43,25 @@ module lsuArb input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrM, input logic StallW, + input logic PendingInterruptM, // to CPU output logic [`XLEN-1:0] ReadDataW, output logic SquashSCW, output logic DataMisalignedM, + output logic CommittedM, output logic LSUStall, - // to LSU + // to D Cache output logic DisableTranslation, output logic [1:0] MemRWMtoDCache, output logic [2:0] Funct3MtoDCache, output logic [1:0] AtomicMtoDCache, output logic [`XLEN-1:0] MemAdrMtoDCache, output logic StallWtoDCache, - // from LSU + output logic PendingInterruptMtoDCache, + + // from D Cache + input logic CommittedMfromDCache, input logic SquashSCWfromDCache, input logic DataMisalignedMfromDCache, input logic [`XLEN-1:0] ReadDataWfromDCache, @@ -82,7 +87,6 @@ module lsuArb statetype CurrState, NextState; logic SelPTW; - logic HPTWStallD; logic [2:0] PTWSize; @@ -142,6 +146,8 @@ module lsuArb assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; assign StallWtoDCache = SelPTW ? 1'b0 : StallW; + // always block interrupts when using the hardware page table walker. + assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; // demux the inputs from LSU to walker or cpu's data port. @@ -153,15 +159,9 @@ module lsuArb // not clear at all. I think it should be LSUStall from the LSU, // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one). assign HPTWStall = SelPTW ? DCacheStall : 1'b1; - //assign HPTWStallD = SelPTW ? DataStall : 1'b1; -/* -----\/----- EXCLUDED -----\/----- - assign HPTWStallD = SelPTW ? DataStall : 1'b1; - flopr #(1) HPTWStallReg (.clk(clk), - .reset(reset), - .d(HPTWStallD), - .q(HPTWStall)); - -----/\----- EXCLUDED -----/\----- */ - + + assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM; + assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change. endmodule diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 654c34fb..d2cd6dcb 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -539,11 +539,11 @@ string tests32f[] = '{ else if (TESTSPRIV) tests = tests64p; else begin - tests = {tests64p,tests64i,tests64periph}; + tests = {tests64p,tests64i}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; - if (`A_SUPPORTED) tests = {tests, tests64a}; + //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; From 2c946a282f83282457ad67af958637290d3c7e2a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 17:23:28 -0500 Subject: [PATCH 032/112] Fixed d cache not honoring StallW for uncache writes and reads. --- wally-pipelined/regression/wave.do | 123 ++++++++---------- wally-pipelined/src/cache/dcache.sv | 97 +++++++++++--- wally-pipelined/src/lsu/lsu.sv | 1 + .../testbench/testbench-imperas.sv | 2 +- 4 files changed, 138 insertions(+), 85 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index e34eb866..bda6f414 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,10 +7,10 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM @@ -27,14 +27,14 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -306,15 +306,10 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/ReadDataW -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/WriteDataM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/StallW -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/LSUStall +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -328,34 +323,34 @@ add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead @@ -370,12 +365,12 @@ add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/ add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -expand -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE +add wave -noupdate -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -399,18 +394,14 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate /testbench/dut/uncore/dtim/HWADDR -add wave -noupdate /testbench/dut/uncore/dtim/A -add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim -add wave -noupdate /testbench/dut/uncore/dtim/memwrite -add wave -noupdate /testbench/dut/uncore/dtim/HWDATA +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HCLK +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HSELUART +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HADDR +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWRITE +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {718836 ns} 0} {{Cursor 4} {8790617 ns} 0} +WaveRestoreCursors {{Cursor 12} {4076 ns} 0} {{Cursor 4} {8790617 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -426,4 +417,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {718645 ns} {719057 ns} +WaveRestoreZoom {4026 ns} {4254 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index b7665fa8..3397bedb 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -48,9 +48,10 @@ module dcache // inputs from TLB and PMA/P input logic ExceptionM, - input logic PendingInterruptM, + input logic PendingInterruptM, input logic DTLBMissM, input logic CacheableM, + input logic DTLBWriteM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -133,6 +134,7 @@ module dcache typedef enum {STATE_READY, + STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_DONE, STATE_MISS_EVICT_DIRTY, @@ -141,6 +143,7 @@ module dcache STATE_MISS_READ_WORD, STATE_MISS_READ_WORD_DELAY, STATE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, STATE_AMO_MISS_FETCH_DONE, STATE_AMO_MISS_CHECK_EVICTED_DIRTY, @@ -151,17 +154,19 @@ module dcache STATE_AMO_MISS_WRITE_WORD, STATE_AMO_UPDATE, STATE_AMO_WRITE, + STATE_PTW_READY, - STATE_PTW_MISS_FETCH_WDV, - STATE_PTW_MISS_FETCH_DONE, - STATE_PTW_MISS_CHECK_EVICTED_DIRTY, - STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_PTW_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_MISS_READ_SRAM, + STATE_PTW_READ_MISS_FETCH_WDV, + STATE_PTW_READ_MISS_FETCH_DONE, + STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_READ_MISS_READ_WORD, + STATE_PTW_READ_MISS_READ_WORD_DELAY, + STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, STATE_UNCACHED_READ, STATE_UNCACHED_READ_DONE, + STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -420,7 +425,7 @@ module dcache STATE_READY: begin // TLB Miss if(AnyCPUReqM & DTLBMissM) begin - NextState = STATE_PTW_MISS_FETCH_WDV; + NextState = STATE_PTW_READY; end // amo hit else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin @@ -428,11 +433,10 @@ module dcache DCacheStall = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; + else NextState = STATE_AMO_UPDATE; end // read hit valid cached else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - NextState = STATE_READY; DCacheStall = 1'b0; if(StallW) NextState = STATE_CPU_BUSY; @@ -562,14 +566,69 @@ module dcache end end - STATE_PTW_MISS_FETCH_WDV: begin + STATE_PTW_READY: begin + CommittedM = 1'b1; + // return to ready if page table walk completed. + if(DTLBWriteM) begin + NextState = STATE_READY; + + // read hit valid cached + end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin + NextState = STATE_PTW_READY; + DCacheStall = 1'b0; + end + + // read miss valid cached + else if((MemRWM[1]) & CacheableM & ~ExceptionM & ~CacheHit) begin + NextState = STATE_PTW_READ_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end + end + + STATE_PTW_READ_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + AHBRead = 1'b1; + SelAdrM = 1'b1; + CommittedM = 1'b1; + + if (FetchCountFlag & AHBAck) begin + NextState = STATE_PTW_READ_MISS_FETCH_DONE; + end else begin + NextState = STATE_PTW_READ_MISS_FETCH_WDV; + end + end + + STATE_PTW_READ_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 1'b1; - if (FetchCountFlag & AHBAck) begin - NextState = STATE_PTW_MISS_FETCH_DONE; - end else begin - NextState = STATE_PTW_MISS_FETCH_WDV; - end + CntReset = 1'b1; + CommittedM = 1'b1; + NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK; + end + + STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin + SRAMBlockWriteEnableM = 1'b1; + DCacheStall = 1'b1; + NextState = STATE_PTW_READ_MISS_READ_WORD; + SelAdrM = 1'b1; + SetValidM = 1'b1; + ClearDirtyM = 1'b1; + CommittedM = 1'b1; + end + + STATE_PTW_READ_MISS_READ_WORD: begin + SelAdrM = 1'b1; + DCacheStall = 1'b1; + CommittedM = 1'b1; + NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY; + end + + STATE_PTW_READ_MISS_READ_WORD_DELAY: begin + SelAdrM = 1'b1; + NextState = STATE_PTW_READY; + CommittedM = 1'b1; end STATE_CPU_BUSY : begin @@ -601,13 +660,15 @@ module dcache STATE_UNCACHED_WRITE_DONE: begin CommittedM = 1'b1; - NextState = STATE_READY; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_UNCACHED_READ_DONE: begin CommittedM = 1'b1; SelUncached = 1'b1; - NextState = STATE_READY; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end default: begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 882c2dcd..8f739822 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -333,6 +333,7 @@ module lsu .PendingInterruptM(PendingInterruptMtoDCache), .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), + .DTLBWriteM(DTLBWriteM), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index d2cd6dcb..56a019e8 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -544,9 +544,9 @@ string tests32f[] = '{ else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; //if (`A_SUPPORTED) tests = {tests, tests64a}; - if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; + if (`MEM_VIRTMEM) tests = {tests64periph, tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From c79650b5086dda1190a67d7f8d01fe15bc6dd01e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 17:25:50 -0500 Subject: [PATCH 033/112] Added d cache StallW checks for any time the cache wants to go to STATE_READY. --- wally-pipelined/src/cache/dcache.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3397bedb..a22c5d9b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -485,8 +485,9 @@ module dcache SRAMWordWriteEnableM = 1'b1; // pipelined 1 cycle end STATE_AMO_WRITE: begin - NextState = STATE_READY; SelAMOWrite = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_MISS_FETCH_WDV: begin @@ -540,17 +541,19 @@ module dcache STATE_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; - NextState = STATE_READY; CommittedM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_MISS_WRITE_WORD: begin SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; SelAdrM = 1'b1; - NextState = STATE_READY; DCacheStall = 1'b0; CommittedM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_MISS_EVICT_DIRTY: begin From ba1e1ec2316e962ee0940276fb37474ddacfbee6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 22:26:07 -0500 Subject: [PATCH 034/112] Finally have the ptw correctly walking through the dcache to update the itlb. Still not working fully. --- wally-pipelined/regression/wave.do | 179 ++-- wally-pipelined/src/cache/dcache.sv | 14 +- wally-pipelined/src/lsu/lsu.sv | 45 +- wally-pipelined/src/lsu/lsuArb.sv | 19 +- wally-pipelined/src/mmu/pagetablewalker.sv | 784 +++++++++--------- .../testbench/testbench-imperas.sv | 2 +- 6 files changed, 551 insertions(+), 492 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index bda6f414..4205be70 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -3,48 +3,49 @@ quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename +add wave -noupdate /testbench/dut/hart/SATP_REGW add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -112,7 +113,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 @@ -155,12 +156,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/hart/PCF +add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/hart/PCE +add wave -noupdate -group PCS /testbench/dut/hart/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE @@ -239,6 +240,12 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrE +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrE +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrMtoDCache +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrEtoDCache add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM @@ -271,18 +278,23 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall @@ -297,6 +309,9 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed @@ -306,6 +321,10 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress @@ -351,26 +370,28 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -group ptwalker -divider data -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE +add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM +add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group ptwalker -divider data +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM +add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM +add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -395,13 +416,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HCLK -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HSELUART -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HADDR -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWRITE -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWDATA +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA +add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN +add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {4076 ns} 0} {{Cursor 4} {8790617 ns} 0} +WaveRestoreCursors {{Cursor 3} {21755 ns} 0} {{Cursor 4} {15501 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -417,4 +440,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4026 ns} {4254 ns} +WaveRestoreZoom {21597 ns} {21891 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index a22c5d9b..b0ac3328 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -43,6 +43,7 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, + output logic [`XLEN-1:0] ReadDataM, output logic DCacheStall, output logic CommittedM, @@ -131,6 +132,7 @@ module dcache logic CntEn; logic CntReset; logic CPUBusy, PreviousCPUBusy; + logic SelEvict; typedef enum {STATE_READY, @@ -297,16 +299,22 @@ module dcache // which means the CPU is ready to take data. Or if the CPU just became // busy. Then when we exit CPU_BUSY we want to ensure the data is not // updated, this is ~PreviousCPUBusy. + // also must update if cpu stalled and processing a read miss + // which occurs if in state miss read word delay. assign CPUBusy = CurrState == STATE_CPU_BUSY; flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy)); - assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | (NextState == STATE_CPU_BUSY & CurrState == STATE_READY); + assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | + (NextState == STATE_CPU_BUSY & CurrState == STATE_READY) | + (CurrState == STATE_MISS_READ_WORD_DELAY); flopen #(`XLEN) ReadDataWReg(.clk(clk), .en(ReadDataWEn), .d(FinalReadDataWordM), .q(ReadDataW)); + assign ReadDataM = FinalReadDataWordM; + // write path subwordwrite subwordwrite(.HRDATA(ReadDataWordM), .HADDRD(MemPAdrM[2:0]), @@ -340,7 +348,7 @@ module dcache // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .s(AHBWrite & CacheableM), + .s(SelEvict), .y(BasePAdrM)); assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; @@ -420,6 +428,7 @@ module dcache SelAMOWrite = 1'b0; CommittedM = 1'b0; SelUncached = 1'b0; + SelEvict = 1'b0; case (CurrState) STATE_READY: begin @@ -562,6 +571,7 @@ module dcache AHBWrite = 1'b1; SelAdrM = 1'b1; CommittedM = 1'b1; + SelEvict = 1'b1; if( FetchCountFlag & AHBAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 8f739822..f8fa87a0 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -129,9 +129,10 @@ module lsu logic [`XLEN-1:0] HPTWReadPTE; logic MMUReady; logic HPTWStall; - logic [`XLEN-1:0] HPTWPAdr; + logic [`XLEN-1:0] HPTWPAdrE; + logic [`XLEN-1:0] HPTWPAdrM; logic HPTWTranslate; - logic HPTWRead; + logic HPTWReadM; logic [1:0] MemRWMtoDCache; logic [2:0] Funct3MtoDCache; logic [1:0] AtomicMtoDCache; @@ -146,6 +147,8 @@ module lsu logic DCacheStall; logic CacheableM; + logic CacheableMtoDCache; + logic SelPTW; logic CommittedMfromDCache; logic PendingInterruptMtoDCache; @@ -169,9 +172,10 @@ module lsu .HPTWReadPTE(HPTWReadPTE), .MMUReady(HPTWReady), .HPTWStall(HPTWStall), - .HPTWPAdr(HPTWPAdr), + .HPTWPAdrE(HPTWPAdrE), + .HPTWPAdrM(HPTWPAdrM), .HPTWTranslate(HPTWTranslate), - .HPTWRead(HPTWRead), + .HPTWReadM(HPTWReadM), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM)); @@ -183,15 +187,17 @@ module lsu .reset(reset), // HPTW connection .HPTWTranslate(HPTWTranslate), - .HPTWRead(HPTWRead), - .HPTWPAdr(HPTWPAdr), - .HPTWReadPTE(HPTWReadPTE), + .HPTWReadM(HPTWReadM), + .HPTWPAdrE(HPTWPAdrE), + .HPTWPAdrM(HPTWPAdrM), + //.HPTWReadPTE(HPTWReadPTE), .HPTWStall(HPTWStall), // CPU connection .MemRWM(MemRWM), .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), + .MemAdrE(MemAdrE), .CommittedM(CommittedM), .PendingInterruptM(PendingInterruptM), .StallW(StallW), @@ -204,14 +210,16 @@ module lsu .MemRWMtoDCache(MemRWMtoDCache), .Funct3MtoDCache(Funct3MtoDCache), .AtomicMtoDCache(AtomicMtoDCache), - .MemAdrMtoDCache(MemAdrMtoDCache), + .MemAdrMtoDCache(MemAdrMtoDCache), + .MemAdrEtoDCache(MemAdrEtoDCache), .StallWtoDCache(StallWtoDCache), .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), .CommittedMfromDCache(CommittedMfromDCache), .PendingInterruptMtoDCache(PendingInterruptMtoDCache), - .DCacheStall(DCacheStall)); + .DCacheStall(DCacheStall), + .SelPTW(SelPTW)); mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) @@ -239,10 +247,10 @@ module lsu // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? - + assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM; generate - if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache; - else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache; + if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache; + else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache; endgenerate; @@ -309,30 +317,27 @@ module lsu assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; - // *** BUG - assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb. - - dcache dcache(.clk(clk), .reset(reset), .StallM(StallM), - .StallW(StallW), + .StallW(StallWtoDCache), .FlushM(FlushM), - .FlushW(FlushW), + .FlushW(FlushWtoDCache), .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), .AtomicM(AtomicMtoDCache), - .MemAdrE(MemAdrEtoDCache), // *** add to arb + .MemAdrE(MemAdrEtoDCache), .MemPAdrM(MemPAdrM), .WriteDataM(WriteDataM), .ReadDataW(ReadDataWfromDCache), + .ReadDataM(HPTWReadPTE), .DCacheStall(DCacheStall), .CommittedM(CommittedMfromDCache), .ExceptionM(ExceptionM), .PendingInterruptM(PendingInterruptMtoDCache), .DTLBMissM(DTLBMissM), - .CacheableM(CacheableM), + .CacheableM(CacheableMtoDCache), .DTLBWriteM(DTLBWriteM), // AHB connection diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 08024d0b..3b3ad94f 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -31,10 +31,11 @@ module lsuArb // from page table walker input logic HPTWTranslate, - input logic HPTWRead, - input logic [`XLEN-1:0] HPTWPAdr, + input logic HPTWReadM, + input logic [`XLEN-1:0] HPTWPAdrE, + input logic [`XLEN-1:0] HPTWPAdrM, // to page table walker. - output logic [`XLEN-1:0] HPTWReadPTE, + //output logic [`XLEN-1:0] HPTWReadPTE, output logic HPTWStall, // from CPU @@ -42,6 +43,7 @@ module lsuArb input logic [2:0] Funct3M, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrM, + input logic [`XLEN-1:0] MemAdrE, input logic StallW, input logic PendingInterruptM, // to CPU @@ -57,8 +59,11 @@ module lsuArb output logic [2:0] Funct3MtoDCache, output logic [1:0] AtomicMtoDCache, output logic [`XLEN-1:0] MemAdrMtoDCache, + output logic [`XLEN-1:0] MemAdrEtoDCache, output logic StallWtoDCache, output logic PendingInterruptMtoDCache, + output logic SelPTW, + // from D Cache input logic CommittedMfromDCache, @@ -86,7 +91,6 @@ module lsuArb statetype CurrState, NextState; - logic SelPTW; logic [2:0] PTWSize; @@ -136,7 +140,7 @@ module lsuArb // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate); - assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM; + assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM; generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw @@ -144,7 +148,8 @@ module lsuArb mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache); assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; - assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; + assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM; + assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE; assign StallWtoDCache = SelPTW ? 1'b0 : StallW; // always block interrupts when using the hardware page table walker. assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; @@ -152,7 +157,7 @@ module lsuArb // demux the inputs from LSU to walker or cpu's data port. assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux - assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux + //assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache; assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 83d15f9b..334ef2b2 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -59,9 +59,10 @@ module pagetablewalker input logic HPTWStall, // *** modify to send to LSU - output logic [`XLEN-1:0] HPTWPAdr, // this probalby should be `PA_BITS wide + output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide + output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide output logic HPTWTranslate, // *** rename to HPTWReq - output logic HPTWRead, + output logic HPTWReadM, // Faults @@ -70,52 +71,63 @@ module pagetablewalker output logic WalkerStorePageFaultM ); + logic HPTWReadE; + generate if (`MEM_VIRTMEM) begin // Internal signals // register TLBs translation miss requests logic [`XLEN-1:0] TranslationVAdrQ; - logic ITLBMissFQ, DTLBMissMQ; + logic ITLBMissFQ, DTLBMissMQ; - logic [`PPN_BITS-1:0] BasePageTablePPN; + logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`XLEN-1:0] TranslationVAdr; logic [`XLEN-1:0] SavedPTE, CurrentPTE; logic [`PA_BITS-1:0] TranslationPAdr; - logic [`PPN_BITS-1:0] CurrentPPN; - logic [`SVMODE_BITS-1:0] SvMode; - logic MemStore; + logic [`PPN_BITS-1:0] CurrentPPN; + logic [`SVMODE_BITS-1:0] SvMode; + logic MemStore; // PTE Control Bits - logic Dirty, Accessed, Global, User, - Executable, Writable, Readable, Valid; + logic Dirty, Accessed, Global, User, + Executable, Writable, Readable, Valid; // PTE descriptions - logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; + logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; // Outputs of walker logic [`XLEN-1:0] PageTableEntry; logic [1:0] PageType; - logic StartWalk; - logic EndWalk; + logic StartWalk; + logic EndWalk; typedef enum {LEVEL0_WDV, - LEVEL0, - LEVEL1_WDV, - LEVEL1, - LEVEL2_WDV, - LEVEL2, - LEVEL3_WDV, - LEVEL3, - LEAF, - IDLE, - START, - FAULT} statetype; + LEVEL0, + LEVEL1_WDV, + LEVEL1, + LEVEL2_WDV, + LEVEL2, + LEVEL3_WDV, + LEVEL3, + LEAF, + IDLE, + START, + FAULT} statetype; statetype WalkerState, NextWalkerState; - logic PRegEn; - logic SelDataTranslation; + logic PRegEn; + logic SelDataTranslation; + flop #(`XLEN) HPTWPAdrMReg(.clk(clk), + .d(HPTWPAdrE), + .q(HPTWPAdrM)); + + flop #(1) HPTWReadMReg(.clk(clk), + .d(HPTWReadE), + .q(HPTWReadM)); + + assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; @@ -128,35 +140,35 @@ module pagetablewalker flopenr #(`XLEN) TranslationVAdrReg(.clk(clk), - .reset(reset), - .en(StartWalk), - .d(TranslationVAdr), - .q(TranslationVAdrQ)); + .reset(reset), + .en(StartWalk), + .d(TranslationVAdr), + .q(TranslationVAdrQ)); flopenrc #(1) DTLBMissMReg(.clk(clk), - .reset(reset), - .en(StartWalk | EndWalk), - .clear(EndWalk), - .d(DTLBMissM), - .q(DTLBMissMQ)); + .reset(reset), + .en(StartWalk | EndWalk), + .clear(EndWalk), + .d(DTLBMissM), + .q(DTLBMissMQ)); flopenrc #(1) ITLBMissMReg(.clk(clk), - .reset(reset), - .en(StartWalk | EndWalk), - .clear(EndWalk), - .d(ITLBMissF), - .q(ITLBMissFQ)); + .reset(reset), + .en(StartWalk | EndWalk), + .clear(EndWalk), + .d(ITLBMissF), + .q(ITLBMissFQ)); assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); assign EndWalk = WalkerState == LEAF || - //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == FAULT); + //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == FAULT); assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; //assign HPTWTranslate = DTLBMissM | ITLBMissF; @@ -177,385 +189,389 @@ module pagetablewalker assign PageTypeM = PageType; -// generate - if (`XLEN == 32) begin - logic [9:0] VPN1, VPN0; + // generate + if (`XLEN == 32) begin + logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ + /* -----\/----- EXCLUDED -----\/----- + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; + -----/\----- EXCLUDED -----/\----- */ - // State transition logic - always_comb begin - PRegEn = 1'b0; - TranslationPAdr = '0; - HPTWRead = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; + // State transition logic + always_comb begin + PRegEn = 1'b0; + TranslationPAdr = '0; + HPTWReadE = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - case (WalkerState) - IDLE: begin - if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end + case (WalkerState) + IDLE: begin + if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode + NextWalkerState = START; + end else begin + NextWalkerState = IDLE; + end + end - START: begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWRead = 1'b1; - end - - LEVEL1_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; - end - end - - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]}; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end - - LEVEL0_WDV: begin + START: begin + NextWalkerState = LEVEL1_WDV; + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + HPTWReadE = 1'b1; + end + + LEVEL1_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; + PRegEn = 1'b1; + end + end + + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_WDV; TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; - end + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; + end + end + + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL0_WDV; + end else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; + end + end + + LEVEL0: begin + if (ValidPTE & LeafPTE & ~AccessAlert) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end else begin + NextWalkerState = FAULT; + end + end + + LEAF: begin + NextWalkerState = IDLE; + end + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end + + // Default case should never happen, but is included for linter. + default: NextWalkerState = IDLE; + endcase end - LEVEL0: begin - if (ValidPTE & LeafPTE & ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]}; - end else begin - NextWalkerState = FAULT; - end - end + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[9:0]); + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + + assign VPN1 = TranslationVAdr[31:22]; + assign VPN0 = TranslationVAdr[21:12]; + - LEAF: begin - NextWalkerState = IDLE; - end - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end + + // Capture page table entry from data cache + // *** may need to delay reading this value until the next clock cycle. + // The clk to q latency of the SRAM in the data cache will be long. + // I cannot see directly using this value. This is no different than + // a load delay hazard. This will require rewriting the walker fsm. + // also need a new signal to save. Should be a mealy output of the fsm + // request followed by ~stall. + flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + + // Assign outputs to ahblite + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = TranslationPAdr[31:0]; + + end else begin - // Default case should never happen, but is included for linter. - default: NextWalkerState = IDLE; - endcase - end + logic [8:0] VPN3, VPN2, VPN1, VPN0; - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[9:0]); - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - assign VPN1 = TranslationVAdrQ[31:22]; - assign VPN0 = TranslationVAdrQ[21:12]; + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - + /* -----\/----- EXCLUDED -----\/----- + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || + WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; + -----/\----- EXCLUDED -----/\----- */ - // Capture page table entry from data cache - // *** may need to delay reading this value until the next clock cycle. - // The clk to q latency of the SRAM in the data cache will be long. - // I cannot see directly using this value. This is no different than - // a load delay hazard. This will require rewriting the walker fsm. - // also need a new signal to save. Should be a mealy output of the fsm - // request followed by ~stall. - flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || + // WalkerState == LEVEL2 || WalkerState == LEVEL1; + - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdr = TranslationPAdr[31:0]; + always_comb begin + PRegEn = 1'b0; + TranslationPAdr = '0; + HPTWReadE = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - end else begin - - logic [8:0] VPN3, VPN2, VPN1, VPN0; + case (WalkerState) + IDLE: begin + if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin + NextWalkerState = START; + end else begin + NextWalkerState = IDLE; + end + end - logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || - WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ - - //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || - // WalkerState == LEVEL2 || WalkerState == LEVEL1; - - - always_comb begin - PRegEn = 1'b0; - TranslationPAdr = '0; - HPTWRead = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; - - case (WalkerState) - IDLE: begin - if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end - - START: begin - if (HPTWTranslate && SvMode == `SV48) begin - NextWalkerState = LEVEL3_WDV; - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWRead = 1'b1; - end else if (HPTWTranslate && SvMode == `SV39) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; - HPTWRead = 1'b1; - end else begin // *** should not get here - NextWalkerState = IDLE; - TranslationPAdr = '0; - end - end - - LEVEL3_WDV: begin + START: begin + if (HPTWTranslate && SvMode == `SV48) begin + NextWalkerState = LEVEL3_WDV; TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - if (HPTWStall) begin - NextWalkerState = LEVEL3_WDV; - end else begin - NextWalkerState = LEVEL3; - PRegEn = 1'b1; - end - end - - LEVEL3: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadTerapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - + HPTWReadE = 1'b1; + end else if (HPTWTranslate && SvMode == `SV39) begin + NextWalkerState = LEVEL2_WDV; + TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; + HPTWReadE = 1'b1; + end else begin // *** should not get here + NextWalkerState = IDLE; + TranslationPAdr = '0; end + end - LEVEL2_WDV: begin + LEVEL3_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL3_WDV; + end else begin + NextWalkerState = LEVEL3; + PRegEn = 1'b1; + end + end + + LEVEL3: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadTerapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL2_WDV; TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - //HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL2_WDV; - end else begin - NextWalkerState = LEVEL2; - PRegEn = 1'b1; - end - end - - LEVEL2: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadGigapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; end - LEVEL1_WDV: begin + end + + LEVEL2_WDV: begin + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL2_WDV; + end else begin + NextWalkerState = LEVEL2; + PRegEn = 1'b1; + end + end + + LEVEL2: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadGigapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL1_WDV; TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - //HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; - end + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; end - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end + end - LEVEL0_WDV: begin + LEVEL1_WDV: begin + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; + PRegEn = 1'b1; + end + end + + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_WDV; TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; - end + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; end + end - LEVEL0: begin - if (ValidPTE && LeafPTE && ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - end else begin - NextWalkerState = FAULT; - end + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL0_WDV; + end else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; end - - LEAF: begin - NextWalkerState = IDLE; + end + + LEVEL0: begin + if (ValidPTE && LeafPTE && ~AccessAlert) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end else begin + NextWalkerState = FAULT; end + end + + LEAF: begin + NextWalkerState = IDLE; + end - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end - // Default case should never happen - default: begin - NextWalkerState = IDLE; - end + // Default case should never happen + default: begin + NextWalkerState = IDLE; + end - endcase - end - - // A terapage is a level 3 leaf page. This page must have zero PPN[2], - // zero PPN[1], and zero PPN[0] - assign TerapageMisaligned = |(CurrentPPN[26:0]); - // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and - // zero PPN[0] - assign GigapageMisaligned = |(CurrentPPN[17:0]); - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[8:0]); - - assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - - assign VPN3 = TranslationVAdrQ[47:39]; - assign VPN2 = TranslationVAdrQ[38:30]; - assign VPN1 = TranslationVAdrQ[29:21]; - assign VPN0 = TranslationVAdrQ[20:12]; - - - // Capture page table entry from ahblite - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + endcase end + + // A terapage is a level 3 leaf page. This page must have zero PPN[2], + // zero PPN[1], and zero PPN[0] + assign TerapageMisaligned = |(CurrentPPN[26:0]); + // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and + // zero PPN[0] + assign GigapageMisaligned = |(CurrentPPN[17:0]); + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[8:0]); + + assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + + assign VPN3 = TranslationVAdr[47:39]; + assign VPN2 = TranslationVAdr[38:30]; + assign VPN1 = TranslationVAdr[29:21]; + assign VPN0 = TranslationVAdr[20:12]; + + + // Capture page table entry from ahblite + flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + + // Assign outputs to ahblite + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + end //endgenerate end else begin - assign HPTWPAdr = 0; + assign HPTWPAdrE = 0; assign HPTWTranslate = 0; - assign HPTWRead = 0; + assign HPTWReadE = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 56a019e8..b33b9ca4 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -546,7 +546,7 @@ string tests32f[] = '{ //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - if (`MEM_VIRTMEM) tests = {tests64periph, tests64mmu, tests}; + if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From 704f4f724e5230d6ab01cdd5adbbb6b51ea6bfbc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 23:08:07 -0500 Subject: [PATCH 035/112] dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. --- wally-pipelined/regression/wave.do | 131 +++++++++--------- wally-pipelined/src/cache/dcache.sv | 1 + .../testbench/testbench-imperas.sv | 4 +- 3 files changed, 68 insertions(+), 68 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 4205be70..91544483 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -12,40 +12,40 @@ add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrVali add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -group {Memory Stage} /testbench/InstrMName add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -321,14 +321,14 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -370,28 +370,27 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM -add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group ptwalker -divider data -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM -add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE +add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM +add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group ptwalker -divider data +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM +add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM +add wave -noupdate -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -424,7 +423,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 3} {21755 ns} 0} {{Cursor 4} {15501 ns} 0} +WaveRestoreCursors {{Cursor 4} {48736 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -440,4 +439,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {21597 ns} {21891 ns} +WaveRestoreZoom {48440 ns} {48880 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index b0ac3328..6e5c95d2 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -645,6 +645,7 @@ module dcache end STATE_CPU_BUSY : begin + CommittedM = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index b33b9ca4..b6a20602 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -539,14 +539,14 @@ string tests32f[] = '{ else if (TESTSPRIV) tests = tests64p; else begin - tests = {tests64p,tests64i}; + tests = {tests64periph, tests64p,tests64i}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; + if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From 8610ef204cca0ee0384e72f7d4422601ba27e547 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 10:16:16 -0500 Subject: [PATCH 036/112] Renamed DCacheStall to LSUStall in hart and hazard. Added missing logic in lsu. --- wally-pipelined/src/cache/dcache.sv | 2 +- wally-pipelined/src/hazard/hazard.sv | 4 ++-- wally-pipelined/src/lsu/lsu.sv | 1 + wally-pipelined/src/wally/wallypipelinedhart.sv | 4 ++-- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 6e5c95d2..6c3ae803 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -433,7 +433,7 @@ module dcache case (CurrState) STATE_READY: begin // TLB Miss - if(AnyCPUReqM & DTLBMissM) begin + if(AnyCPUReqM & DTLBMissM) begin NextState = STATE_PTW_READY; end // amo hit diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 331fc326..e5480286 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -31,7 +31,7 @@ module hazard( // Detect hazards input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, - input logic DCacheStall, ICacheStallF, + input logic LSUStall, ICacheStallF, input logic FPUStallD, FStallD, input logic DivBusyE,FDivBusyE, // Stall & flush outputs @@ -59,7 +59,7 @@ module hazard( assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallECause = DivBusyE | FDivBusyE; assign StallMCause = 0; - assign StallWCause = DCacheStall | ICacheStallF; + assign StallWCause = LSUStall | ICacheStallF; assign StallF = StallFCause | StallD; assign StallD = StallDCause | StallE; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index f8fa87a0..345e3514 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -152,6 +152,7 @@ module lsu logic CommittedMfromDCache; logic PendingInterruptMtoDCache; + logic FlushWtoDCache; pagetablewalker pagetablewalker( diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index e0337bc3..b8d7af57 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -126,7 +126,7 @@ module wallypipelinedhart // IMem stalls logic ICacheStallF; - logic DCacheStall; + logic LSUStall; @@ -233,7 +233,7 @@ module wallypipelinedhart .DTLBHitM(DTLBHitM), // not connected remove - .LSUStall(DCacheStall)); // change to DCacheStall + .LSUStall(LSUStall)); // change to LSUStall From b9902b056079b21be1750c855bc1a03823597193 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 11:00:42 -0500 Subject: [PATCH 037/112] Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. --- wally-pipelined/src/cache/dcache.sv | 10 +++++++++- wally-pipelined/src/mmu/pagetablewalker.sv | 10 +--------- wally-pipelined/testbench/testbench-imperas.sv | 2 +- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 6c3ae803..d6915666 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -433,7 +433,14 @@ module dcache case (CurrState) STATE_READY: begin // TLB Miss - if(AnyCPUReqM & DTLBMissM) begin + if(AnyCPUReqM & DTLBMissM) begin + // the LSU arbiter has not yet selected the PTW. + // The CPU needs to be stalled until that happens. + // If we set DCacheStall for 1 cycle before going to + // PTW ready the CPU will stall. + // The page table walker asserts it's control 1 cycle + // after the TLBs miss. + DCacheStall = 1'b1; NextState = STATE_PTW_READY; end // amo hit @@ -580,6 +587,7 @@ module dcache end STATE_PTW_READY: begin + // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. if(DTLBWriteM) begin diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 334ef2b2..5beddf48 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -77,7 +77,6 @@ module pagetablewalker if (`MEM_VIRTMEM) begin // Internal signals // register TLBs translation miss requests - logic [`XLEN-1:0] TranslationVAdrQ; logic ITLBMissFQ, DTLBMissMQ; logic [`PPN_BITS-1:0] BasePageTablePPN; @@ -138,13 +137,6 @@ module pagetablewalker assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr assign SelDataTranslation = DTLBMissMQ | DTLBMissM; - flopenr #(`XLEN) - TranslationVAdrReg(.clk(clk), - .reset(reset), - .en(StartWalk), - .d(TranslationVAdr), - .q(TranslationVAdrQ)); - flopenrc #(1) DTLBMissMReg(.clk(clk), .reset(reset), @@ -170,7 +162,7 @@ module pagetablewalker (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || (WalkerState == FAULT); - assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; + assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ); //assign HPTWTranslate = DTLBMissM | ITLBMissF; // unswizzle PTE bits diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index b6a20602..418ddc42 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -543,10 +543,10 @@ string tests32f[] = '{ if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; - if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; + if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From fd1de6b04760baca9c2f82ab1810564b3ccbd12b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 11:04:49 -0500 Subject: [PATCH 038/112] Updated wave file. --- wally-pipelined/regression/wave.do | 177 +++++++++++++---------------- 1 file changed, 82 insertions(+), 95 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 91544483..697bc567 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -8,33 +8,34 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD @@ -113,7 +114,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 @@ -126,19 +127,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -expand -group alu -divider internals -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu -add wave -noupdate /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu -divider internals +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -240,12 +240,9 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrE -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrE -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrMtoDCache -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrEtoDCache +add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM @@ -254,22 +251,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM @@ -298,7 +295,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW @@ -308,10 +304,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed @@ -321,14 +321,24 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWTranslate +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM +add wave -noupdate -expand -group lsu -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -group ptwalker -divider data +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -370,27 +380,6 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM -add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -group ptwalker -divider data -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM -add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -420,10 +409,8 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA -add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN -add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {48736 ns} 0} +WaveRestoreCursors {{Cursor 4} {25841 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -439,4 +426,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {48440 ns} {48880 ns} +WaveRestoreZoom {25409 ns} {26369 ns} From e5d624c1fabc98cc44928bda7599745814c1b379 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 11:56:35 -0500 Subject: [PATCH 039/112] Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. --- wally-pipelined/regression/wave.do | 177 +++++++++--------- wally-pipelined/src/ifu/ifu.sv | 4 - wally-pipelined/src/lsu/lsu.sv | 2 +- wally-pipelined/src/mmu/pmachecker.sv | 2 +- .../testbench/testbench-imperas.sv | 2 +- 5 files changed, 95 insertions(+), 92 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 697bc567..6c4b1d79 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -29,14 +29,15 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -243,81 +244,87 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/HPTWTranslate add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/CurrState add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM @@ -410,7 +417,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {25841 ns} 0} +WaveRestoreCursors {{Cursor 4} {10516 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -426,4 +433,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {25409 ns} {26369 ns} +WaveRestoreZoom {10473 ns} {10589 ns} diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index ff2545b7..a0728a1a 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -101,10 +101,6 @@ module ifu ( logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; - logic PMALoadAccessFaultM, PMAStoreAccessFaultM; - logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage - // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. - logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. generate diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 9bb991ef..0f38b829 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -219,7 +219,7 @@ module lsu mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) - dmmu(.VirtualAddress(MemAdrMtoDCache), + dmmu(.Address(MemAdrMtoDCache), .Size(Funct3MtoDCache[1:0]), .PTE(PageTableEntryM), .PageTypeWriteVal(PageTypeM), diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 86abcb3f..a95252f3 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -61,7 +61,7 @@ module pmachecker ( assign AtomicAllowed = SelRegions[4]; // Detect access faults - assign PMAAccessFault = (~|SelRegions) & AccessRWX; + assign PMAAccessFault = SelRegions[6] & AccessRWX; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 2d41efd9..67140aa0 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -535,7 +535,7 @@ string tests32f[] = '{ else if (TESTSPRIV) tests = tests64p; else begin - tests = {tests64periph, tests64p,tests64i}; + tests = {tests64p,tests64i, tests64periph}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; From 3b6291b734c03f453281b64f062cc5f67e7e29bd Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 16:07:56 -0400 Subject: [PATCH 041/112] stripped down busybox a bit --- .../buildroot-config-src/busybox.config | 280 +++++++++--------- .../buildroot-config-src/main.config | 2 +- 2 files changed, 139 insertions(+), 143 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/busybox.config b/wally-pipelined/linux-testgen/buildroot-config-src/busybox.config index c8e96261..48aa77ee 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/busybox.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/busybox.config @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Busybox version: 1.33.1 -# Wed Jun 30 12:12:45 2021 +# Thu Jul 15 15:59:54 2021 # CONFIG_HAVE_DOT_CONFIG=y @@ -13,28 +13,28 @@ CONFIG_HAVE_DOT_CONFIG=y # CONFIG_FEDORA_COMPAT is not set # CONFIG_INCLUDE_SUSv2 is not set CONFIG_LONG_OPTS=y -CONFIG_SHOW_USAGE=y -CONFIG_FEATURE_VERBOSE_USAGE=y +# CONFIG_SHOW_USAGE is not set +# CONFIG_FEATURE_VERBOSE_USAGE is not set # CONFIG_FEATURE_COMPRESS_USAGE is not set # CONFIG_LFS is not set # CONFIG_PAM is not set -CONFIG_FEATURE_DEVPTS=y -CONFIG_FEATURE_UTMP=y -CONFIG_FEATURE_WTMP=y +# CONFIG_FEATURE_DEVPTS is not set +# CONFIG_FEATURE_UTMP is not set +# CONFIG_FEATURE_WTMP is not set # CONFIG_FEATURE_PIDFILE is not set CONFIG_PID_FILE_PATH="" CONFIG_BUSYBOX=y CONFIG_FEATURE_SHOW_SCRIPT=y CONFIG_FEATURE_INSTALLER=y # CONFIG_INSTALL_NO_USR is not set -CONFIG_FEATURE_SUID=y +# CONFIG_FEATURE_SUID is not set # CONFIG_FEATURE_SUID_CONFIG is not set # CONFIG_FEATURE_SUID_CONFIG_QUIET is not set # CONFIG_FEATURE_PREFER_APPLETS is not set CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe" # CONFIG_SELINUX is not set # CONFIG_FEATURE_CLEAN_UP is not set -CONFIG_FEATURE_SYSLOG_INFO=y +# CONFIG_FEATURE_SYSLOG_INFO is not set CONFIG_FEATURE_SYSLOG=y # @@ -53,7 +53,7 @@ CONFIG_EXTRA_CFLAGS="" CONFIG_EXTRA_LDFLAGS="" CONFIG_EXTRA_LDLIBS="" # CONFIG_USE_PORTABLE_CODE is not set -CONFIG_STACK_OPTIMIZATION_386=y +# CONFIG_STACK_OPTIMIZATION_386 is not set CONFIG_STATIC_LIBGCC=y # @@ -71,7 +71,7 @@ CONFIG_PREFIX="./_install" # # Debugging Options # -# CONFIG_DEBUG is not set +CONFIG_DEBUG=y # CONFIG_DEBUG_PESSIMIZE is not set # CONFIG_DEBUG_SANITIZE is not set # CONFIG_UNIT_TEST is not set @@ -85,9 +85,9 @@ CONFIG_NO_DEBUG_LIB=y # Library Tuning # # CONFIG_FEATURE_USE_BSS_TAIL is not set -CONFIG_FLOAT_DURATION=y -CONFIG_FEATURE_RTMINMAX=y -CONFIG_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS=y +# CONFIG_FLOAT_DURATION is not set +# CONFIG_FEATURE_RTMINMAX is not set +# CONFIG_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS is not set CONFIG_FEATURE_BUFFERS_USE_MALLOC=y # CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set # CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set @@ -97,17 +97,17 @@ CONFIG_SHA3_SMALL=1 # CONFIG_FEATURE_FAST_TOP is not set # CONFIG_FEATURE_ETC_NETWORKS is not set # CONFIG_FEATURE_ETC_SERVICES is not set -CONFIG_FEATURE_EDITING=y -CONFIG_FEATURE_EDITING_MAX_LEN=1024 -CONFIG_FEATURE_EDITING_VI=y -CONFIG_FEATURE_EDITING_HISTORY=999 -CONFIG_FEATURE_EDITING_SAVEHISTORY=y +# CONFIG_FEATURE_EDITING is not set +CONFIG_FEATURE_EDITING_MAX_LEN=0 +# CONFIG_FEATURE_EDITING_VI is not set +CONFIG_FEATURE_EDITING_HISTORY=0 +# CONFIG_FEATURE_EDITING_SAVEHISTORY is not set # CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set -CONFIG_FEATURE_REVERSE_SEARCH=y -CONFIG_FEATURE_TAB_COMPLETION=y +# CONFIG_FEATURE_REVERSE_SEARCH is not set +# CONFIG_FEATURE_TAB_COMPLETION is not set # CONFIG_FEATURE_USERNAME_COMPLETION is not set -CONFIG_FEATURE_EDITING_FANCY_PROMPT=y -CONFIG_FEATURE_EDITING_WINCH=y +# CONFIG_FEATURE_EDITING_FANCY_PROMPT is not set +# CONFIG_FEATURE_EDITING_WINCH is not set # CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set # CONFIG_LOCALE_SUPPORT is not set # CONFIG_UNICODE_SUPPORT is not set @@ -120,14 +120,14 @@ CONFIG_LAST_SUPPORTED_WCHAR=0 # CONFIG_UNICODE_BIDI_SUPPORT is not set # CONFIG_UNICODE_NEUTRAL_TABLE is not set # CONFIG_UNICODE_PRESERVE_BROKEN is not set -CONFIG_FEATURE_NON_POSIX_CP=y -# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set -CONFIG_FEATURE_USE_SENDFILE=y +# CONFIG_FEATURE_NON_POSIX_CP is not set +CONFIG_FEATURE_VERBOSE_CP_MESSAGE=y +# CONFIG_FEATURE_USE_SENDFILE is not set CONFIG_FEATURE_COPYBUF_KB=4 CONFIG_FEATURE_SKIP_ROOTFS=y -CONFIG_MONOTONIC_SYSCALL=y -CONFIG_IOCTL_HEX2STR_ERROR=y -CONFIG_FEATURE_HWIB=y +# CONFIG_MONOTONIC_SYSCALL is not set +# CONFIG_IOCTL_HEX2STR_ERROR is not set +# CONFIG_FEATURE_HWIB is not set # # Applets @@ -160,8 +160,8 @@ CONFIG_FEATURE_HWIB=y CONFIG_BZIP2_SMALL=0 # CONFIG_FEATURE_BZIP2_DECOMPRESS is not set CONFIG_CPIO=y -CONFIG_FEATURE_CPIO_O=y -CONFIG_FEATURE_CPIO_P=y +# CONFIG_FEATURE_CPIO_O is not set +# CONFIG_FEATURE_CPIO_P is not set # CONFIG_DPKG is not set # CONFIG_DPKG_DEB is not set CONFIG_GZIP=y @@ -175,15 +175,15 @@ CONFIG_FEATURE_GZIP_DECOMPRESS=y # CONFIG_LZOP_COMPR_HIGH is not set # CONFIG_RPM is not set # CONFIG_RPM2CPIO is not set -CONFIG_TAR=y -CONFIG_FEATURE_TAR_LONG_OPTIONS=y -CONFIG_FEATURE_TAR_CREATE=y +# CONFIG_TAR is not set +# CONFIG_FEATURE_TAR_LONG_OPTIONS is not set +# CONFIG_FEATURE_TAR_CREATE is not set # CONFIG_FEATURE_TAR_AUTODETECT is not set -CONFIG_FEATURE_TAR_FROM=y +# CONFIG_FEATURE_TAR_FROM is not set # CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY is not set # CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY is not set -CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y -CONFIG_FEATURE_TAR_TO_COMMAND=y +# CONFIG_FEATURE_TAR_GNU_EXTENSIONS is not set +# CONFIG_FEATURE_TAR_TO_COMMAND is not set # CONFIG_FEATURE_TAR_UNAME_GNAME is not set # CONFIG_FEATURE_TAR_NOPRESERVE_TIME is not set # CONFIG_FEATURE_TAR_SELINUX is not set @@ -224,8 +224,8 @@ CONFIG_FEATURE_DD_STATUS=y CONFIG_DF=y # CONFIG_FEATURE_DF_FANCY is not set CONFIG_DIRNAME=y -CONFIG_DOS2UNIX=y -CONFIG_UNIX2DOS=y +# CONFIG_DOS2UNIX is not set +# CONFIG_UNIX2DOS is not set CONFIG_DU=y CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y CONFIG_ECHO=y @@ -277,7 +277,7 @@ CONFIG_NICE=y CONFIG_NL=y CONFIG_NOHUP=y CONFIG_NPROC=y -CONFIG_OD=y +# CONFIG_OD is not set CONFIG_PASTE=y CONFIG_PRINTENV=y CONFIG_PRINTF=y @@ -288,15 +288,15 @@ CONFIG_REALPATH=y CONFIG_RM=y CONFIG_RMDIR=y CONFIG_SEQ=y -CONFIG_SHRED=y +# CONFIG_SHRED is not set # CONFIG_SHUF is not set -CONFIG_SLEEP=y -CONFIG_FEATURE_FANCY_SLEEP=y +# CONFIG_SLEEP is not set +# CONFIG_FEATURE_FANCY_SLEEP is not set CONFIG_SORT=y -CONFIG_FEATURE_SORT_BIG=y +# CONFIG_FEATURE_SORT_BIG is not set # CONFIG_FEATURE_SORT_OPTIMIZE_MEMORY is not set -# CONFIG_SPLIT is not set -# CONFIG_FEATURE_SPLIT_FANCY is not set +CONFIG_SPLIT=y +CONFIG_FEATURE_SPLIT_FANCY=y # CONFIG_STAT is not set # CONFIG_FEATURE_STAT_FORMAT is not set # CONFIG_FEATURE_STAT_FILESYSTEM is not set @@ -317,7 +317,7 @@ CONFIG_FEATURE_TEST_64=y # CONFIG_TIMEOUT is not set CONFIG_TOUCH=y # CONFIG_FEATURE_TOUCH_NODEREF is not set -CONFIG_FEATURE_TOUCH_SUSV3=y +# CONFIG_FEATURE_TOUCH_SUSV3 is not set CONFIG_TR=y CONFIG_FEATURE_TR_CLASSES=y CONFIG_FEATURE_TR_EQUIV=y @@ -325,7 +325,7 @@ CONFIG_TRUE=y CONFIG_TRUNCATE=y CONFIG_TTY=y CONFIG_UNAME=y -CONFIG_UNAME_OSNAME="GNU/Linux" +CONFIG_UNAME_OSNAME="GNU/Linux for Wally" CONFIG_BB_ARCH=y CONFIG_UNIQ=y CONFIG_UNLINK=y @@ -337,8 +337,8 @@ CONFIG_UUENCODE=y CONFIG_WC=y # CONFIG_FEATURE_WC_LARGE is not set CONFIG_WHOAMI=y -CONFIG_WHO=y -CONFIG_W=y +# CONFIG_WHO is not set +# CONFIG_W is not set # CONFIG_USERS is not set CONFIG_YES=y @@ -363,36 +363,32 @@ CONFIG_FEATURE_HUMAN_READABLE=y CONFIG_CHVT=y CONFIG_CLEAR=y CONFIG_DEALLOCVT=y -CONFIG_DUMPKMAP=y +# CONFIG_DUMPKMAP is not set # CONFIG_FGCONSOLE is not set # CONFIG_KBD_MODE is not set -CONFIG_LOADFONT=y +# CONFIG_LOADFONT is not set # CONFIG_SETFONT is not set # CONFIG_FEATURE_SETFONT_TEXTUAL_MAP is not set CONFIG_DEFAULT_SETFONT_DIR="" - -# -# Common options for loadfont and setfont -# -CONFIG_FEATURE_LOADFONT_PSF2=y -CONFIG_FEATURE_LOADFONT_RAW=y -CONFIG_LOADKMAP=y +# CONFIG_FEATURE_LOADFONT_PSF2 is not set +# CONFIG_FEATURE_LOADFONT_RAW is not set +# CONFIG_LOADKMAP is not set CONFIG_OPENVT=y CONFIG_RESET=y -CONFIG_RESIZE=y -CONFIG_FEATURE_RESIZE_PRINT=y +# CONFIG_RESIZE is not set +# CONFIG_FEATURE_RESIZE_PRINT is not set CONFIG_SETCONSOLE=y # CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS is not set -CONFIG_SETKEYCODES=y +# CONFIG_SETKEYCODES is not set CONFIG_SETLOGCONS=y # CONFIG_SHOWKEY is not set # # Debian Utilities # -CONFIG_PIPE_PROGRESS=y -CONFIG_RUN_PARTS=y -CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y +# CONFIG_PIPE_PROGRESS is not set +# CONFIG_RUN_PARTS is not set +# CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS is not set # CONFIG_FEATURE_RUN_PARTS_FANCY is not set CONFIG_START_STOP_DAEMON=y CONFIG_FEATURE_START_STOP_DAEMON_LONG_OPTIONS=y @@ -405,15 +401,15 @@ CONFIG_WHICH=y # CONFIG_MINIPS is not set # CONFIG_NUKE is not set # CONFIG_RESUME is not set -# CONFIG_RUN_INIT is not set +CONFIG_RUN_INIT=y # # Editors # -CONFIG_AWK=y +# CONFIG_AWK is not set # CONFIG_FEATURE_AWK_LIBM is not set -CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y -CONFIG_CMP=y +# CONFIG_FEATURE_AWK_GNU_EXTENSIONS is not set +# CONFIG_CMP is not set CONFIG_DIFF=y # CONFIG_FEATURE_DIFF_LONG_OPTIONS is not set CONFIG_FEATURE_DIFF_DIR=y @@ -437,7 +433,7 @@ CONFIG_FEATURE_VI_ASK_TERMINAL=y CONFIG_FEATURE_VI_UNDO=y CONFIG_FEATURE_VI_UNDO_QUEUE=y CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256 -CONFIG_FEATURE_ALLOW_EXEC=y +# CONFIG_FEATURE_ALLOW_EXEC is not set # # Finding Utilities @@ -543,21 +539,21 @@ CONFIG_FEATURE_SU_SYSLOG=y CONFIG_FEATURE_SU_CHECKS_SHELLS=y # CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set CONFIG_SULOGIN=y -CONFIG_VLOCK=y +# CONFIG_VLOCK is not set # # Linux Ext2 FS Progs # -CONFIG_CHATTR=y -CONFIG_FSCK=y -CONFIG_LSATTR=y +# CONFIG_CHATTR is not set +# CONFIG_FSCK is not set +# CONFIG_LSATTR is not set # CONFIG_TUNE2FS is not set # # Linux Module Utilities # # CONFIG_MODPROBE_SMALL is not set -# CONFIG_DEPMOD is not set +CONFIG_DEPMOD=y CONFIG_INSMOD=y CONFIG_LSMOD=y CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT=y @@ -597,62 +593,62 @@ CONFIG_BLKID=y CONFIG_CHRT=y CONFIG_DMESG=y CONFIG_FEATURE_DMESG_PRETTY=y -CONFIG_EJECT=y +# CONFIG_EJECT is not set # CONFIG_FEATURE_EJECT_SCSI is not set CONFIG_FALLOCATE=y # CONFIG_FATATTR is not set -CONFIG_FBSET=y -CONFIG_FEATURE_FBSET_FANCY=y -CONFIG_FEATURE_FBSET_READMODE=y -CONFIG_FDFORMAT=y -CONFIG_FDISK=y -CONFIG_FDISK_SUPPORT_LARGE_DISKS=y -CONFIG_FEATURE_FDISK_WRITABLE=y +# CONFIG_FBSET is not set +# CONFIG_FEATURE_FBSET_FANCY is not set +# CONFIG_FEATURE_FBSET_READMODE is not set +# CONFIG_FDFORMAT is not set +# CONFIG_FDISK is not set +# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set +# CONFIG_FEATURE_FDISK_WRITABLE is not set # CONFIG_FEATURE_AIX_LABEL is not set # CONFIG_FEATURE_SGI_LABEL is not set # CONFIG_FEATURE_SUN_LABEL is not set # CONFIG_FEATURE_OSF_LABEL is not set -CONFIG_FEATURE_GPT_LABEL=y -CONFIG_FEATURE_FDISK_ADVANCED=y +# CONFIG_FEATURE_GPT_LABEL is not set +# CONFIG_FEATURE_FDISK_ADVANCED is not set # CONFIG_FINDFS is not set -CONFIG_FLOCK=y -CONFIG_FDFLUSH=y +# CONFIG_FLOCK is not set +# CONFIG_FDFLUSH is not set CONFIG_FREERAMDISK=y # CONFIG_FSCK_MINIX is not set -CONFIG_FSFREEZE=y -CONFIG_FSTRIM=y +# CONFIG_FSFREEZE is not set +# CONFIG_FSTRIM is not set CONFIG_GETOPT=y CONFIG_FEATURE_GETOPT_LONG=y CONFIG_HEXDUMP=y # CONFIG_HD is not set CONFIG_XXD=y -CONFIG_HWCLOCK=y -CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS=y +# CONFIG_HWCLOCK is not set +# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set # CONFIG_IONICE is not set -CONFIG_IPCRM=y -CONFIG_IPCS=y -CONFIG_LAST=y +# CONFIG_IPCRM is not set +# CONFIG_IPCS is not set +# CONFIG_LAST is not set # CONFIG_FEATURE_LAST_FANCY is not set # CONFIG_LOSETUP is not set # CONFIG_LSPCI is not set # CONFIG_LSUSB is not set -CONFIG_MDEV=y -CONFIG_FEATURE_MDEV_CONF=y -CONFIG_FEATURE_MDEV_RENAME=y +# CONFIG_MDEV is not set +# CONFIG_FEATURE_MDEV_CONF is not set +# CONFIG_FEATURE_MDEV_RENAME is not set # CONFIG_FEATURE_MDEV_RENAME_REGEXP is not set -CONFIG_FEATURE_MDEV_EXEC=y +# CONFIG_FEATURE_MDEV_EXEC is not set # CONFIG_FEATURE_MDEV_LOAD_FIRMWARE is not set -CONFIG_FEATURE_MDEV_DAEMON=y -CONFIG_MESG=y -CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y -CONFIG_MKE2FS=y +# CONFIG_FEATURE_MDEV_DAEMON is not set +# CONFIG_MESG is not set +# CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP is not set +# CONFIG_MKE2FS is not set # CONFIG_MKFS_EXT2 is not set # CONFIG_MKFS_MINIX is not set # CONFIG_FEATURE_MINIX2 is not set # CONFIG_MKFS_REISER is not set -CONFIG_MKDOSFS=y +# CONFIG_MKDOSFS is not set # CONFIG_MKFS_VFAT is not set -CONFIG_MKSWAP=y +# CONFIG_MKSWAP is not set # CONFIG_FEATURE_MKSWAP_UUID is not set CONFIG_MORE=y CONFIG_MOUNT=y @@ -661,16 +657,16 @@ CONFIG_MOUNT=y # CONFIG_FEATURE_MOUNT_HELPERS is not set # CONFIG_FEATURE_MOUNT_LABEL is not set # CONFIG_FEATURE_MOUNT_NFS is not set -CONFIG_FEATURE_MOUNT_CIFS=y +# CONFIG_FEATURE_MOUNT_CIFS is not set CONFIG_FEATURE_MOUNT_FLAGS=y CONFIG_FEATURE_MOUNT_FSTAB=y CONFIG_FEATURE_MOUNT_OTHERTAB=y CONFIG_MOUNTPOINT=y -CONFIG_NOLOGIN=y +# CONFIG_NOLOGIN is not set # CONFIG_NOLOGIN_DEPENDENCIES is not set # CONFIG_NSENTER is not set CONFIG_PIVOT_ROOT=y -CONFIG_RDATE=y +# CONFIG_RDATE is not set # CONFIG_RDEV is not set CONFIG_READPROFILE=y CONFIG_RENICE=y @@ -704,8 +700,8 @@ CONFIG_FEATURE_UMOUNT_ALL=y # # Common options for mount/umount # -CONFIG_FEATURE_MOUNT_LOOP=y -CONFIG_FEATURE_MOUNT_LOOP_CREATE=y +# CONFIG_FEATURE_MOUNT_LOOP is not set +# CONFIG_FEATURE_MOUNT_LOOP_CREATE is not set # CONFIG_FEATURE_MTAB_SUPPORT is not set CONFIG_VOLUMEID=y @@ -715,10 +711,10 @@ CONFIG_VOLUMEID=y # CONFIG_FEATURE_VOLUMEID_BCACHE is not set # CONFIG_FEATURE_VOLUMEID_BTRFS is not set # CONFIG_FEATURE_VOLUMEID_CRAMFS is not set -CONFIG_FEATURE_VOLUMEID_EROFS=y -CONFIG_FEATURE_VOLUMEID_EXFAT=y -CONFIG_FEATURE_VOLUMEID_EXT=y -CONFIG_FEATURE_VOLUMEID_F2FS=y +# CONFIG_FEATURE_VOLUMEID_EROFS is not set +# CONFIG_FEATURE_VOLUMEID_EXFAT is not set +# CONFIG_FEATURE_VOLUMEID_EXT is not set +# CONFIG_FEATURE_VOLUMEID_F2FS is not set CONFIG_FEATURE_VOLUMEID_FAT=y # CONFIG_FEATURE_VOLUMEID_HFS is not set # CONFIG_FEATURE_VOLUMEID_ISO9660 is not set @@ -727,7 +723,7 @@ CONFIG_FEATURE_VOLUMEID_FAT=y # CONFIG_FEATURE_VOLUMEID_LINUXRAID is not set # CONFIG_FEATURE_VOLUMEID_LINUXSWAP is not set # CONFIG_FEATURE_VOLUMEID_LUKS is not set -CONFIG_FEATURE_VOLUMEID_MINIX=y +# CONFIG_FEATURE_VOLUMEID_MINIX is not set # CONFIG_FEATURE_VOLUMEID_NILFS is not set # CONFIG_FEATURE_VOLUMEID_NTFS is not set # CONFIG_FEATURE_VOLUMEID_OCFS2 is not set @@ -735,7 +731,7 @@ CONFIG_FEATURE_VOLUMEID_MINIX=y # CONFIG_FEATURE_VOLUMEID_ROMFS is not set # CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set # CONFIG_FEATURE_VOLUMEID_SYSV is not set -CONFIG_FEATURE_VOLUMEID_UBIFS=y +# CONFIG_FEATURE_VOLUMEID_UBIFS is not set # CONFIG_FEATURE_VOLUMEID_UDF is not set # CONFIG_FEATURE_VOLUMEID_XFS is not set @@ -763,12 +759,12 @@ CONFIG_FEATURE_BEEP_LENGTH_MS=0 # CONFIG_FEATURE_CHAT_VAR_ABORT_LEN is not set # CONFIG_FEATURE_CHAT_CLR_ABORT is not set # CONFIG_CONSPY is not set -# CONFIG_CROND is not set +CONFIG_CROND=y # CONFIG_FEATURE_CROND_D is not set # CONFIG_FEATURE_CROND_CALL_SENDMAIL is not set -# CONFIG_FEATURE_CROND_SPECIAL_TIMES is not set -CONFIG_FEATURE_CROND_DIR="" -# CONFIG_CRONTAB is not set +CONFIG_FEATURE_CROND_SPECIAL_TIMES=y +CONFIG_FEATURE_CROND_DIR="/var/spool/cron" +CONFIG_CRONTAB=y # CONFIG_DEVFSD is not set # CONFIG_DEVFSD_MODLOAD is not set # CONFIG_DEVFSD_FG_NP is not set @@ -794,13 +790,13 @@ CONFIG_HEXEDIT=y # CONFIG_I2CDETECT is not set # CONFIG_I2CTRANSFER is not set # CONFIG_INOTIFYD is not set -# CONFIG_LESS is not set -CONFIG_FEATURE_LESS_MAXLINES=0 +CONFIG_LESS=y +CONFIG_FEATURE_LESS_MAXLINES=9999999 # CONFIG_FEATURE_LESS_BRACKETS is not set # CONFIG_FEATURE_LESS_FLAGS is not set # CONFIG_FEATURE_LESS_TRUNCATE is not set # CONFIG_FEATURE_LESS_MARKS is not set -# CONFIG_FEATURE_LESS_REGEXP is not set +CONFIG_FEATURE_LESS_REGEXP=y # CONFIG_FEATURE_LESS_WINCH is not set # CONFIG_FEATURE_LESS_ASK_TERMINAL is not set # CONFIG_FEATURE_LESS_DASHCMD is not set @@ -808,11 +804,11 @@ CONFIG_FEATURE_LESS_MAXLINES=0 # CONFIG_FEATURE_LESS_RAW is not set # CONFIG_FEATURE_LESS_ENV is not set # CONFIG_LSSCSI is not set -# CONFIG_MAKEDEVS is not set +CONFIG_MAKEDEVS=y # CONFIG_FEATURE_MAKEDEVS_LEAF is not set -# CONFIG_FEATURE_MAKEDEVS_TABLE is not set -CONFIG_MAN=y -# CONFIG_MICROCOM is not set +CONFIG_FEATURE_MAKEDEVS_TABLE=y +# CONFIG_MAN is not set +CONFIG_MICROCOM=y # CONFIG_MIM is not set # CONFIG_MT is not set # CONFIG_NANDWRITE is not set @@ -821,7 +817,7 @@ CONFIG_PARTPROBE=y # CONFIG_RAIDAUTORUN is not set # CONFIG_READAHEAD is not set # CONFIG_RFKILL is not set -CONFIG_RUNLEVEL=y +# CONFIG_RUNLEVEL is not set # CONFIG_RX is not set CONFIG_SETFATTR=y CONFIG_SETSERIAL=y @@ -829,7 +825,7 @@ CONFIG_STRINGS=y CONFIG_TIME=y CONFIG_TS=y # CONFIG_TTYSIZE is not set -# CONFIG_UBIRENAME is not set +CONFIG_UBIRENAME=y # CONFIG_UBIATTACH is not set # CONFIG_UBIDETACH is not set # CONFIG_UBIMKVOL is not set @@ -837,7 +833,7 @@ CONFIG_TS=y # CONFIG_UBIRSVOL is not set # CONFIG_UBIUPDATEVOL is not set # CONFIG_VOLNAME is not set -# CONFIG_WATCHDOG is not set +CONFIG_WATCHDOG=y # # Networking Utilities @@ -861,7 +857,7 @@ CONFIG_TS=y # CONFIG_FTPGET is not set # CONFIG_FTPPUT is not set # CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS is not set -# CONFIG_HOSTNAME is not set +CONFIG_HOSTNAME=y # CONFIG_DNSDOMAINNAME is not set # CONFIG_HTTPD is not set # CONFIG_FEATURE_HTTPD_RANGES is not set @@ -1034,8 +1030,8 @@ CONFIG_KILLALL5=y CONFIG_LSOF=y # CONFIG_MPSTAT is not set # CONFIG_NMETER is not set -CONFIG_PGREP=y -CONFIG_PKILL=y +# CONFIG_PGREP is not set +# CONFIG_PKILL is not set CONFIG_PIDOF=y CONFIG_FEATURE_PIDOF_SINGLE=y CONFIG_FEATURE_PIDOF_OMIT=y @@ -1053,7 +1049,7 @@ CONFIG_PSTREE=y # CONFIG_SMEMCAP is not set CONFIG_BB_SYSCTL=y CONFIG_TOP=y -CONFIG_FEATURE_TOP_INTERACTIVE=y +# CONFIG_FEATURE_TOP_INTERACTIVE is not set CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y # CONFIG_FEATURE_TOP_SMP_CPU is not set @@ -1078,8 +1074,8 @@ CONFIG_WATCH=y # CONFIG_FEATURE_RUNSVDIR_LOG is not set # CONFIG_SV is not set CONFIG_SV_DEFAULT_SERVICE_DIR="" -CONFIG_SVC=y -CONFIG_SVOK=y +# CONFIG_SVC is not set +# CONFIG_SVOK is not set # CONFIG_SVLOGD is not set # CONFIG_CHCON is not set # CONFIG_GETENFORCE is not set @@ -1109,7 +1105,7 @@ CONFIG_ASH=y CONFIG_ASH_OPTIMIZE_FOR_SIZE=y CONFIG_ASH_INTERNAL_GLOB=y CONFIG_ASH_BASH_COMPAT=y -# CONFIG_ASH_BASH_SOURCE_CURDIR is not set +CONFIG_ASH_BASH_SOURCE_CURDIR=y CONFIG_ASH_BASH_NOT_FOUND_HOOK=y CONFIG_ASH_JOB_CONTROL=y CONFIG_ASH_ALIAS=y @@ -1165,15 +1161,15 @@ CONFIG_ASH_CMDCMD=y # # Options common to all shells # -CONFIG_FEATURE_SH_MATH=y -CONFIG_FEATURE_SH_MATH_64=y -CONFIG_FEATURE_SH_MATH_BASE=y -CONFIG_FEATURE_SH_EXTRA_QUIET=y +# CONFIG_FEATURE_SH_MATH is not set +# CONFIG_FEATURE_SH_MATH_64 is not set +# CONFIG_FEATURE_SH_MATH_BASE is not set +# CONFIG_FEATURE_SH_EXTRA_QUIET is not set # CONFIG_FEATURE_SH_STANDALONE is not set # CONFIG_FEATURE_SH_NOFORK is not set -CONFIG_FEATURE_SH_READ_FRAC=y +# CONFIG_FEATURE_SH_READ_FRAC is not set # CONFIG_FEATURE_SH_HISTFILESIZE is not set -CONFIG_FEATURE_SH_EMBEDDED_SCRIPTS=y +# CONFIG_FEATURE_SH_EMBEDDED_SCRIPTS is not set # # System Logging Utilities @@ -1185,7 +1181,7 @@ CONFIG_LOGGER=y # CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING is not set CONFIG_SYSLOGD=y CONFIG_FEATURE_ROTATE_LOGFILE=y -CONFIG_FEATURE_REMOTE_LOG=y +# CONFIG_FEATURE_REMOTE_LOG is not set # CONFIG_FEATURE_SYSLOGD_DUP is not set # CONFIG_FEATURE_SYSLOGD_CFG is not set # CONFIG_FEATURE_SYSLOGD_PRECISE_TIMESTAMPS is not set diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/main.config b/wally-pipelined/linux-testgen/buildroot-config-src/main.config index f7dd942e..8f5779fb 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/main.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/main.config @@ -474,7 +474,7 @@ BR2_LINUX_KERNEL_GZIP=y # Target packages # BR2_PACKAGE_BUSYBOX=y -BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox.config" +BR2_PACKAGE_BUSYBOX_CONFIG="../buildroot-config-src/busybox.config" BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="" # BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set # BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set From abd5b1c02ddc3e9e0e9f529fb2972d694db7f495 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Thu, 15 Jul 2021 18:30:29 -0400 Subject: [PATCH 042/112] Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. --- wally-pipelined/src/cache/dcache.sv | 63 ++++++++++++++++++++-- wally-pipelined/src/mmu/pagetablewalker.sv | 40 +++++++++----- 2 files changed, 86 insertions(+), 17 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index d6915666..dc66043c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -162,7 +162,9 @@ module dcache STATE_PTW_READ_MISS_FETCH_DONE, STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, STATE_PTW_READ_MISS_READ_WORD, - STATE_PTW_READ_MISS_READ_WORD_DELAY, + STATE_PTW_READ_MISS_READ_WORD_DELAY, + STATE_PTW_ACCESS_AFTER_WALK, + STATE_PTW_UPDATE_TLB, STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, @@ -590,8 +592,8 @@ module dcache // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. - if(DTLBWriteM) begin - NextState = STATE_READY; + if (DTLBWriteM) begin + NextState = STATE_PTW_ACCESS_AFTER_WALK; // read hit valid cached end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin @@ -648,10 +650,63 @@ module dcache STATE_PTW_READ_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; - NextState = STATE_PTW_READY; + NextState = STATE_PTW_READY; CommittedM = 1'b1; end + + STATE_PTW_ACCESS_AFTER_WALK: begin + SelAdrM = 1'b1; + // amo hit + if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin + NextState = STATE_AMO_UPDATE; + DCacheStall = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_AMO_UPDATE; + end + // read hit valid cached + else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin + DCacheStall = 1'b0; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + end + // write hit valid cached + else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin + DCacheStall = 1'b0; + SRAMWordWriteEnableM = 1'b1; + SetDirtyM = 1'b1; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + end + // read or write miss valid cached + else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end + // uncached write + else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_WRITE; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBWrite = 1'b1; + end + // uncached read + else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_READ; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBRead = 1'b1; + end + // fault + else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin + NextState = STATE_READY; + end + else NextState = STATE_READY; + end + STATE_CPU_BUSY : begin CommittedM = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 5beddf48..282d5bf2 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -86,6 +86,7 @@ module pagetablewalker logic [`PPN_BITS-1:0] CurrentPPN; logic [`SVMODE_BITS-1:0] SvMode; logic MemStore; + logic DTLBWriteM_d; // PTE Control Bits logic Dirty, Accessed, Global, User, @@ -122,6 +123,18 @@ module pagetablewalker .d(HPTWPAdrE), .q(HPTWPAdrM)); + flop #(2) PageTypeReg(.clk(clk), + .d(PageType), + .q(PageTypeM)); + + flop #(`XLEN) PageTableEntryReg(.clk(clk), + .d(PageTableEntry), + .q(PageTableEntryM)); + + flop #(1) DTLBWriteReg(.clk(clk), + .d(DTLBWriteM_d), + .q(DTLBWriteM)); + flop #(1) HPTWReadMReg(.clk(clk), .d(HPTWReadE), .q(HPTWReadM)); @@ -157,9 +170,9 @@ module pagetablewalker assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); assign EndWalk = WalkerState == LEAF || //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || + //(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || + //(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || + //(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || (WalkerState == FAULT); assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ); @@ -176,9 +189,9 @@ module pagetablewalker // Assign specific outputs to general outputs assign PageTableEntryF = PageTableEntry; - assign PageTableEntryM = PageTableEntry; + //assign PageTableEntryM = PageTableEntry; assign PageTypeF = PageType; - assign PageTypeM = PageType; + //assign PageTypeM = PageType; // generate @@ -198,7 +211,7 @@ module pagetablewalker HPTWReadE = 1'b0; PageTableEntry = '0; PageType = '0; - DTLBWriteM = '0; + DTLBWriteM_d = '0; ITLBWriteF = '0; WalkerInstrPageFaultF = 1'b0; @@ -240,7 +253,7 @@ module pagetablewalker NextWalkerState = LEAF; PageTableEntry = CurrentPTE; PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end @@ -270,7 +283,7 @@ module pagetablewalker NextWalkerState = LEAF; PageTableEntry = CurrentPTE; PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end else begin @@ -281,6 +294,7 @@ module pagetablewalker LEAF: begin NextWalkerState = IDLE; end + FAULT: begin NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; @@ -342,7 +356,7 @@ module pagetablewalker HPTWReadE = 1'b0; PageTableEntry = '0; PageType = '0; - DTLBWriteM = '0; + DTLBWriteM_d = '0; ITLBWriteF = '0; WalkerInstrPageFaultF = 1'b0; @@ -395,7 +409,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end @@ -432,7 +446,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end @@ -469,7 +483,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; @@ -502,7 +516,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end else begin From c2535308fd477e4ca78bd37f33892645d8cb843f Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 18:49:54 -0400 Subject: [PATCH 044/112] working linux config --- .../buildroot-config-src/linux.config | 2524 +++++++++++++++-- .../buildroot-config-src/main.config | 7 +- .../gdbinit_qemulog_debug | 2 +- .../testvector-generation/logAllBuildroot.sh | 4 +- 4 files changed, 2357 insertions(+), 180 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 8c7e5d08..e66a329d 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -2,9 +2,9 @@ # Automatically generated file; DO NOT EDIT. # Linux/riscv 5.10.7 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot -g70ba6c0-dirty) 9.4.0" +CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot -g8d5e37d-dirty) 10.3.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=90400 +CONFIG_GCC_VERSION=100300 CONFIG_LD_VERSION=235020000 CONFIG_CLANG_VERSION=0 CONFIG_LLD_VERSION=0 @@ -18,19 +18,22 @@ CONFIG_THREAD_INFO_IN_TASK=y # # General setup # -CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set -CONFIG_LOCALVERSION="Wally-Local-Release-Jul-2021" +CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_HOSTNAME="Wally-Default-Hostname" -# CONFIG_SWAP is not set -# CONFIG_SYSVIPC is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_WATCH_QUEUE is not set -# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set +# CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # @@ -39,8 +42,11 @@ CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y @@ -55,13 +61,15 @@ CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set # CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y # # CPU/Task time and stats accounting @@ -69,24 +77,30 @@ CONFIG_PREEMPT_NONE=y CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set # CONFIG_PSI is not set # end of CPU/Task time and stats accounting +CONFIG_CPU_ISOLATION=y + # # RCU Subsystem # -CONFIG_TINY_RCU=y +CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y -CONFIG_TINY_SRCU=y +CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y -CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y # CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y @@ -97,36 +111,61 @@ CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y -# CONFIG_CGROUPS is not set +CONFIG_CGROUPS=y +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CGROUP_CPUACCT is not set +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../../../output/images/rootfs.cpio" +CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio" CONFIG_INITRAMFS_ROOT_UID=0 CONFIG_INITRAMFS_ROOT_GID=0 CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_RD_XZ is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set -# CONFIG_RD_ZSTD is not set +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y CONFIG_INITRAMFS_COMPRESSION_GZIP=y +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +# CONFIG_INITRAMFS_COMPRESSION_XZ is not set +# CONFIG_INITRAMFS_COMPRESSION_LZO is not set +# CONFIG_INITRAMFS_COMPRESSION_LZ4 is not set +# CONFIG_INITRAMFS_COMPRESSION_ZSTD is not set # CONFIG_INITRAMFS_COMPRESSION_NONE is not set # CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_EXPERT is not set +CONFIG_BPF=y +CONFIG_EXPERT=y CONFIG_MULTIUSER=y -CONFIG_SYSFS_SYSCALL=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y @@ -148,10 +187,12 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_BPF_SYSCALL is not set +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set # # Kernel Performance Events And Counters @@ -164,12 +205,13 @@ CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y # CONFIG_PROFILING is not set -CONFIG_TRACEPOINTS=y # end of General setup CONFIG_64BIT=y @@ -203,7 +245,7 @@ CONFIG_LOCKDEP_SUPPORT=y # SoC selection # CONFIG_SOC_SIFIVE=y -# CONFIG_SOC_VIRT is not set +CONFIG_SOC_VIRT=y # end of SoC selection # @@ -213,9 +255,12 @@ CONFIG_SOC_SIFIVE=y CONFIG_ARCH_RV64I=y # CONFIG_CMODEL_MEDLOW is not set CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y # CONFIG_MAXPHYSMEM_2GB is not set CONFIG_MAXPHYSMEM_128GB=y -# CONFIG_SMP is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=8 +# CONFIG_HOTPLUG_CPU is not set CONFIG_TUNE_GENERIC=y CONFIG_RISCV_ISA_C=y CONFIG_FPU=y @@ -229,14 +274,16 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_RISCV_SBI_V01 is not set +CONFIG_SCHED_HRTICK=y +CONFIG_RISCV_SBI_V01=y # end of Kernel features # # Boot options # CONFIG_CMDLINE="" -# CONFIG_EFI is not set +CONFIG_EFI_STUB=y +CONFIG_EFI=y # end of Boot options # @@ -248,8 +295,25 @@ CONFIG_CMDLINE="" # # Firmware Drivers # +# CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_GOOGLE_FIRMWARE is not set +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y + # # Tegra firmware driver # @@ -259,7 +323,8 @@ CONFIG_CMDLINE="" # # General architecture-dependent options # -# CONFIG_JUMP_LABEL is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y @@ -273,12 +338,16 @@ CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -# CONFIG_SECCOMP is not set +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y CONFIG_HAVE_STACKPROTECTOR=y -# CONFIG_STACKPROTECTOR is not set +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 @@ -289,10 +358,13 @@ CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set # # GCOV-based kernel profiling # +# CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling @@ -302,15 +374,26 @@ CONFIG_HAVE_GCC_PLUGINS=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 -# CONFIG_MODULES is not set -CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_BLOCK=y -# CONFIG_BLK_DEV_BSG is not set +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_DEV_BSGLIB is not set # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set @@ -322,21 +405,24 @@ CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y # end of Partition Types +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y + # # IO Schedulers # -# CONFIG_MQ_IOSCHED_DEADLINE is not set -# CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y # CONFIG_IOSCHED_BFQ is not set # end of IO Schedulers -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -CONFIG_INLINE_READ_UNLOCK=y -CONFIG_INLINE_READ_UNLOCK_IRQ=y -CONFIG_INLINE_WRITE_UNLOCK=y -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_MMIOWB=y # # Executable file formats @@ -361,13 +447,16 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_COMPACTION is not set +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NEED_PER_CPU_KM=y # CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set # CONFIG_CMA is not set # CONFIG_ZPOOL is not set # CONFIG_ZBUD is not set @@ -379,15 +468,228 @@ CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options -# CONFIG_NET is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +# CONFIG_XFRM_USER is not set +# CONFIG_NET_KEY is not set +# CONFIG_XDP_SOCKETS is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_MPTCP is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +# CONFIG_NET_9P_DEBUG is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_FAILOVER=y +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # # Device Drivers # CONFIG_HAVE_PCI=y -# CONFIG_PCI is not set +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIE_PTM is not set +# CONFIG_PCIE_BW is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_MSI_ARCH_FALLBACKS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +CONFIG_PCI_ECAM=y +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +# CONFIG_PCI_FTPCI100 is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_XILINX=y + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_MESON is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + # CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set # # Generic Driver Options @@ -411,16 +713,22 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y # end of Generic Driver Options # # Bus devices # +# CONFIG_MOXTET is not set # CONFIG_MHI_BUS is not set # end of Bus devices +# CONFIG_CONNECTOR is not set # CONFIG_GNSS is not set # CONFIG_MTD is not set CONFIG_DTC=y @@ -431,23 +739,57 @@ CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y +CONFIG_OF_NET=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set # CONFIG_PARPORT is not set -# CONFIG_BLK_DEV is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_CDROM=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_VIRTIO_BLK=y +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set # # NVME Support # +# CONFIG_BLK_DEV_NVME is not set # CONFIG_NVME_FC is not set # end of NVME Support # # Misc devices # +# CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set @@ -455,18 +797,32 @@ CONFIG_OF_RESERVED_MEM=y # # EEPROM support # +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set # end of EEPROM support +# CONFIG_CB710_CORE is not set + # # Texas Instruments shared transport line discipline # # end of Texas Instruments shared transport line discipline -# -# Altera FPGA firmware download module (requires I2C) -# +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_GENWQE is not set # CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set # end of Misc devices # @@ -474,12 +830,522 @@ CONFIG_OF_RESERVED_MEM=y # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_SMARTPQI is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +CONFIG_SCSI_VIRTIO=y +# CONFIG_SCSI_DH is not set # end of SCSI device support -# CONFIG_ATA is not set +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_QORIQ is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_SX4 is not set +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_LEGACY is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +CONFIG_VIRTIO_NET=y +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_3COM=y +# CONFIG_VORTEX is not set +# CONFIG_TYPHOON is not set +CONFIG_NET_VENDOR_ADAPTEC=y +# CONFIG_ADAPTEC_STARFIRE is not set +CONFIG_NET_VENDOR_AGERE=y +# CONFIG_ET131X is not set +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_SLICOSS is not set +CONFIG_NET_VENDOR_ALTEON=y +# CONFIG_ACENIC is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +# CONFIG_ENA_ETHERNET is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +# CONFIG_PCNET32 is not set +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +# CONFIG_ATL2 is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_ALX is not set +CONFIG_NET_VENDOR_AURORA=y +# CONFIG_AURORA_NB8800 is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCMGENET is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2X is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_BNXT is not set +CONFIG_NET_VENDOR_BROCADE=y +# CONFIG_BNA is not set +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_NET_VENDOR_CAVIUM=y +# CONFIG_THUNDER_NIC_PF is not set +# CONFIG_THUNDER_NIC_VF is not set +# CONFIG_THUNDER_NIC_BGX is not set +# CONFIG_THUNDER_NIC_RGX is not set +# CONFIG_LIQUIDIO is not set +# CONFIG_LIQUIDIO_VF is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_ENIC is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DEC=y +# CONFIG_NET_TULIP is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DL2K is not set +# CONFIG_SUNDANCE is not set +CONFIG_NET_VENDOR_EMULEX=y +# CONFIG_BE2NET is not set +CONFIG_NET_VENDOR_EZCHIP=y +# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +CONFIG_E1000E=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +# CONFIG_I40EVF is not set +# CONFIG_ICE is not set +# CONFIG_FM10K is not set +# CONFIG_IGC is not set +# CONFIG_JME is not set +CONFIG_NET_VENDOR_MARVELL=y +# CONFIG_MVMDIO is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLXSW_CORE is not set +# CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_LAN743X is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_MYRI10GE is not set +# CONFIG_FEALNX is not set +CONFIG_NET_VENDOR_NATSEMI=y +# CONFIG_NATSEMI is not set +# CONFIG_NS83820 is not set +CONFIG_NET_VENDOR_NETERION=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NFP is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_8390=y +# CONFIG_NE2K_PCI is not set +CONFIG_NET_VENDOR_NVIDIA=y +# CONFIG_FORCEDETH is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PACKET_ENGINES=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set +CONFIG_NET_VENDOR_QLOGIC=y +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_QED is not set +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCOM_EMAC is not set +# CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=y +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +# CONFIG_SXGBE_ETH is not set +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set +CONFIG_NET_VENDOR_SILAN=y +# CONFIG_SC92031 is not set +CONFIG_NET_VENDOR_SIS=y +# CONFIG_SIS900 is not set +# CONFIG_SIS190 is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_EPIC100 is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_NET_VENDOR_SUN=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NIU is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +CONFIG_NET_VENDOR_TEHUTI=y +# CONFIG_TEHUTI is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_NET_VENDOR_WIZNET=y +# CONFIG_WIZNET_W5100 is not set +# CONFIG_WIZNET_W5300 is not set +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLINK=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROSEMI_PHY=y +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH5K_PCI is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_PRISM54 is not set +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLAN_VENDOR_QUANTENNA=y + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +CONFIG_NET_FAILOVER=y +# CONFIG_ISDN is not set # CONFIG_NVM is not set # @@ -494,7 +1360,10 @@ CONFIG_INPUT=y # # Userland interfaces # -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -502,8 +1371,53 @@ CONFIG_INPUT=y # # Input Device Drivers # -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_SMBUS=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -513,7 +1427,16 @@ CONFIG_INPUT=y # # Hardware I/O ports # -# CONFIG_SERIO is not set +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set # end of Hardware I/O ports # end of Input device support @@ -526,40 +1449,50 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_LDISC_AUTOLOAD is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LDISC_AUTOLOAD=y # # Serial drivers # CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set -# CONFIG_SERIAL_OF_PLATFORM is not set +CONFIG_SERIAL_OF_PLATFORM=y # # Non-8250 serial port support # +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set CONFIG_SERIAL_SIFIVE=y CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set # CONFIG_SERIAL_FSL_LPUART is not set # CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set @@ -567,15 +1500,28 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # end of Serial drivers # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_GOLDFISH_TTY is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set # CONFIG_TRACE_SINK is not set +CONFIG_HVC_DRIVER=y +CONFIG_HVC_RISCV_SBI=y # CONFIG_SERIAL_DEV_BUS is not set -# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_VIRTIO_CONSOLE=y # CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_DEVMEM is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set +CONFIG_HW_RANDOM_VIRTIO=y +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set +# CONFIG_APPLICOM is not set +CONFIG_DEVMEM=y # CONFIG_DEVKMEM is not set # CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # end of Character devices @@ -585,11 +1531,107 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # # I2C support # -# CONFIG_I2C is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set # end of I2C support # CONFIG_I3C is not set -# CONFIG_SPI is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MEM is not set + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SIFIVE=y +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set # CONFIG_SPMI is not set # CONFIG_HSI is not set # CONFIG_PPS is not set @@ -597,6 +1639,7 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # # PTP clock support # +# CONFIG_PTP_1588_CLOCK is not set # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -606,9 +1649,172 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_PINCTRL is not set # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set -# CONFIG_POWER_RESET is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +# CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_CHARGER_BD99954 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_DRIVETEMP is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -619,18 +1825,106 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_ATMEL_FLEXCOM is not set # CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set # CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set # CONFIG_ABX500_CORE is not set -# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set # CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set @@ -641,34 +1935,215 @@ CONFIG_BCMA_POSSIBLE=y # # Graphics support # -# CONFIG_DRM is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_DRM=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_TTM=y +CONFIG_DRM_TTM_DMA_PAGE_POOL=y +CONFIG_DRM_GEM_SHMEM_HELPER=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips # # ARM devices # +# CONFIG_DRM_KOMEDA is not set # end of ARM devices +CONFIG_DRM_RADEON=y +# CONFIG_DRM_RADEON_USERPTR is not set +# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_BOCHS is not set +CONFIG_DRM_VIRTIO_GPU=y +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +# CONFIG_DRM_DISPLAY_CONNECTOR is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_I2C_ADV7511 is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + # # Frame buffer Devices # -# CONFIG_FB is not set +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_EFI is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SM712 is not set # end of Frame buffer Devices # # Backlight & LCD device support # # CONFIG_LCD_CLASS_DEVICE is not set -# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set # end of Backlight & LCD device support +CONFIG_HDMI=y + # # Console display driver support # -# CONFIG_VGA_CONSOLE is not set +CONFIG_VGA_CONSOLE=y CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set # end of Console display driver support + +# CONFIG_LOGO is not set # end of Graphics support # CONFIG_SOUND is not set @@ -676,23 +2151,393 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 # # HID support # -# CONFIG_HID is not set +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_ULPI_BUS is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_GOLDFISH is not set +CONFIG_MMC_SPI=y +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_EFI is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_RTC_DRV_GOLDFISH=y # CONFIG_DMADEVICES is not set # # DMABUF options # CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set # CONFIG_DMABUF_SELFTESTS is not set # CONFIG_DMABUF_HEAPS is not set @@ -701,9 +2546,19 @@ CONFIG_SYNC_FILE=y # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_VIRT_DRIVERS is not set -# CONFIG_VIRTIO_MENU is not set +CONFIG_VIRTIO=y +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_INPUT=y +CONFIG_VIRTIO_MMIO=y +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=y # CONFIG_VDPA is not set -# CONFIG_VHOST_MENU is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support @@ -712,11 +2567,22 @@ CONFIG_SYNC_FILE=y # CONFIG_GREYBUS is not set # CONFIG_STAGING is not set -# CONFIG_GOLDFISH is not set +CONFIG_GOLDFISH=y +# CONFIG_GOLDFISH_PIPE is not set CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y CONFIG_CLK_SIFIVE=y @@ -733,7 +2599,14 @@ CONFIG_RISCV_TIMER=y # end of Clock Source drivers # CONFIG_MAILBOX is not set -# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set # # Remoteproc drivers @@ -744,7 +2617,9 @@ CONFIG_RISCV_TIMER=y # # Rpmsg drivers # -# CONFIG_RPMSG_VIRTIO is not set +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_VIRTIO=y # end of Rpmsg drivers # CONFIG_SOUNDWIRE is not set @@ -797,6 +2672,8 @@ CONFIG_RISCV_TIMER=y # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set # CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set # CONFIG_PWM is not set # @@ -815,6 +2692,7 @@ CONFIG_SIFIVE_PLIC=y # PHY Subsystem # # CONFIG_GENERIC_PHY is not set +# CONFIG_USB_LGM_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -823,11 +2701,13 @@ CONFIG_SIFIVE_PLIC=y # CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_OCELOT_SERDES is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set # CONFIG_MCB is not set # CONFIG_RAS is not set +# CONFIG_USB4 is not set # # Android @@ -835,8 +2715,10 @@ CONFIG_SIFIVE_PLIC=y # CONFIG_ANDROID is not set # end of Android +# CONFIG_LIBNVDIMM is not set # CONFIG_DAX is not set -# CONFIG_NVMEM is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y # # HW tracing support @@ -857,9 +2739,17 @@ CONFIG_SIFIVE_PLIC=y # File systems # # CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_XFS_FS is not set @@ -868,18 +2758,20 @@ CONFIG_SIFIVE_PLIC=y # CONFIG_NILFS2_FS is not set # CONFIG_F2FS_FS is not set # CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y -# CONFIG_MANDATORY_FILE_LOCKING is not set +CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y # CONFIG_FUSE_FS is not set # CONFIG_OVERLAY_FS is not set @@ -899,8 +2791,12 @@ CONFIG_FILE_LOCKING=y # # DOS/FAT/EXFAT/NT Filesystems # -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set # CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems @@ -912,17 +2808,128 @@ CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y -# CONFIG_PROC_CHILDREN is not set +CONFIG_PROC_CHILDREN=y CONFIG_KERNFS=y CONFIG_SYSFS=y -# CONFIG_TMPFS is not set +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set # CONFIG_HUGETLBFS is not set +CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y # CONFIG_CONFIGFS_FS is not set +CONFIG_EFIVAR_FS=m # end of Pseudo filesystems -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_NLS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=y +# CONFIG_9P_FS_POSIX_ACL is not set +# CONFIG_9P_FS_SECURITY is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set # CONFIG_UNICODE is not set CONFIG_IO_WQ=y # end of File systems @@ -930,7 +2937,11 @@ CONFIG_IO_WQ=y # # Security options # -# CONFIG_KEYS is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set @@ -954,8 +2965,171 @@ CONFIG_INIT_STACK_NONE=y # end of Kernel hardening options # end of Security options -# CONFIG_CRYPTO is not set -CONFIG_BINARY_PRINTF=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ENGINE=y + +# +# Public-key cryptography +# +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_ECHAINIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y + +# +# Crypto library routines +# +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +CONFIG_CRYPTO_DEV_VIRTIO=y +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking # # Library routines @@ -964,14 +3138,15 @@ CONFIG_BINARY_PRINTF=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y # CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set +CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC_ITU_T=y CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y @@ -980,13 +3155,34 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_BIT is not set # CONFIG_CRC64 is not set # CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set +CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set # CONFIG_CRC8 is not set +CONFIG_XXHASH=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y -# CONFIG_XZ_DEC is not set +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_INTERVAL_TREE=y +CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y @@ -995,12 +3191,23 @@ CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_SWIOTLB=y # CONFIG_DMA_API_DEBUG is not set +# CONFIG_CPUMASK_OFFSTACK is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y # CONFIG_IRQ_POLL is not set CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines @@ -1014,7 +3221,7 @@ CONFIG_GENERIC_IOREMAP=y # # printk and dmesg options # -# CONFIG_PRINTK_TIME is not set +CONFIG_PRINTK_TIME=y # CONFIG_PRINTK_CALLER is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 @@ -1022,27 +3229,22 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_DYNAMIC_DEBUG_CORE is not set -# CONFIG_SYMBOLIC_ERRNAME is not set +CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options # # Compile-time checks and compiler options # -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_INFO_REDUCED is not set -# CONFIG_DEBUG_INFO_COMPRESSED is not set -# CONFIG_DEBUG_INFO_SPLIT is not set -# CONFIG_DEBUG_INFO_DWARF4 is not set -# CONFIG_DEBUG_INFO_BTF is not set -CONFIG_GDB_SCRIPTS=y +# CONFIG_DEBUG_INFO is not set CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set @@ -1052,7 +3254,10 @@ CONFIG_FRAME_POINTER=y # Generic Kernel Debugging Instruments # # CONFIG_MAGIC_SYSRQ is not set -# CONFIG_DEBUG_FS is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y # CONFIG_KGDB is not set @@ -1060,20 +3265,21 @@ CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y # end of Generic Kernel Debugging Instruments CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_MISC is not set +CONFIG_DEBUG_MISC=y # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_DEBUG_PAGEALLOC=y +# CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set @@ -1090,10 +3296,9 @@ CONFIG_DEBUG_VM_PGTABLE=y CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_PER_CPU_MAPS=y CONFIG_HAVE_ARCH_KASAN=y -CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y -# CONFIG_KASAN is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -1106,23 +3311,24 @@ CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 -CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_WQ_WATCHDOG=y +# CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # -# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging -# CONFIG_DEBUG_TIMEKEEPING is not set +CONFIG_DEBUG_TIMEKEEPING=y # # Lock Debugging (spinlocks, mutexes, etc...) @@ -1130,13 +3336,13 @@ CONFIG_WQ_WATCHDOG=y CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_PROVE_LOCKING is not set # CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -# CONFIG_DEBUG_RWSEMS is not set +CONFIG_DEBUG_RWSEMS=y # CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_ATOMIC_SLEEP is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set @@ -1151,9 +3357,9 @@ CONFIG_STACKTRACE=y # # Debug kernel data structures # -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PLIST is not set -# CONFIG_DEBUG_SG is not set +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_PLIST=y +CONFIG_DEBUG_SG=y # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set # end of Debug kernel data structures @@ -1166,52 +3372,22 @@ CONFIG_STACKTRACE=y # CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_RCU_TRACE is not set -# CONFIG_RCU_EQS_DEBUG is not set +CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +CONFIG_DEBUG_BLOCK_EXT_DEVT=y # CONFIG_LATENCYTOP is not set -CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_TRACE_CLOCK=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_BOOTTIME_TRACING is not set -CONFIG_FUNCTION_TRACER=y -CONFIG_FUNCTION_GRAPH_TRACER=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_DYNAMIC_FTRACE_WITH_REGS=y -# CONFIG_FUNCTION_PROFILER is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_HWLAT_TRACER is not set -# CONFIG_FTRACE_SYSCALLS is not set -# CONFIG_TRACER_SNAPSHOT is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_FTRACE_MCOUNT_RECORD=y -# CONFIG_SYNTH_EVENTS is not set -# CONFIG_TRACE_EVENT_INJECT is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set # @@ -1228,6 +3404,6 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set -# CONFIG_MEMTEST is not set +CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/main.config b/wally-pipelined/linux-testgen/buildroot-config-src/main.config index 8f5779fb..7315007d 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/main.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/main.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Buildroot -g1cd7186-dirty Configuration +# Buildroot -g8d5e37d-dirty Configuration # BR2_HAVE_DOT_CONFIG=y @@ -430,8 +430,9 @@ BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.7" BR2_LINUX_KERNEL_VERSION="5.10.7" BR2_LINUX_KERNEL_PATCH="" # BR2_LINUX_KERNEL_USE_DEFCONFIG is not set -BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y -# BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG is not set +# BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="../buildroot-config-src/linux.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="" BR2_LINUX_KERNEL_CUSTOM_LOGO_PATH="" BR2_LINUX_KERNEL_IMAGE=y diff --git a/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog_debug b/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog_debug index f554fe67..b349fd88 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog_debug +++ b/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog_debug @@ -1,5 +1,5 @@ set pagination off -target extended-remote :1234 +target extended-remote :1236 maint print symbols symbols.txt b *0x000000008020103c c diff --git a/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh b/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh index 797b9f7d..52f0fe6f 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh +++ b/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh @@ -14,7 +14,7 @@ outDir="../linux-testvectors" # Uncomment this version for QEMU debugging of kernel # - good for poking around VM if it boots up # - good for running QEMU commands (press "Ctrl-A" then "c" to open QEMU command prompt) -#$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio +$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio # Uncomment this version for GDB debugging of kernel # - attempts to load in symbols from "vmlinux" # - good for looking at backtraces when Linux gets stuck for some reason @@ -41,4 +41,4 @@ outDir="../linux-testvectors" # =========== Just Do the Thing ========== # Uncomment this version for the whole thing # - Logs info needed by buildroot testbench -($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog +#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog From e922732fc589a733d5cc97b82ab7bc2dfcf83a7d Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 20:54:36 -0400 Subject: [PATCH 046/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 725 +----------------- 1 file changed, 5 insertions(+), 720 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index e66a329d..b007bb5a 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -24,7 +24,7 @@ CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HOSTNAME="WallyDefaultHostname" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -42,8 +42,6 @@ CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set @@ -405,7 +403,6 @@ CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y # end of Partition Types -CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y # @@ -543,8 +540,6 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_ATM is not set # CONFIG_L2TP is not set # CONFIG_BRIDGE is not set -CONFIG_HAVE_NET_DSA=y -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -619,77 +614,8 @@ CONFIG_HAVE_EBPF_JIT=y # Device Drivers # CONFIG_HAVE_PCI=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCIEPORTBUS=y -# CONFIG_PCIEAER is not set -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIE_PTM is not set -# CONFIG_PCIE_BW is not set -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_MSI_ARCH_FALLBACKS=y -CONFIG_PCI_QUIRKS=y -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_STUB is not set -CONFIG_PCI_ECAM=y -# CONFIG_PCI_IOV is not set -# CONFIG_PCI_PRI is not set -# CONFIG_PCI_PASID is not set -# CONFIG_PCIE_BUS_TUNE_OFF is not set -CONFIG_PCIE_BUS_DEFAULT=y -# CONFIG_PCIE_BUS_SAFE is not set -# CONFIG_PCIE_BUS_PERFORMANCE is not set -# CONFIG_PCIE_BUS_PEER2PEER is not set -# CONFIG_HOTPLUG_PCI is not set - -# -# PCI controller drivers -# -# CONFIG_PCI_FTPCI100 is not set -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCIE_XILINX=y - -# -# DesignWare PCI Core Support -# -# CONFIG_PCIE_DW_PLAT_HOST is not set -# CONFIG_PCI_MESON is not set -# end of DesignWare PCI Core Support - -# -# Mobiveil PCIe Core Support -# -# end of Mobiveil PCIe Core Support - -# -# Cadence PCIe controllers support -# -# CONFIG_PCIE_CADENCE_PLAT_HOST is not set -# CONFIG_PCI_J721E_HOST is not set -# end of Cadence PCIe controllers support -# end of PCI controller drivers - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set -# end of PCI Endpoint - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set -# end of PCI switch controller drivers - +# CONFIG_PCI is not set # CONFIG_PCCARD is not set -# CONFIG_RAPIDIO is not set # # Generic Driver Options @@ -739,33 +665,25 @@ CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y -CONFIG_OF_NET=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set -CONFIG_CDROM=y -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SKD is not set -# CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set # # NVME Support # -# CONFIG_BLK_DEV_NVME is not set # CONFIG_NVME_FC is not set # end of NVME Support @@ -774,11 +692,8 @@ CONFIG_VIRTIO_BLK=y # # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set -# CONFIG_PHANTOM is not set -# CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set # CONFIG_APDS9802ALS is not set # CONFIG_ISL29003 is not set # CONFIG_ISL29020 is not set @@ -789,7 +704,6 @@ CONFIG_VIRTIO_BLK=y # CONFIG_DS1682 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set -# CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set @@ -807,8 +721,6 @@ CONFIG_VIRTIO_BLK=y # CONFIG_EEPROM_EE1004 is not set # end of EEPROM support -# CONFIG_CB710_CORE is not set - # # Texas Instruments shared transport line discipline # @@ -817,12 +729,8 @@ CONFIG_VIRTIO_BLK=y # CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_ALTERA_STAPL is not set -# CONFIG_GENWQE is not set # CONFIG_ECHO is not set -# CONFIG_MISC_ALCOR_PCI is not set -# CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set -# CONFIG_HABANA_AI is not set # end of Misc devices # @@ -830,522 +738,13 @@ CONFIG_VIRTIO_BLK=y # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# end of SCSI Transports - -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_ISCSI_BOOT_SYSFS is not set -# CONFIG_SCSI_CXGB3_ISCSI is not set -# CONFIG_SCSI_CXGB4_ISCSI is not set -# CONFIG_SCSI_BNX2_ISCSI is not set -# CONFIG_BE2ISCSI is not set -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_HPSA is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_3W_SAS is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_MVSAS is not set -# CONFIG_SCSI_MVUMI is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_SCSI_ESAS2R is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_MPT3SAS is not set -# CONFIG_SCSI_MPT2SAS is not set -# CONFIG_SCSI_SMARTPQI is not set -# CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_MYRB is not set -# CONFIG_SCSI_MYRS is not set -# CONFIG_SCSI_SNIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FDOMAIN_PCI is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_WD719X is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_PMCRAID is not set -# CONFIG_SCSI_PM8001 is not set -CONFIG_SCSI_VIRTIO=y -# CONFIG_SCSI_DH is not set +# CONFIG_SCSI is not set # end of SCSI device support -CONFIG_ATA=y -CONFIG_SATA_HOST=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_ATA_FORCE=y -CONFIG_SATA_PMP=y - -# -# Controllers with non-SFF native interface -# -CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 -CONFIG_SATA_AHCI_PLATFORM=y -# CONFIG_AHCI_CEVA is not set -# CONFIG_AHCI_QORIQ is not set -# CONFIG_SATA_INIC162X is not set -# CONFIG_SATA_ACARD_AHCI is not set -# CONFIG_SATA_SIL24 is not set -CONFIG_ATA_SFF=y - -# -# SFF controllers with custom DMA interface -# -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set -# CONFIG_SATA_SX4 is not set -CONFIG_ATA_BMDMA=y - -# -# SATA SFF controllers with BMDMA -# -# CONFIG_ATA_PIIX is not set -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set -# CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_SVW is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set - -# -# PATA SFF controllers with BMDMA -# -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_ATP867X is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87415 is not set -# CONFIG_PATA_OLDPIIX is not set -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RDC is not set -# CONFIG_PATA_SCH is not set -# CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_TOSHIBA is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set - -# -# PIO-only SFF controllers -# -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_RZ1000 is not set - -# -# Generic fallback / legacy drivers -# -# CONFIG_ATA_GENERIC is not set -# CONFIG_PATA_LEGACY is not set +# CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_FIREWIRE_NOSY is not set -# end of IEEE 1394 (FireWire) support - -CONFIG_NETDEVICES=y -CONFIG_NET_CORE=y -# CONFIG_BONDING is not set -# CONFIG_DUMMY is not set -# CONFIG_WIREGUARD is not set -# CONFIG_EQUALIZER is not set -# CONFIG_NET_FC is not set -# CONFIG_NET_TEAM is not set -# CONFIG_MACVLAN is not set -# CONFIG_IPVLAN is not set -# CONFIG_VXLAN is not set -# CONFIG_GENEVE is not set -# CONFIG_BAREUDP is not set -# CONFIG_GTP is not set -# CONFIG_MACSEC is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_TUN is not set -# CONFIG_TUN_VNET_CROSS_LE is not set -# CONFIG_VETH is not set -CONFIG_VIRTIO_NET=y -# CONFIG_NLMON is not set -# CONFIG_ARCNET is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - -CONFIG_ETHERNET=y -CONFIG_NET_VENDOR_3COM=y -# CONFIG_VORTEX is not set -# CONFIG_TYPHOON is not set -CONFIG_NET_VENDOR_ADAPTEC=y -# CONFIG_ADAPTEC_STARFIRE is not set -CONFIG_NET_VENDOR_AGERE=y -# CONFIG_ET131X is not set -CONFIG_NET_VENDOR_ALACRITECH=y -# CONFIG_SLICOSS is not set -CONFIG_NET_VENDOR_ALTEON=y -# CONFIG_ACENIC is not set -# CONFIG_ALTERA_TSE is not set -CONFIG_NET_VENDOR_AMAZON=y -# CONFIG_ENA_ETHERNET is not set -CONFIG_NET_VENDOR_AMD=y -# CONFIG_AMD8111_ETH is not set -# CONFIG_PCNET32 is not set -CONFIG_NET_VENDOR_AQUANTIA=y -CONFIG_NET_VENDOR_ARC=y -CONFIG_NET_VENDOR_ATHEROS=y -# CONFIG_ATL2 is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL1C is not set -# CONFIG_ALX is not set -CONFIG_NET_VENDOR_AURORA=y -# CONFIG_AURORA_NB8800 is not set -CONFIG_NET_VENDOR_BROADCOM=y -# CONFIG_B44 is not set -# CONFIG_BCMGENET is not set -# CONFIG_BNX2 is not set -# CONFIG_CNIC is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2X is not set -# CONFIG_SYSTEMPORT is not set -# CONFIG_BNXT is not set -CONFIG_NET_VENDOR_BROCADE=y -# CONFIG_BNA is not set -CONFIG_NET_VENDOR_CADENCE=y -CONFIG_MACB=y -# CONFIG_MACB_PCI is not set -CONFIG_NET_VENDOR_CAVIUM=y -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_VF is not set -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_RGX is not set -# CONFIG_LIQUIDIO is not set -# CONFIG_LIQUIDIO_VF is not set -CONFIG_NET_VENDOR_CHELSIO=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHELSIO_T4 is not set -# CONFIG_CHELSIO_T4VF is not set -CONFIG_NET_VENDOR_CISCO=y -# CONFIG_ENIC is not set -CONFIG_NET_VENDOR_CORTINA=y -# CONFIG_GEMINI_ETHERNET is not set -# CONFIG_DNET is not set -CONFIG_NET_VENDOR_DEC=y -# CONFIG_NET_TULIP is not set -CONFIG_NET_VENDOR_DLINK=y -# CONFIG_DL2K is not set -# CONFIG_SUNDANCE is not set -CONFIG_NET_VENDOR_EMULEX=y -# CONFIG_BE2NET is not set -CONFIG_NET_VENDOR_EZCHIP=y -# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_GOOGLE=y -# CONFIG_GVE is not set -CONFIG_NET_VENDOR_HUAWEI=y -CONFIG_NET_VENDOR_I825XX=y -CONFIG_NET_VENDOR_INTEL=y -# CONFIG_E100 is not set -# CONFIG_E1000 is not set -CONFIG_E1000E=y -# CONFIG_IGB is not set -# CONFIG_IGBVF is not set -# CONFIG_IXGB is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGBEVF is not set -# CONFIG_I40E is not set -# CONFIG_I40EVF is not set -# CONFIG_ICE is not set -# CONFIG_FM10K is not set -# CONFIG_IGC is not set -# CONFIG_JME is not set -CONFIG_NET_VENDOR_MARVELL=y -# CONFIG_MVMDIO is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -CONFIG_NET_VENDOR_MELLANOX=y -# CONFIG_MLX4_EN is not set -# CONFIG_MLX5_CORE is not set -# CONFIG_MLXSW_CORE is not set -# CONFIG_MLXFW is not set -CONFIG_NET_VENDOR_MICREL=y -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_KSZ884X_PCI is not set -CONFIG_NET_VENDOR_MICROCHIP=y -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_LAN743X is not set -CONFIG_NET_VENDOR_MICROSEMI=y -CONFIG_NET_VENDOR_MYRI=y -# CONFIG_MYRI10GE is not set -# CONFIG_FEALNX is not set -CONFIG_NET_VENDOR_NATSEMI=y -# CONFIG_NATSEMI is not set -# CONFIG_NS83820 is not set -CONFIG_NET_VENDOR_NETERION=y -# CONFIG_S2IO is not set -# CONFIG_VXGE is not set -CONFIG_NET_VENDOR_NETRONOME=y -# CONFIG_NFP is not set -CONFIG_NET_VENDOR_NI=y -# CONFIG_NI_XGE_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_8390=y -# CONFIG_NE2K_PCI is not set -CONFIG_NET_VENDOR_NVIDIA=y -# CONFIG_FORCEDETH is not set -CONFIG_NET_VENDOR_OKI=y -# CONFIG_ETHOC is not set -CONFIG_NET_VENDOR_PACKET_ENGINES=y -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -CONFIG_NET_VENDOR_PENSANDO=y -# CONFIG_IONIC is not set -CONFIG_NET_VENDOR_QLOGIC=y -# CONFIG_QLA3XXX is not set -# CONFIG_QLCNIC is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_QED is not set -CONFIG_NET_VENDOR_QUALCOMM=y -# CONFIG_QCA7000_SPI is not set -# CONFIG_QCOM_EMAC is not set -# CONFIG_RMNET is not set -CONFIG_NET_VENDOR_RDC=y -# CONFIG_R6040 is not set -CONFIG_NET_VENDOR_REALTEK=y -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -CONFIG_R8169=y -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_NET_VENDOR_SAMSUNG=y -# CONFIG_SXGBE_ETH is not set -CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SOLARFLARE=y -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set -CONFIG_NET_VENDOR_SILAN=y -# CONFIG_SC92031 is not set -CONFIG_NET_VENDOR_SIS=y -# CONFIG_SIS900 is not set -# CONFIG_SIS190 is not set -CONFIG_NET_VENDOR_SMSC=y -# CONFIG_EPIC100 is not set -# CONFIG_SMSC911X is not set -# CONFIG_SMSC9420 is not set -CONFIG_NET_VENDOR_SOCIONEXT=y -CONFIG_NET_VENDOR_STMICRO=y -# CONFIG_STMMAC_ETH is not set -CONFIG_NET_VENDOR_SUN=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NIU is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_DWC_XLGMAC is not set -CONFIG_NET_VENDOR_TEHUTI=y -# CONFIG_TEHUTI is not set -CONFIG_NET_VENDOR_TI=y -# CONFIG_TI_CPSW_PHY_SEL is not set -# CONFIG_TLAN is not set -CONFIG_NET_VENDOR_VIA=y -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -CONFIG_NET_VENDOR_WIZNET=y -# CONFIG_WIZNET_W5100 is not set -# CONFIG_WIZNET_W5300 is not set -CONFIG_NET_VENDOR_XILINX=y -# CONFIG_XILINX_AXI_EMAC is not set -# CONFIG_XILINX_LL_TEMAC is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PHYLINK=y -CONFIG_PHYLIB=y -CONFIG_SWPHY=y -CONFIG_FIXED_PHY=y -# CONFIG_SFP is not set - -# -# MII PHY device drivers -# -# CONFIG_AMD_PHY is not set -# CONFIG_ADIN_PHY is not set -# CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BCM54140_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM84881_PHY is not set -# CONFIG_BCM87XX_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_CORTINA_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_INTEL_XWAY_PHY is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MARVELL_10G_PHY is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_MICROCHIP_PHY is not set -# CONFIG_MICROCHIP_T1_PHY is not set -CONFIG_MICROSEMI_PHY=y -# CONFIG_NATIONAL_PHY is not set -# CONFIG_NXP_TJA11XX_PHY is not set -# CONFIG_QSEMI_PHY is not set -CONFIG_REALTEK_PHY=y -# CONFIG_RENESAS_PHY is not set -# CONFIG_ROCKCHIP_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_DP83869_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_XILINX_GMII2RGMII is not set -# CONFIG_MICREL_KS8995MA is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -CONFIG_OF_MDIO=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_HISI_FEMAC is not set -# CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_OCTEON is not set -# CONFIG_MDIO_IPQ4019 is not set -# CONFIG_MDIO_IPQ8064 is not set -# CONFIG_MDIO_THUNDER is not set - -# -# MDIO Multiplexers -# -# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set - -# -# PCS device drivers -# -# CONFIG_PCS_XPCS is not set -# end of PCS device drivers - -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -CONFIG_USB_NET_DRIVERS=y -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_RTL8152 is not set -# CONFIG_USB_LAN78XX is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_IPHETH is not set -CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set -CONFIG_WLAN_VENDOR_ADMTEK=y -CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set -# CONFIG_ATH5K_PCI is not set -CONFIG_WLAN_VENDOR_ATMEL=y -CONFIG_WLAN_VENDOR_BROADCOM=y -CONFIG_WLAN_VENDOR_CISCO=y -CONFIG_WLAN_VENDOR_INTEL=y -CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set -# CONFIG_PRISM54 is not set -CONFIG_WLAN_VENDOR_MARVELL=y -CONFIG_WLAN_VENDOR_MEDIATEK=y -CONFIG_WLAN_VENDOR_MICROCHIP=y -CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_WLAN_VENDOR_REALTEK=y -CONFIG_WLAN_VENDOR_RSI=y -CONFIG_WLAN_VENDOR_ST=y -CONFIG_WLAN_VENDOR_TI=y -CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_WLAN_VENDOR_QUANTENNA=y - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_VMXNET3 is not set -# CONFIG_NETDEVSIM is not set -CONFIG_NET_FAILOVER=y -# CONFIG_ISDN is not set +# CONFIG_NETDEVICES is not set # CONFIG_NVM is not set # @@ -1429,7 +828,6 @@ CONFIG_MOUSE_PS2_SMBUS=y # CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_SERIO_ALTERA_PS2 is not set @@ -1464,8 +862,6 @@ CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set @@ -1483,7 +879,6 @@ CONFIG_SERIAL_EARLYCON_RISCV_SBI=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set CONFIG_SERIAL_SIFIVE=y CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_SCCNXP is not set @@ -1492,7 +887,6 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set -# CONFIG_SERIAL_RP2 is not set # CONFIG_SERIAL_FSL_LPUART is not set # CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set @@ -1502,7 +896,6 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_GOLDFISH_TTY is not set # CONFIG_N_GSM is not set -# CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set # CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y @@ -1517,11 +910,9 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set -# CONFIG_APPLICOM is not set CONFIG_DEVMEM=y # CONFIG_DEVKMEM is not set # CONFIG_RAW_DRIVER is not set -CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # end of Character devices @@ -1543,30 +934,10 @@ CONFIG_I2C_ALGOBIT=y # I2C Hardware Bus support # -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_NVIDIA_GPU is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set - # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set # CONFIG_I2C_EMEV2 is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set @@ -1610,7 +981,6 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_FSL_SPI is not set -# CONFIG_SPI_PXA2XX is not set # CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set CONFIG_SPI_SIFIVE=y @@ -1706,10 +1076,8 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set -# CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set @@ -1777,7 +1145,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set # CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_EMC1403 is not set # CONFIG_SENSORS_EMC2103 is not set @@ -1802,9 +1169,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_TMP513 is not set -# CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83773G is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set @@ -1849,10 +1214,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set # CONFIG_MFD_IQS62X is not set -# CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set @@ -1875,7 +1237,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_VIPERBOARD is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_RDC321X is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RK808 is not set @@ -1910,7 +1271,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_LM3533 is not set # CONFIG_MFD_TC3589X is not set # CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_VX855 is not set # CONFIG_MFD_LOCHNAGAR is not set # CONFIG_MFD_ARIZONA_I2C is not set # CONFIG_MFD_ARIZONA_SPI is not set @@ -1935,8 +1295,6 @@ CONFIG_MFD_SYSCON=y # # Graphics support # -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_DRM=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_MM is not set @@ -1949,8 +1307,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set # CONFIG_DRM_DP_CEC is not set -CONFIG_DRM_TTM=y -CONFIG_DRM_TTM_DMA_PAGE_POOL=y CONFIG_DRM_GEM_SHMEM_HELPER=y # @@ -1968,19 +1324,11 @@ CONFIG_DRM_GEM_SHMEM_HELPER=y # CONFIG_DRM_KOMEDA is not set # end of ARM devices -CONFIG_DRM_RADEON=y -# CONFIG_DRM_RADEON_USERPTR is not set -# CONFIG_DRM_AMDGPU is not set -# CONFIG_DRM_NOUVEAU is not set # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set # CONFIG_DRM_UDL is not set -# CONFIG_DRM_AST is not set -# CONFIG_DRM_MGAG200 is not set # CONFIG_DRM_RCAR_DW_HDMI is not set # CONFIG_DRM_RCAR_LVDS is not set -# CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set CONFIG_DRM_VIRTIO_GPU=y CONFIG_DRM_PANEL=y @@ -2041,7 +1389,6 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set @@ -2076,42 +1423,16 @@ CONFIG_FB_DEFERRED_IO=y # # Frame buffer hardware drivers # -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set # CONFIG_FB_EFI is not set # CONFIG_FB_OPENCORES is not set # CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_GOLDFISH is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set # CONFIG_FB_SIMPLE is not set -# CONFIG_FB_SM712 is not set # end of Frame buffer Devices # @@ -2258,7 +1579,6 @@ CONFIG_USB_COMMON=y # CONFIG_USB_ULPI_BUS is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y -CONFIG_USB_PCI=y # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # @@ -2278,13 +1598,11 @@ CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_C67X00_HCD is not set CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_DBGCAP is not set -CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_ROOT_HUB_TT is not set CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_EHCI_PCI=y # CONFIG_USB_EHCI_FSL is not set CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set @@ -2292,9 +1610,7 @@ CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_MAX3421_HCD is not set CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y CONFIG_USB_OHCI_HCD_PLATFORM=y -# CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_HCD_TEST_MODE is not set @@ -2314,28 +1630,11 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y # # also be needed; see USB_STORAGE Help for more info # -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_REALTEK is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_STORAGE_ENE_UB6250 is not set -CONFIG_USB_UAS=y # # USB Imaging devices # # CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set # CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set @@ -2402,18 +1701,14 @@ CONFIG_MMC_BLOCK_MINORS=8 # # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_TIFM_SD is not set # CONFIG_MMC_GOLDFISH is not set CONFIG_MMC_SPI=y -# CONFIG_MMC_CB710 is not set -# CONFIG_MMC_VIA_SDMMC is not set # CONFIG_MMC_DW is not set # CONFIG_MMC_VUB300 is not set # CONFIG_MMC_USHC is not set # CONFIG_MMC_USDHI6ROL0 is not set # CONFIG_MMC_CQHCI is not set # CONFIG_MMC_HSQ is not set -# CONFIG_MMC_TOSHIBA_PCI is not set # CONFIG_MMC_MTK is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -2548,8 +1843,6 @@ CONFIG_SYNC_FILE=y # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO=y CONFIG_VIRTIO_MENU=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y @@ -2672,8 +1965,6 @@ CONFIG_RPMSG_VIRTIO=y # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set # CONFIG_IIO is not set -# CONFIG_NTB is not set -# CONFIG_VME_BUS is not set # CONFIG_PWM is not set # @@ -2707,7 +1998,6 @@ CONFIG_SIFIVE_PLIC=y # CONFIG_POWERCAP is not set # CONFIG_MCB is not set # CONFIG_RAS is not set -# CONFIG_USB4 is not set # # Android @@ -3118,7 +2408,6 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set -# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set CONFIG_CRYPTO_DEV_VIRTIO=y # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set @@ -3181,7 +2470,6 @@ CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y -CONFIG_INTERVAL_TREE=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -3194,8 +2482,6 @@ CONFIG_SWIOTLB=y # CONFIG_CPUMASK_OFFSTACK is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y -CONFIG_GLOB=y -# CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y # CONFIG_IRQ_POLL is not set CONFIG_LIBFDT=y @@ -3207,7 +2493,6 @@ CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y -CONFIG_SG_POOL=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines From 03e0bdaa5a32e5fea465465b450dec7adf28882e Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 21:33:52 -0400 Subject: [PATCH 047/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 217 +----------------- 1 file changed, 5 insertions(+), 212 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index b007bb5a..d46f9162 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -28,12 +28,9 @@ CONFIG_DEFAULT_HOSTNAME="WallyDefaultHostname" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set -# CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # @@ -75,7 +72,6 @@ CONFIG_PREEMPT_COUNT=y CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set # CONFIG_PSI is not set # end of CPU/Task time and stats accounting @@ -130,7 +126,6 @@ CONFIG_UTS_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y -CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set @@ -337,7 +332,6 @@ CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y @@ -465,149 +459,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_DIAG is not set -CONFIG_UNIX=y -CONFIG_UNIX_SCM=y -# CONFIG_UNIX_DIAG is not set -# CONFIG_TLS is not set -# CONFIG_XFRM_USER is not set -# CONFIG_NET_KEY is not set -# CONFIG_XDP_SOCKETS is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_FIB_TRIE_STATS is not set -# CONFIG_IP_MULTIPLE_TABLES is not set -# CONFIG_IP_ROUTE_MULTIPATH is not set -# CONFIG_IP_ROUTE_VERBOSE is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=y -# CONFIG_IP_MROUTE is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_NET_IPVTI is not set -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_INET_UDP_DIAG is not set -# CONFIG_INET_RAW_DIAG is not set -# CONFIG_INET_DIAG_DESTROY is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_IPV6_VTI is not set -CONFIG_IPV6_SIT=y -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_IPV6_SEG6_LWTUNNEL is not set -# CONFIG_IPV6_SEG6_HMAC is not set -# CONFIG_IPV6_RPL_LWTUNNEL is not set -# CONFIG_MPTCP is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set -# CONFIG_NETFILTER is not set -# CONFIG_BPFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_L2TP is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_PHONET is not set -# CONFIG_6LOWPAN is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set -CONFIG_DNS_RESOLVER=y -# CONFIG_BATMAN_ADV is not set -# CONFIG_OPENVSWITCH is not set -# CONFIG_VSOCKETS is not set -CONFIG_NETLINK_DIAG=y -# CONFIG_MPLS is not set -# CONFIG_NET_NSH is not set -# CONFIG_HSR is not set -# CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_L3_MASTER_DEV is not set -# CONFIG_QRTR is not set -# CONFIG_NET_NCSI is not set -CONFIG_RPS=y -CONFIG_RFS_ACCEL=y -CONFIG_XPS=y -# CONFIG_CGROUP_NET_PRIO is not set -# CONFIG_CGROUP_NET_CLASSID is not set -CONFIG_NET_RX_BUSY_POLL=y -CONFIG_BQL=y -# CONFIG_BPF_JIT is not set -# CONFIG_BPF_STREAM_PARSER is not set -CONFIG_NET_FLOW_LIMIT=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# end of Network testing -# end of Networking options - -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_AF_KCM is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y -# CONFIG_NET_9P_DEBUG is not set -# CONFIG_CAIF is not set -# CONFIG_CEPH_LIB is not set -# CONFIG_NFC is not set -# CONFIG_PSAMPLE is not set -# CONFIG_NET_IFE is not set -# CONFIG_LWTUNNEL is not set -CONFIG_DST_CACHE=y -CONFIG_GRO_CELLS=y -CONFIG_FAILOVER=y -CONFIG_ETHTOOL_NETLINK=y +# CONFIG_NET is not set CONFIG_HAVE_EBPF_JIT=y # @@ -654,7 +506,6 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # CONFIG_MHI_BUS is not set # end of Bus devices -# CONFIG_CONNECTOR is not set # CONFIG_GNSS is not set # CONFIG_MTD is not set CONFIG_DTC=y @@ -673,13 +524,13 @@ CONFIG_BLK_DEV=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set + +# +# DRBD disabled because PROC_FS or INET not selected +# # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y -# CONFIG_BLK_DEV_RBD is not set # # NVME Support @@ -744,7 +595,6 @@ CONFIG_SCSI_MOD=y # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set -# CONFIG_NETDEVICES is not set # CONFIG_NVM is not set # @@ -895,7 +745,6 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_GOLDFISH_TTY is not set -# CONFIG_N_GSM is not set # CONFIG_NULL_TTY is not set # CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y @@ -1009,7 +858,6 @@ CONFIG_SPI_SIFIVE=y # # PTP clock support # -# CONFIG_PTP_1588_CLOCK is not set # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. @@ -1635,7 +1483,6 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y # USB Imaging devices # # CONFIG_USB_MDC800 is not set -# CONFIG_USBIP_CORE is not set # CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set @@ -1713,7 +1560,6 @@ CONFIG_MMC_SPI=y # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y @@ -1850,7 +1696,6 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_DMA_SHARED_BUFFER=y # CONFIG_VDPA is not set CONFIG_VHOST_MENU=y -# CONFIG_VHOST_NET is not set # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # @@ -1911,7 +1756,6 @@ CONFIG_IOMMU_SUPPORT=y # Rpmsg drivers # CONFIG_RPMSG=y -CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_VIRTIO=y # end of Rpmsg drivers @@ -2135,40 +1979,6 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V2=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_SWAP is not set -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_PNFS_FILE_LAYOUT=y -CONFIG_PNFS_FLEXFILE_LAYOUT=m -CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" -# CONFIG_NFS_V4_1_MIGRATION is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_USE_KERNEL_DNS=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -# CONFIG_NFS_V4_2_READ_PLUS is not set -# CONFIG_NFSD is not set -CONFIG_GRACE_PERIOD=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_SUNRPC_BACKCHANNEL=y -# CONFIG_SUNRPC_DEBUG is not set -# CONFIG_CEPH_FS is not set -# CONFIG_CIFS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -CONFIG_9P_FS=y -# CONFIG_9P_FS_POSIX_ACL is not set -# CONFIG_9P_FS_SECURITY is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set @@ -2270,7 +2080,6 @@ CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG2=y # CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_USER is not set CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y # CONFIG_CRYPTO_NULL is not set CONFIG_CRYPTO_NULL2=y @@ -2356,21 +2165,16 @@ CONFIG_CRYPTO_CRC32C=y # # CONFIG_CRYPTO_AES is not set # CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set -# CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # @@ -2389,12 +2193,6 @@ CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_DRBG_MENU is not set # CONFIG_CRYPTO_JITTERENTROPY is not set -CONFIG_CRYPTO_USER_API=y -CONFIG_CRYPTO_USER_API_HASH=y -# CONFIG_CRYPTO_USER_API_SKCIPHER is not set -# CONFIG_CRYPTO_USER_API_RNG is not set -# CONFIG_CRYPTO_USER_API_AEAD is not set -CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # # Crypto library routines @@ -2427,7 +2225,6 @@ CONFIG_CRYPTO_DEV_VIRTIO=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_NET_UTILS=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -2480,12 +2277,8 @@ CONFIG_DMA_DECLARE_COHERENT=y CONFIG_SWIOTLB=y # CONFIG_DMA_API_DEBUG is not set # CONFIG_CPUMASK_OFFSTACK is not set -CONFIG_CPU_RMAP=y -CONFIG_DQL=y -CONFIG_NLATTR=y # CONFIG_IRQ_POLL is not set CONFIG_LIBFDT=y -CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y From 8586462ee5f251acc35bbb44ea5f432a41560a4e Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 23:00:20 -0400 Subject: [PATCH 048/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 336 +----------------- 1 file changed, 4 insertions(+), 332 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index d46f9162..77647b0c 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -502,7 +502,6 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # # Bus devices # -# CONFIG_MOXTET is not set # CONFIG_MHI_BUS is not set # end of Bus devices @@ -553,7 +552,6 @@ CONFIG_VIRTIO_BLK=y # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set @@ -563,11 +561,9 @@ CONFIG_VIRTIO_BLK=y # EEPROM support # # CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set -# CONFIG_EEPROM_93XX46 is not set # CONFIG_EEPROM_IDT_89HPESX is not set # CONFIG_EEPROM_EE1004 is not set # end of EEPROM support @@ -577,11 +573,9 @@ CONFIG_VIRTIO_BLK=y # # end of Texas Instruments shared transport line discipline -# CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_ALTERA_STAPL is not set # CONFIG_ECHO is not set -# CONFIG_MISC_RTSX_USB is not set # end of Misc devices # @@ -660,13 +654,10 @@ CONFIG_MOUSE_PS2_TRACKPOINT=y CONFIG_MOUSE_PS2_FOCALTECH=y CONFIG_MOUSE_PS2_SMBUS=y # CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_CYAPA is not set # CONFIG_MOUSE_ELAN_I2C is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_SYNAPTICS_USB is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -724,8 +715,6 @@ CONFIG_SERIAL_OF_PLATFORM=y # Non-8250 serial port support # CONFIG_SERIAL_EARLYCON_RISCV_SBI=y -# CONFIG_SERIAL_MAX3100 is not set -# CONFIG_SERIAL_MAX310X is not set # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y @@ -797,10 +786,7 @@ CONFIG_I2C_ALGOBIT=y # # External I2C/SMBus adapter drivers # -# CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set # # Other I2C/SMBus bus drivers @@ -815,42 +801,7 @@ CONFIG_I2C_ALGOBIT=y # end of I2C support # CONFIG_I3C is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y -# CONFIG_SPI_MEM is not set - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_ALTERA is not set -# CONFIG_SPI_AXI_SPI_ENGINE is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_CADENCE is not set -# CONFIG_SPI_DESIGNWARE is not set -# CONFIG_SPI_NXP_FLEXSPI is not set -# CONFIG_SPI_FSL_SPI is not set -# CONFIG_SPI_ROCKCHIP is not set -# CONFIG_SPI_SC18IS602 is not set -CONFIG_SPI_SIFIVE=y -# CONFIG_SPI_MXIC is not set -# CONFIG_SPI_XCOMM is not set -# CONFIG_SPI_XILINX is not set -# CONFIG_SPI_ZYNQMP_GQSPI is not set -# CONFIG_SPI_AMD is not set - -# -# SPI Multiplexer support -# -# CONFIG_SPI_MUX is not set - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_LOOPBACK_TEST is not set -# CONFIG_SPI_TLE62X0 is not set -# CONFIG_SPI_SLAVE is not set +# CONFIG_SPI is not set # CONFIG_SPMI is not set # CONFIG_HSI is not set # CONFIG_PPS is not set @@ -902,7 +853,6 @@ CONFIG_HWMON=y # # Native drivers # -# CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set @@ -912,7 +862,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7310 is not set # CONFIG_SENSORS_ADT7410 is not set # CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set @@ -923,7 +872,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -940,7 +888,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -948,12 +895,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX31722 is not set # CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set @@ -964,9 +909,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set # CONFIG_SENSORS_MR75203 is not set -# CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set # CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set @@ -1004,7 +947,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set # CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_ADS7871 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set # CONFIG_SENSORS_INA2XX is not set @@ -1049,15 +991,12 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_AXP20X_I2C is not set # CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_SPI is not set # CONFIG_MFD_DA9052_I2C is not set # CONFIG_MFD_DA9055 is not set # CONFIG_MFD_DA9062 is not set # CONFIG_MFD_DA9063 is not set # CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set # CONFIG_MFD_GATEWORKS_GSC is not set -# CONFIG_MFD_MC13XXX_SPI is not set # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set @@ -1080,9 +1019,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_CPCAP is not set -# CONFIG_MFD_VIPERBOARD is not set # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_RT5033 is not set @@ -1111,7 +1047,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TPS65218 is not set # CONFIG_MFD_TPS6586X is not set # CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS65912_SPI is not set # CONFIG_MFD_TPS80031 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_TWL6040_CORE is not set @@ -1121,10 +1056,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TQMX86 is not set # CONFIG_MFD_LOCHNAGAR is not set # CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_ARIZONA_SPI is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set @@ -1132,7 +1065,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set -# CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set @@ -1174,7 +1106,6 @@ CONFIG_DRM_GEM_SHMEM_HELPER=y # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set -# CONFIG_DRM_UDL is not set # CONFIG_DRM_RCAR_DW_HDMI is not set # CONFIG_DRM_RCAR_LVDS is not set CONFIG_DRM_VIRTIO_GPU=y @@ -1186,17 +1117,11 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_SIMPLE is not set -# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set -# CONFIG_DRM_PANEL_LG_LG4573 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # end of Display Panels CONFIG_DRM_BRIDGE=y @@ -1237,15 +1162,6 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_GM12U320 is not set -# CONFIG_TINYDRM_HX8357D is not set -# CONFIG_TINYDRM_ILI9225 is not set -# CONFIG_TINYDRM_ILI9341 is not set -# CONFIG_TINYDRM_ILI9486 is not set -# CONFIG_TINYDRM_MI0283QT is not set -# CONFIG_TINYDRM_REPAPER is not set -# CONFIG_TINYDRM_ST7586 is not set -# CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -1274,8 +1190,6 @@ CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_EFI is not set # CONFIG_FB_OPENCORES is not set # CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_SMSCUFX is not set -# CONFIG_FB_UDL is not set # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_GOLDFISH is not set # CONFIG_FB_VIRTUAL is not set @@ -1320,99 +1234,7 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # # HID support # -CONFIG_HID=y -# CONFIG_HID_BATTERY_STRENGTH is not set -# CONFIG_HIDRAW is not set -# CONFIG_UHID is not set -CONFIG_HID_GENERIC=y - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_ACCUTOUCH is not set -# CONFIG_HID_ACRUX is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_AUREAL is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_COUGAR is not set -# CONFIG_HID_MACALLY is not set -# CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CREATIVE_SB0540 is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EMS_FF is not set -# CONFIG_HID_ELECOM is not set -# CONFIG_HID_ELO is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_GLORIOUS is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_VIVALDI is not set -# CONFIG_HID_KEYTOUCH is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_WALTOP is not set -# CONFIG_HID_VIEWSONIC is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_ICADE is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_JABRA is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LENOVO is not set -# CONFIG_HID_MAGICMOUSE is not set -# CONFIG_HID_MALTRON is not set -# CONFIG_HID_MAYFLASH is not set -# CONFIG_HID_REDRAGON is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_MULTITOUCH is not set -# CONFIG_HID_NTI is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set -# CONFIG_HID_PLANTRONICS is not set -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_RETRODE is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SPEEDLINK is not set -# CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_RMI is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_UDRAW_PS3 is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_ALPS is not set -# end of Special HID drivers - -# -# USB HID support -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set -# end of USB HID support +# CONFIG_HID is not set # # I2C HID support @@ -1422,141 +1244,8 @@ CONFIG_USB_HID=y # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_COMMON=y -# CONFIG_USB_ULPI_BUS is not set -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB=y -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_FEW_INIT_RETRIES is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG_PRODUCTLIST is not set -# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -CONFIG_USB_AUTOSUSPEND_DELAY=2 -# CONFIG_USB_MON is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_DBGCAP is not set -# CONFIG_USB_XHCI_PCI_RENESAS is not set -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_EHCI_FSL is not set -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set -# CONFIG_USB_MAX3421_HCD is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HCD_TEST_MODE is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_CDNS3 is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_DWC3 is not set -# CONFIG_USB_DWC2 is not set -# CONFIG_USB_CHIPIDEA is not set -# CONFIG_USB_ISP1760 is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_APPLE_MFI_FASTCHARGE is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_EHSET_TEST_FIXTURE is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_YUREX is not set -# CONFIG_USB_EZUSB_FX2 is not set -# CONFIG_USB_HUB_USB251XB is not set -# CONFIG_USB_HSIC_USB3503 is not set -# CONFIG_USB_HSIC_USB4604 is not set -# CONFIG_USB_LINK_LAYER_TEST is not set -# CONFIG_USB_CHAOSKEY is not set - -# -# USB Physical Layer drivers -# -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_USB_ISP1301 is not set -# end of USB Physical Layer drivers - -# CONFIG_USB_GADGET is not set -# CONFIG_TYPEC is not set -# CONFIG_USB_ROLE_SWITCH is not set -CONFIG_MMC=y -CONFIG_PWRSEQ_EMMC=y -CONFIG_PWRSEQ_SIMPLE=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=8 -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_GOLDFISH is not set -CONFIG_MMC_SPI=y -# CONFIG_MMC_DW is not set -# CONFIG_MMC_VUB300 is not set -# CONFIG_MMC_USHC is not set -# CONFIG_MMC_USDHI6ROL0 is not set -# CONFIG_MMC_CQHCI is not set -# CONFIG_MMC_HSQ is not set -# CONFIG_MMC_MTK is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set @@ -1616,21 +1305,6 @@ CONFIG_RTC_INTF_DEV=y # # SPI RTC drivers # -# CONFIG_RTC_DRV_M41T93 is not set -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1302 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1343 is not set -# CONFIG_RTC_DRV_DS1347 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6916 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_PCF2123 is not set -# CONFIG_RTC_DRV_MCP795 is not set CONFIG_RTC_I2C_AND_SPI=y # @@ -1827,7 +1501,6 @@ CONFIG_SIFIVE_PLIC=y # PHY Subsystem # # CONFIG_GENERIC_PHY is not set -# CONFIG_USB_LGM_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set @@ -2266,7 +1939,6 @@ CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y CONFIG_DECOMPRESS_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y From 3ff723493f62e462ff192958af35f3acd76a5585 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 23:12:21 -0400 Subject: [PATCH 049/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 77647b0c..606865f5 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -518,18 +518,7 @@ CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set # CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS or INET not selected -# -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_VIRTIO_BLK=y +# CONFIG_BLK_DEV is not set # # NVME Support @@ -1522,7 +1511,6 @@ CONFIG_SIFIVE_PLIC=y # CONFIG_ANDROID is not set # end of Android -# CONFIG_LIBNVDIMM is not set # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y From e565adfece33fdc302c485edb7143bfed6196d99 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 23:30:24 -0400 Subject: [PATCH 050/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 282 ++---------------- 1 file changed, 18 insertions(+), 264 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 606865f5..d0354b90 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -494,8 +494,6 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y # end of Generic Driver Options @@ -751,11 +749,19 @@ CONFIG_DEVMEM=y # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y +# CONFIG_I2C_COMPAT is not set # CONFIG_I2C_CHARDEV is not set # CONFIG_I2C_MUX is not set -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set +# end of I2C Algorithms # # I2C Hardware Bus support @@ -815,7 +821,6 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y # CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set -CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set @@ -836,129 +841,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_CHARGER_BD99954 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM1177 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_AS370 is not set -# CONFIG_SENSORS_ASC7621 is not set -# CONFIG_SENSORS_AXI_FAN_CONTROL is not set -# CONFIG_SENSORS_ASPEED is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS620 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_HIH6130 is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX31730 is not set -# CONFIG_SENSORS_MAX6621 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_MAX31790 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_TC654 is not set -# CONFIG_SENSORS_MR75203 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95234 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LM95245 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NPCM7XX is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_PMBUS is not set -# CONFIG_SENSORS_SHT21 is not set -# CONFIG_SENSORS_SHT3x is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_EMC1403 is not set -# CONFIG_SENSORS_EMC2103 is not set -# CONFIG_SENSORS_EMC6W201 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_STTS751 is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_AMC6821 is not set -# CONFIG_SENSORS_INA209 is not set -# CONFIG_SENSORS_INA2XX is not set -# CONFIG_SENSORS_INA3221 is not set -# CONFIG_SENSORS_TC74 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP102 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_SENSORS_TMP108 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_TMP513 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83773G is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83795 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -1064,158 +947,34 @@ CONFIG_MFD_SYSCON=y # # Graphics support # -CONFIG_DRM=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_MM is not set -# CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y -# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set -# CONFIG_DRM_DP_CEC is not set -CONFIG_DRM_GEM_SHMEM_HELPER=y - -# -# I2C encoder or helper chips -# -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# end of I2C encoder or helper chips +# CONFIG_DRM is not set # # ARM devices # -# CONFIG_DRM_KOMEDA is not set # end of ARM devices -# CONFIG_DRM_VGEM is not set -# CONFIG_DRM_VKMS is not set -# CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set -CONFIG_DRM_VIRTIO_GPU=y -CONFIG_DRM_PANEL=y - -# -# Display Panels -# -# CONFIG_DRM_PANEL_ARM_VERSATILE is not set -# CONFIG_DRM_PANEL_LVDS is not set -# CONFIG_DRM_PANEL_SIMPLE is not set -# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set -# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set -# end of Display Panels - -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_PANEL_BRIDGE=y - -# -# Display Interface Bridges -# -# CONFIG_DRM_CDNS_DSI is not set -# CONFIG_DRM_CHRONTEL_CH7033 is not set -# CONFIG_DRM_DISPLAY_CONNECTOR is not set -# CONFIG_DRM_LONTIUM_LT9611 is not set -# CONFIG_DRM_LVDS_CODEC is not set -# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set -# CONFIG_DRM_NWL_MIPI_DSI is not set -# CONFIG_DRM_NXP_PTN3460 is not set -# CONFIG_DRM_PARADE_PS8622 is not set -# CONFIG_DRM_PARADE_PS8640 is not set -# CONFIG_DRM_SIL_SII8620 is not set -# CONFIG_DRM_SII902X is not set -# CONFIG_DRM_SII9234 is not set -# CONFIG_DRM_SIMPLE_BRIDGE is not set -# CONFIG_DRM_THINE_THC63LVD1024 is not set -# CONFIG_DRM_TOSHIBA_TC358762 is not set -# CONFIG_DRM_TOSHIBA_TC358764 is not set -# CONFIG_DRM_TOSHIBA_TC358767 is not set -# CONFIG_DRM_TOSHIBA_TC358768 is not set -# CONFIG_DRM_TOSHIBA_TC358775 is not set -# CONFIG_DRM_TI_TFP410 is not set -# CONFIG_DRM_TI_SN65DSI86 is not set -# CONFIG_DRM_TI_TPD12S015 is not set -# CONFIG_DRM_ANALOGIX_ANX6345 is not set -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# CONFIG_DRM_I2C_ADV7511 is not set -# CONFIG_DRM_CDNS_MHDP8546 is not set -# end of Display Interface Bridges - -# CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set -# CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y - # # Frame buffer Devices # -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_EFI is not set -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_GOLDFISH is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_SIMPLE is not set +# CONFIG_FB is not set # end of Frame buffer Devices # # Backlight & LCD device support # # CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_QCOM_WLED is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_LM3639 is not set -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set # end of Backlight & LCD device support -CONFIG_HDMI=y - # # Console display driver support # -CONFIG_VGA_CONSOLE=y +# CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set # end of Console display driver support - -# CONFIG_LOGO is not set # end of Graphics support # CONFIG_SOUND is not set @@ -1339,11 +1098,8 @@ CONFIG_RTC_DRV_GOLDFISH=y # # DMABUF options # -CONFIG_SYNC_FILE=y -# CONFIG_SW_SYNC is not set -# CONFIG_UDMABUF is not set +# CONFIG_SYNC_FILE is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_SELFTESTS is not set # CONFIG_DMABUF_HEAPS is not set # end of DMABUF options @@ -1356,7 +1112,6 @@ CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y # CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -CONFIG_VIRTIO_DMA_SHARED_BUFFER=y # CONFIG_VDPA is not set CONFIG_VHOST_MENU=y # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set @@ -1943,9 +1698,8 @@ CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_FONT_SUPPORT=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines From 4734f0eee50c747cff4f504c6008b64f3cfe3972 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 15 Jul 2021 23:53:15 -0400 Subject: [PATCH 051/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 34 +++++-------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index d0354b90..466a7c4d 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -58,7 +58,7 @@ CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ_FULL is not set # CONFIG_NO_HZ is not set -CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIGH_RES_TIMERS is not set # end of Timers subsystem CONFIG_PREEMPT_NONE=y @@ -75,7 +75,7 @@ CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_PSI is not set # end of CPU/Task time and stats accounting -CONFIG_CPU_ISOLATION=y +# CONFIG_CPU_ISOLATION is not set # # RCU Subsystem @@ -105,22 +105,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y -CONFIG_CGROUPS=y -# CONFIG_MEMCG is not set -# CONFIG_BLK_CGROUP is not set -CONFIG_CGROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_CFS_BANDWIDTH=y -# CONFIG_RT_GROUP_SCHED is not set -# CONFIG_CGROUP_PIDS is not set -# CONFIG_CGROUP_RDMA is not set -# CONFIG_CGROUP_FREEZER is not set -# CONFIG_CPUSETS is not set -# CONFIG_CGROUP_DEVICE is not set -# CONFIG_CGROUP_CPUACCT is not set -CONFIG_CGROUP_BPF=y -# CONFIG_CGROUP_DEBUG is not set -CONFIG_SOCK_CGROUP_DATA=y +# CONFIG_CGROUPS is not set CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y @@ -193,8 +178,8 @@ CONFIG_HAVE_PERF_EVENTS=y # CONFIG_PERF_EVENTS is not set # end of Kernel Performance Events And Counters -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -203,7 +188,7 @@ CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SLUB_CPU_PARTIAL is not set # CONFIG_PROFILING is not set # end of General setup @@ -237,8 +222,8 @@ CONFIG_LOCKDEP_SUPPORT=y # # SoC selection # -CONFIG_SOC_SIFIVE=y -CONFIG_SOC_VIRT=y +# CONFIG_SOC_SIFIVE is not set +# CONFIG_SOC_VIRT is not set # end of SoC selection # @@ -267,7 +252,6 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -CONFIG_SCHED_HRTICK=y CONFIG_RISCV_SBI_V01=y # end of Kernel features @@ -1213,7 +1197,6 @@ CONFIG_RPMSG_VIRTIO=y # # end of Qualcomm SoC drivers -# CONFIG_SIFIVE_L2 is not set # CONFIG_SOC_TI is not set # @@ -1773,7 +1756,6 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set From 66bf2005fe92b5816b65ad336ea0a6a4438b8878 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 00:10:31 -0400 Subject: [PATCH 052/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 42 ++++--------------- 1 file changed, 9 insertions(+), 33 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 466a7c4d..8a241e78 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -84,8 +84,6 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y -CONFIG_TASKS_RCU_GENERIC=y -CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem @@ -106,12 +104,8 @@ CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y # CONFIG_CGROUPS is not set -CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y -CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_CHECKPOINT_RESTORE=y +# CONFIG_NAMESPACES is not set +# CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set @@ -120,26 +114,19 @@ CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio" CONFIG_INITRAMFS_ROOT_UID=0 CONFIG_INITRAMFS_ROOT_GID=0 CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_RD_XZ=y -CONFIG_RD_LZO=y -CONFIG_RD_LZ4=y -CONFIG_RD_ZSTD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set CONFIG_INITRAMFS_COMPRESSION_GZIP=y -# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set -# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set -# CONFIG_INITRAMFS_COMPRESSION_XZ is not set -# CONFIG_INITRAMFS_COMPRESSION_LZO is not set -# CONFIG_INITRAMFS_COMPRESSION_LZ4 is not set -# CONFIG_INITRAMFS_COMPRESSION_ZSTD is not set # CONFIG_INITRAMFS_COMPRESSION_NONE is not set # CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_MULTIUSER=y # CONFIG_SGETMASK_SYSCALL is not set @@ -165,8 +152,7 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_PRELOAD is not set +# CONFIG_BPF_SYSCALL is not set # CONFIG_USERFAULTFD is not set # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y @@ -1643,12 +1629,8 @@ CONFIG_CRC32_SLICEBY8=y CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set # CONFIG_CRC8 is not set -CONFIG_XXHASH=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y @@ -1659,12 +1641,6 @@ CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_ZSTD=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y From 3273b030e14250d1ef2d84bc27a9cf79052abe8b Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 00:16:12 -0400 Subject: [PATCH 053/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 32 +++++-------------- 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 8a241e78..7ec83e7e 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -18,6 +18,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # # General setup # +CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="" @@ -56,7 +57,6 @@ CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_HZ_FULL is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set # end of Timers subsystem @@ -75,24 +75,19 @@ CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_PSI is not set # end of CPU/Task time and stats accounting -# CONFIG_CPU_ISOLATION is not set - # # RCU Subsystem # -CONFIG_TREE_RCU=y +CONFIG_TINY_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y -CONFIG_TREE_SRCU=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_TINY_SRCU=y # end of RCU Subsystem CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y # CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=17 -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y @@ -174,7 +169,6 @@ CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -# CONFIG_SLUB_CPU_PARTIAL is not set # CONFIG_PROFILING is not set # end of General setup @@ -187,7 +181,7 @@ CONFIG_MMU=y CONFIG_ZONE_DMA32=y CONFIG_VA_BITS=39 CONFIG_PA_BITS=56 -CONFIG_PAGE_OFFSET=0xffffffe000000000 +CONFIG_PAGE_OFFSET=0xffffffff80000000 CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y @@ -220,11 +214,9 @@ CONFIG_ARCH_RV64I=y # CONFIG_CMODEL_MEDLOW is not set CONFIG_CMODEL_MEDANY=y CONFIG_MODULE_SECTIONS=y -# CONFIG_MAXPHYSMEM_2GB is not set -CONFIG_MAXPHYSMEM_128GB=y -CONFIG_SMP=y -CONFIG_NR_CPUS=8 -# CONFIG_HOTPLUG_CPU is not set +CONFIG_MAXPHYSMEM_2GB=y +# CONFIG_MAXPHYSMEM_128GB is not set +# CONFIG_SMP is not set CONFIG_TUNE_GENERIC=y CONFIG_RISCV_ISA_C=y CONFIG_FPU=y @@ -379,11 +371,7 @@ CONFIG_MQ_IOSCHED_KYBER=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_ARCH_HAS_MMIOWB=y -CONFIG_MMIOWB=y # # Executable file formats @@ -416,6 +404,7 @@ CONFIG_MIGRATION=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y # CONFIG_CLEANCACHE is not set # CONFIG_FRONTSWAP is not set # CONFIG_CMA is not set @@ -464,7 +453,6 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y # end of Generic Driver Options # @@ -1468,7 +1456,6 @@ CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y # CONFIG_CRYPTO_NULL is not set CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_PCRYPT is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set @@ -1650,7 +1637,6 @@ CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_SWIOTLB=y # CONFIG_DMA_API_DEBUG is not set -# CONFIG_CPUMASK_OFFSTACK is not set # CONFIG_IRQ_POLL is not set CONFIG_LIBFDT=y CONFIG_UCS2_STRING=y @@ -1746,7 +1732,6 @@ CONFIG_DEBUG_VM_PGTABLE=y CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DEBUG_PER_CPU_MAPS=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # end of Memory Debugging @@ -1822,7 +1807,6 @@ CONFIG_DEBUG_SG=y # CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_REF_SCALE_TEST is not set -CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_RCU_TRACE is not set CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging From 0238b869fbb1dfe3e427e04e8073210fc8b9edd1 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 00:34:41 -0400 Subject: [PATCH 054/112] incremental linux config de-bloating --- .../linux-testgen/buildroot-config-src/linux.config | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 7ec83e7e..88873a10 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -230,7 +230,7 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -CONFIG_RISCV_SBI_V01=y +# CONFIG_RISCV_SBI_V01 is not set # end of Kernel features # @@ -659,7 +659,6 @@ CONFIG_SERIAL_OF_PLATFORM=y # # Non-8250 serial port support # -CONFIG_SERIAL_EARLYCON_RISCV_SBI=y # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y @@ -682,7 +681,6 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_NULL_TTY is not set # CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y -CONFIG_HVC_RISCV_SBI=y # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set CONFIG_VIRTIO_CONSOLE=y From c4716af4d6d5c1cab5d448ed647f903b46cf731c Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 00:41:18 -0400 Subject: [PATCH 055/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 147 +----------------- 1 file changed, 3 insertions(+), 144 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 88873a10..c04eb527 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -26,7 +26,6 @@ CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="WallyDefaultHostname" -CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_WATCH_QUEUE is not set @@ -213,7 +212,6 @@ CONFIG_LOCKDEP_SUPPORT=y CONFIG_ARCH_RV64I=y # CONFIG_CMODEL_MEDLOW is not set CONFIG_CMODEL_MEDANY=y -CONFIG_MODULE_SECTIONS=y CONFIG_MAXPHYSMEM_2GB=y # CONFIG_MAXPHYSMEM_128GB is not set # CONFIG_SMP is not set @@ -237,8 +235,7 @@ CONFIG_HZ=250 # Boot options # CONFIG_CMDLINE="" -CONFIG_EFI_STUB=y -CONFIG_EFI=y +# CONFIG_EFI is not set # end of Boot options # @@ -253,22 +250,6 @@ CONFIG_EFI=y # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_GOOGLE_FIRMWARE is not set -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_ESRT=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB=y -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_EFI_EARLYCON=y - # # Tegra firmware driver # @@ -300,8 +281,6 @@ CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 @@ -312,7 +291,6 @@ CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set # @@ -328,47 +306,8 @@ CONFIG_HAVE_GCC_PLUGINS=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_COMPRESS is not set -# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_BSGLIB is not set -# CONFIG_BLK_DEV_INTEGRITY is not set -# CONFIG_BLK_DEV_ZONED is not set -# CONFIG_BLK_CMDLINE_PARSER is not set -# CONFIG_BLK_WBT is not set -CONFIG_BLK_DEBUG_FS=y -# CONFIG_BLK_SED_OPAL is not set -# CONFIG_BLK_INLINE_ENCRYPTION is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_EFI_PARTITION=y -# end of Partition Types - -CONFIG_BLK_MQ_VIRTIO=y - -# -# IO Schedulers -# -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -# CONFIG_IOSCHED_BFQ is not set -# end of IO Schedulers - +# CONFIG_MODULES is not set +# CONFIG_BLOCK is not set CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_HAS_MMIOWB=y @@ -406,7 +345,6 @@ CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_NEED_PER_CPU_KM=y # CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set # CONFIG_CMA is not set # CONFIG_ZPOOL is not set # CONFIG_ZBUD is not set @@ -450,7 +388,6 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y # end of Generic Driver Options @@ -474,12 +411,10 @@ CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set # CONFIG_PARPORT is not set -# CONFIG_BLK_DEV is not set # # NVME Support # -# CONFIG_NVME_FC is not set # end of NVME Support # @@ -527,15 +462,8 @@ CONFIG_OF_RESERVED_MEM=y # SCSI device support # CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set # end of SCSI device support -# CONFIG_ATA is not set -# CONFIG_MD is not set -# CONFIG_TARGET_CORE is not set -# CONFIG_NVM is not set - # # Input device support # @@ -693,7 +621,6 @@ CONFIG_HW_RANDOM_VIRTIO=y # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_DEVMEM=y # CONFIG_DEVKMEM is not set -# CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # end of Character devices @@ -744,7 +671,6 @@ CONFIG_I2C_BOARDINFO=y # # end of I2C Hardware Bus support -# CONFIG_I2C_STUB is not set # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1027,7 +953,6 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS1685_FAMILY is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_EFI is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set @@ -1244,25 +1169,6 @@ CONFIG_NVMEM_SYSFS=y # File systems # # CONFIG_VALIDATE_FS_PARSER is not set -CONFIG_FS_IOMAP=y -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -CONFIG_EXT4_FS=y -CONFIG_EXT4_USE_FOR_EXT2=y -CONFIG_EXT4_FS_POSIX_ACL=y -# CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -# CONFIG_F2FS_FS is not set -# CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -1286,26 +1192,6 @@ CONFIG_AUTOFS_FS=y # CONFIG_FSCACHE is not set # end of Caches -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set -# end of CD-ROM/DVD Filesystems - -# -# DOS/FAT/EXFAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_FAT_DEFAULT_UTF8 is not set -# CONFIG_EXFAT_FS is not set -# CONFIG_NTFS_FS is not set -# end of DOS/FAT/EXFAT/NT Filesystems - # # Pseudo filesystems # @@ -1324,32 +1210,13 @@ CONFIG_TMPFS_XATTR=y CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y # CONFIG_CONFIGFS_FS is not set -CONFIG_EFIVAR_FS=m # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y # CONFIG_ORANGEFS_FS is not set -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX6FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_PSTORE is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_EROFS_FS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set @@ -1456,7 +1323,6 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set CONFIG_CRYPTO_ENGINE=y # @@ -1637,13 +1503,8 @@ CONFIG_SWIOTLB=y # CONFIG_DMA_API_DEBUG is not set # CONFIG_IRQ_POLL is not set CONFIG_LIBFDT=y -CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_FONT_SUPPORT=y -CONFIG_FONT_8x16=y -CONFIG_FONT_AUTOSELECT=y -CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines @@ -1751,7 +1612,6 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_WQ_WATCHDOG=y -# CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs # @@ -1810,7 +1670,6 @@ CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -CONFIG_DEBUG_BLOCK_EXT_DEVT=y # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y From 7340e089f7e09ce453bee5f370c2187573da2310 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 00:46:22 -0400 Subject: [PATCH 056/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 256 +----------------- 1 file changed, 7 insertions(+), 249 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index c04eb527..70167fe7 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -420,18 +420,8 @@ CONFIG_OF_RESERVED_MEM=y # # Misc devices # -# CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set -# CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_HMC6352 is not set -# CONFIG_DS1682 is not set # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set @@ -440,12 +430,7 @@ CONFIG_OF_RESERVED_MEM=y # # EEPROM support # -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set -# CONFIG_EEPROM_IDT_89HPESX is not set -# CONFIG_EEPROM_EE1004 is not set # end of EEPROM support # @@ -453,8 +438,9 @@ CONFIG_OF_RESERVED_MEM=y # # end of Texas Instruments shared transport line discipline -# CONFIG_SENSORS_LIS3_I2C is not set -# CONFIG_ALTERA_STAPL is not set +# +# Altera FPGA firmware download module (requires I2C) +# # CONFIG_ECHO is not set # end of Misc devices @@ -476,10 +462,7 @@ CONFIG_INPUT=y # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -487,50 +470,8 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # # Input Device Drivers # -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_QT1050 is not set -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_OMAP4 is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_CAP11XX is not set -# CONFIG_KEYBOARD_BCM is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -CONFIG_MOUSE_PS2_CYPRESS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -CONFIG_MOUSE_PS2_SMBUS=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -593,7 +534,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_SIFIVE=y CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_SCCNXP is not set -# CONFIG_SERIAL_SC16IS7XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set @@ -630,51 +570,7 @@ CONFIG_DEVMEM=y # # I2C support # -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_COMPAT is not set -# CONFIG_I2C_CHARDEV is not set -# CONFIG_I2C_MUX is not set -# CONFIG_I2C_HELPER_AUTO is not set -# CONFIG_I2C_SMBUS is not set - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set -# end of I2C Algorithms - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_EMEV2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_RK3X is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_XILINX is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_TAOS_EVM is not set - -# -# Other I2C/SMBus bus drivers -# -# end of I2C Hardware Bus support - -# CONFIG_I2C_SLAVE is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C is not set # end of I2C support # CONFIG_I3C is not set @@ -705,24 +601,11 @@ CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set # CONFIG_PDA_POWER is not set # CONFIG_TEST_POWER is not set -# CONFIG_CHARGER_ADP5061 is not set -# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_SBS is not set -# CONFIG_CHARGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_LP8727 is not set -# CONFIG_CHARGER_DETECTOR_MAX14656 is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_BATTERY_GOLDFISH is not set -# CONFIG_CHARGER_BD99954 is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set @@ -734,91 +617,18 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # -# CONFIG_MFD_ACT8945A is not set -# CONFIG_MFD_AS3711 is not set -# CONFIG_MFD_AS3722 is not set -# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_ATMEL_FLEXCOM is not set # CONFIG_MFD_ATMEL_HLCDC is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_AXP20X_I2C is not set # CONFIG_MFD_MADERA is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_GATEWORKS_GSC is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77620 is not set -# CONFIG_MFD_MAX77650 is not set -# CONFIG_MFD_MAX77686 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_RK808 is not set -# CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SKY81452 is not set # CONFIG_ABX500_CORE is not set -# CONFIG_MFD_STMPE is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_TI_LMU is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS6507X is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TPS65217 is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TI_LP87565 is not set -# CONFIG_MFD_TPS65218 is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS80031 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL6040_CORE is not set -# CONFIG_MFD_WL1273_CORE is not set -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_TC3589X is not set # CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_LOCHNAGAR is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set -# CONFIG_MFD_ROHM_BD71828 is not set -# CONFIG_MFD_STPMIC1 is not set -# CONFIG_MFD_STMFX is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set @@ -865,12 +675,6 @@ CONFIG_DUMMY_CONSOLE_ROWS=25 # HID support # # CONFIG_HID is not set - -# -# I2C HID support -# -# CONFIG_I2C_HID is not set -# end of I2C HID support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y @@ -901,48 +705,14 @@ CONFIG_RTC_INTF_DEV=y # # I2C RTC drivers # -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABEOZ9 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_HYM8563 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_ISL12026 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF85363 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_RV3028 is not set -# CONFIG_RTC_DRV_RV3032 is not set -# CONFIG_RTC_DRV_RV8803 is not set -# CONFIG_RTC_DRV_SD3078 is not set # # SPI RTC drivers # -CONFIG_RTC_I2C_AND_SPI=y # # SPI and I2C RTC drivers # -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set # # Platform RTC drivers @@ -1010,16 +780,6 @@ CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_MAX9485 is not set -# CONFIG_COMMON_CLK_SI5341 is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI514 is not set -# CONFIG_COMMON_CLK_SI544 is not set -# CONFIG_COMMON_CLK_SI570 is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CDCE925 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y CONFIG_CLK_SIFIVE=y @@ -1440,8 +1200,6 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set -# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set CONFIG_CRYPTO_DEV_VIRTIO=y # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set From ae886b015dcffd168782505831cdc5e5b7d75887 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 01:00:12 -0400 Subject: [PATCH 057/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 57 +++++++++++++------ 1 file changed, 41 insertions(+), 16 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 70167fe7..25d2b654 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -489,6 +489,7 @@ CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_PS2MULT is not set # CONFIG_SERIO_ARC_PS2 is not set # CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set # end of Hardware I/O ports @@ -544,6 +545,7 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_SPRD is not set # end of Serial drivers +CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_GOLDFISH_TTY is not set # CONFIG_NULL_TTY is not set @@ -589,23 +591,46 @@ CONFIG_DEVMEM=y # end of PTP clock support # CONFIG_PINCTRL is not set -# CONFIG_GPIOLIB is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=32 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set +CONFIG_GPIO_CDEV=y +# CONFIG_GPIO_CDEV_V1 is not set +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +CONFIG_GPIO_SIFIVE=y +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set # CONFIG_W1 is not set -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_RESTART is not set -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -# CONFIG_SYSCON_REBOOT_MODE is not set -# CONFIG_NVMEM_REBOOT_MODE is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_TEST_POWER is not set -# CONFIG_BATTERY_DS2780 is not set -# CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set From b003c651be93019ecf81756702c5f76d16f880e0 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 01:25:41 -0400 Subject: [PATCH 058/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 76 +------------------ 1 file changed, 3 insertions(+), 73 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 25d2b654..0181ee8a 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -335,8 +335,6 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_MEMORY_BALLOON=y -CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y @@ -521,7 +519,6 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set CONFIG_SERIAL_OF_PLATFORM=y @@ -612,11 +609,8 @@ CONFIG_GPIO_GENERIC=y # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_GRGPIO is not set # CONFIG_GPIO_HLWD is not set -# CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set -# CONFIG_GPIO_SAMA5D2_PIOBU is not set CONFIG_GPIO_SIFIVE=y -# CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_XILINX is not set # CONFIG_GPIO_AMD_FCH is not set # end of Memory mapped GPIO drivers @@ -651,7 +645,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_SM501 is not set # CONFIG_ABX500_CORE is not set -CONFIG_MFD_SYSCON=y +# CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set # CONFIG_MFD_TQMX86 is not set # end of Multifunction device drivers @@ -709,66 +703,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set CONFIG_EDAC_SUPPORT=y -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set -CONFIG_RTC_NVMEM=y - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# - -# -# SPI RTC drivers -# - -# -# SPI and I2C RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_ZYNQMP is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_CADENCE is not set -# CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_R7301 is not set - -# -# HID Sensor RTC drivers -# -CONFIG_RTC_DRV_GOLDFISH=y +# CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # @@ -783,11 +718,7 @@ CONFIG_RTC_DRV_GOLDFISH=y # CONFIG_UIO is not set # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO=y -CONFIG_VIRTIO_MENU=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_INPUT=y -CONFIG_VIRTIO_MMIO=y -# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +# CONFIG_VIRTIO_MENU is not set # CONFIG_VDPA is not set CONFIG_VHOST_MENU=y # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set @@ -918,7 +849,6 @@ CONFIG_SIFIVE_PLIC=y # CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_OCELOT_SERDES is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set From ca5a1755f342f2d41b54ed384fc77b59f4d63f74 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 01:33:51 -0400 Subject: [PATCH 059/112] incremental linux config de-bloating --- .../linux-testgen/buildroot-config-src/linux.config | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 0181ee8a..afdc0af1 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -544,7 +544,6 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y CONFIG_SERIAL_MCTRL_GPIO=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_GOLDFISH_TTY is not set # CONFIG_NULL_TTY is not set # CONFIG_TRACE_SINK is not set CONFIG_HVC_DRIVER=y @@ -720,8 +719,7 @@ CONFIG_EDAC_SUPPORT=y CONFIG_VIRTIO=y # CONFIG_VIRTIO_MENU is not set # CONFIG_VDPA is not set -CONFIG_VHOST_MENU=y -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +# CONFIG_VHOST_MENU is not set # # Microsoft Hyper-V guest support @@ -730,8 +728,7 @@ CONFIG_VHOST_MENU=y # CONFIG_GREYBUS is not set # CONFIG_STAGING is not set -CONFIG_GOLDFISH=y -# CONFIG_GOLDFISH_PIPE is not set +# CONFIG_GOLDFISH is not set CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y From ff90e6744c91e75ab5762e284269def0d6255542 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 01:43:16 -0400 Subject: [PATCH 060/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index afdc0af1..c2a88390 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -734,9 +734,7 @@ CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_FIXED_MMIO is not set -CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y -CONFIG_CLK_SIFIVE=y -CONFIG_CLK_SIFIVE_FU540_PRCI=y +# CONFIG_CLK_SIFIVE is not set # CONFIG_HWSPINLOCK is not set # @@ -749,14 +747,7 @@ CONFIG_RISCV_TIMER=y # end of Clock Source drivers # CONFIG_MAILBOX is not set -CONFIG_IOMMU_SUPPORT=y - -# -# Generic IOMMU Pagetable Support -# -# end of Generic IOMMU Pagetable Support - -# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_SUPPORT is not set # # Remoteproc drivers @@ -767,8 +758,7 @@ CONFIG_IOMMU_SUPPORT=y # # Rpmsg drivers # -CONFIG_RPMSG=y -CONFIG_RPMSG_VIRTIO=y +# CONFIG_RPMSG_VIRTIO is not set # end of Rpmsg drivers # CONFIG_SOUNDWIRE is not set From 3bcc5808d41ce1aa36800cafcab24e96e162fbd9 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 01:54:36 -0400 Subject: [PATCH 061/112] incremental linux config de-bloating --- .../linux-testgen/buildroot-config-src/linux.config | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index c2a88390..486c0f58 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -512,7 +512,7 @@ CONFIG_LDISC_AUTOLOAD=y # CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y @@ -849,8 +849,7 @@ CONFIG_SIFIVE_PLIC=y # end of Android # CONFIG_DAX is not set -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM is not set # # HW tracing support From f34e28d18787f82f4036df602b111543c8633ee4 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 01:58:21 -0400 Subject: [PATCH 062/112] incremental linux config de-bloating --- .../linux-testgen/buildroot-config-src/linux.config | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 486c0f58..8b4a252c 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -479,16 +479,7 @@ CONFIG_INPUT=y # # Hardware I/O ports # -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_SERIO_PS2MULT is not set -# CONFIG_SERIO_ARC_PS2 is not set -# CONFIG_SERIO_APBPS2 is not set -# CONFIG_SERIO_GPIO_PS2 is not set -# CONFIG_USERIO is not set +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # end of Hardware I/O ports # end of Input device support From b1fe4ff295732e42f675f54dac4acd08d3cb91b6 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 11:15:25 -0400 Subject: [PATCH 063/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 82 ++----------------- 1 file changed, 5 insertions(+), 77 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 8b4a252c..9a34e3f4 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -873,7 +873,7 @@ CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set -CONFIG_AUTOFS4_FS=y +# CONFIG_AUTOFS4_FS is not set CONFIG_AUTOFS_FS=y # CONFIG_FUSE_FS is not set # CONFIG_OVERLAY_FS is not set @@ -904,62 +904,8 @@ CONFIG_ARCH_HAS_GIGANTIC_PAGE=y # CONFIG_CONFIGFS_FS is not set # end of Pseudo filesystems -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ORANGEFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_PSTORE is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_MAC_ROMAN is not set -# CONFIG_NLS_MAC_CELTIC is not set -# CONFIG_NLS_MAC_CENTEURO is not set -# CONFIG_NLS_MAC_CROATIAN is not set -# CONFIG_NLS_MAC_CYRILLIC is not set -# CONFIG_NLS_MAC_GAELIC is not set -# CONFIG_NLS_MAC_GREEK is not set -# CONFIG_NLS_MAC_ICELAND is not set -# CONFIG_NLS_MAC_INUIT is not set -# CONFIG_NLS_MAC_ROMANIAN is not set -# CONFIG_NLS_MAC_TURKISH is not set -# CONFIG_NLS_UTF8 is not set +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NLS is not set # CONFIG_UNICODE is not set CONFIG_IO_WQ=y # end of File systems @@ -967,11 +913,7 @@ CONFIG_IO_WQ=y # # Security options # -CONFIG_KEYS=y -# CONFIG_KEYS_REQUEST_CACHE is not set -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set @@ -1002,20 +944,13 @@ CONFIG_CRYPTO=y # CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_SKCIPHER=y -CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y # CONFIG_CRYPTO_MANAGER is not set CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y # CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set -CONFIG_CRYPTO_ENGINE=y # # Public-key cryptography @@ -1131,17 +1066,11 @@ CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_DEV_VIRTIO=y -# CONFIG_CRYPTO_DEV_SAFEXCEL is not set -# CONFIG_CRYPTO_DEV_CCREE is not set -# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set -# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_CRYPTO_HW is not set # # Certificates for signature checking # -# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking # @@ -1182,7 +1111,6 @@ CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y -CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y From 40352ab7e4b36095455a07ef7e18ea51d25a2c26 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 11:33:11 -0400 Subject: [PATCH 064/112] incremental linux config de-bloating --- .../buildroot-config-src/linux.config | 34 ++++++++----------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index 9a34e3f4..aec52f6d 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -942,12 +942,8 @@ CONFIG_CRYPTO=y # # Crypto core or helper # -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y # CONFIG_CRYPTO_MANAGER is not set -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set @@ -999,7 +995,7 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y # # Digest # -CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_CRC32 is not set # CONFIG_CRYPTO_XXHASH is not set # CONFIG_CRYPTO_BLAKE2B is not set @@ -1085,9 +1081,9 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y # CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y +# CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y @@ -1096,20 +1092,12 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_BIT is not set # CONFIG_CRC64 is not set # CONFIG_CRC4 is not set -CONFIG_CRC7=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set # CONFIG_CRC8 is not set # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y -CONFIG_XZ_DEC=y -CONFIG_XZ_DEC_X86=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_BCJ=y -# CONFIG_XZ_DEC_TEST is not set +# CONFIG_XZ_DEC is not set CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -1150,11 +1138,17 @@ CONFIG_DEBUG_BUGVERBOSE=y # # Compile-time checks and compiler options # -# CONFIG_DEBUG_INFO is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_BTF is not set +CONFIG_GDB_SCRIPTS=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set +CONFIG_READABLE_ASM=y # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y From ae7d48c326db2a7836905c6c540cc323deb56acd Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 12:08:58 -0400 Subject: [PATCH 065/112] incremental linux config de-bloating --- wally-pipelined/linux-testgen/buildroot-config-src/main.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/main.config b/wally-pipelined/linux-testgen/buildroot-config-src/main.config index 7315007d..7888971c 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/main.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/main.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Buildroot -g8d5e37d-dirty Configuration +# Buildroot -gafcb8fe-dirty Configuration # BR2_HAVE_DOT_CONFIG=y From e0f719d51326a1db45bf8582f1aef28c7a217249 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 11:12:57 -0500 Subject: [PATCH 066/112] Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. --- wally-pipelined/src/cache/dcache.sv | 67 +- wally-pipelined/src/lsu/lsu.sv | 13 +- wally-pipelined/src/lsu/lsuArb.sv | 65 +- wally-pipelined/src/mmu/pagetablewalker.sv | 778 ++++++++++----------- 4 files changed, 399 insertions(+), 524 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index dc66043c..e5ef5f35 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -43,7 +43,7 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, - output logic [`XLEN-1:0] ReadDataM, + output logic [`XLEN-1:0] ReadDataM, output logic DCacheStall, output logic CommittedM, @@ -53,6 +53,7 @@ module dcache input logic DTLBMissM, input logic CacheableM, input logic DTLBWriteM, + input logic SelPTW, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -443,7 +444,13 @@ module dcache // The page table walker asserts it's control 1 cycle // after the TLBs miss. DCacheStall = 1'b1; + NextState = STATE_READY; + end + else if(SelPTW) begin + // Now we have activated the ptw. + // Do not assert Stall as we are now directing the stall the ptw. NextState = STATE_PTW_READY; + CommittedM = 1'b1; end // amo hit else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin @@ -592,7 +599,7 @@ module dcache // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. - if (DTLBWriteM) begin + if (~SelPTW) begin NextState = STATE_PTW_ACCESS_AFTER_WALK; // read hit valid cached @@ -650,61 +657,15 @@ module dcache STATE_PTW_READ_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; - NextState = STATE_PTW_READY; + NextState = STATE_PTW_READY; CommittedM = 1'b1; end STATE_PTW_ACCESS_AFTER_WALK: begin - SelAdrM = 1'b1; - // amo hit - if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - NextState = STATE_AMO_UPDATE; - DCacheStall = 1'b1; - - if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_AMO_UPDATE; - end - // read hit valid cached - else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - DCacheStall = 1'b0; - - if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - end - // write hit valid cached - else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - DCacheStall = 1'b0; - SRAMWordWriteEnableM = 1'b1; - SetDirtyM = 1'b1; - - if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - end - // read or write miss valid cached - else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_MISS_FETCH_WDV; - CntReset = 1'b1; - DCacheStall = 1'b1; - end - // uncached write - else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin - NextState = STATE_UNCACHED_WRITE; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBWrite = 1'b1; - end - // uncached read - else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin - NextState = STATE_UNCACHED_READ; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBRead = 1'b1; - end - // fault - else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin - NextState = STATE_READY; - end - else NextState = STATE_READY; + DCacheStall = 1'b1; + SelAdrM = 1'b1; + CommittedM = 1'b1; + NextState = STATE_READY; end STATE_CPU_BUSY : begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 0f38b829..56d0cb9c 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -126,7 +126,6 @@ module lsu logic HPTWStall; logic [`XLEN-1:0] HPTWPAdrE; logic [`XLEN-1:0] HPTWPAdrM; - logic HPTWTranslate; logic HPTWReadM; logic [1:0] MemRWMtoDCache; logic [2:0] Funct3MtoDCache; @@ -170,8 +169,8 @@ module lsu .HPTWStall(HPTWStall), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), - .HPTWTranslate(HPTWTranslate), .HPTWReadM(HPTWReadM), + .SelPTW(SelPTW), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM)); @@ -182,7 +181,7 @@ module lsu lsuArb arbiter(.clk(clk), .reset(reset), // HPTW connection - .HPTWTranslate(HPTWTranslate), + .SelPTW(SelPTW), .HPTWReadM(HPTWReadM), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), @@ -214,8 +213,9 @@ module lsu .ReadDataWfromDCache(ReadDataWfromDCache), .CommittedMfromDCache(CommittedMfromDCache), .PendingInterruptMtoDCache(PendingInterruptMtoDCache), - .DCacheStall(DCacheStall), - .SelPTW(SelPTW)); + .DCacheStall(DCacheStall)); + + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) @@ -243,7 +243,9 @@ module lsu // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + // *** BUG, this is most likely wrong assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM; + generate if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache; else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache; @@ -335,6 +337,7 @@ module lsu .DTLBMissM(DTLBMissM), .CacheableM(CacheableMtoDCache), .DTLBWriteM(DTLBWriteM), + .SelPTW(SelPTW), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 3b3ad94f..4feec655 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -30,7 +30,7 @@ module lsuArb (input logic clk, reset, // from page table walker - input logic HPTWTranslate, + input logic SelPTW, input logic HPTWReadM, input logic [`XLEN-1:0] HPTWPAdrE, input logic [`XLEN-1:0] HPTWPAdrM, @@ -62,7 +62,6 @@ module lsuArb output logic [`XLEN-1:0] MemAdrEtoDCache, output logic StallWtoDCache, output logic PendingInterruptMtoDCache, - output logic SelPTW, // from D Cache @@ -73,73 +72,11 @@ module lsuArb input logic DCacheStall ); - - // HPTWTranslate is the request for memory by the page table walker. When - // this is high the page table walker gains priority over the CPU's data - // input. Note the ptw only makes a request after an instruction or data - // tlb miss. It is entirely possible the dcache is currently processing - // a data cache miss when an instruction tlb miss occurs. If an instruction - // in the E stage causes a d cache miss, the d cache will immediately start - // processing the request. Simultaneously the ITLB misses. By the time - // the TLB miss causes the page table walker to issue the first request - // to data memory the d cache is already busy. We can interlock by - // leveraging Stall as a d cache busy. We will need an FSM to handle this. - typedef enum{StateReady, - StatePTWPending, - StatePTWActive} statetype; - - - statetype CurrState, NextState; logic [2:0] PTWSize; - - flopenl #(.TYPE(statetype)) StateReg(.clk(clk), - .load(reset), - .en(1'b1), - .d(NextState), - .val(StateReady), - .q(CurrState)); - - always_comb begin - case(CurrState) - StateReady: - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - StatePTWActive: - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - default: NextState = StateReady; - endcase - end - -/* -----\/----- EXCLUDED -----\/----- - - always_comb begin - case(CurrState) - StateReady: - /-* -----\/----- EXCLUDED -----\/----- - if (HPTWTranslate & DataStall) NextState = StatePTWPending; - else - -----/\----- EXCLUDED -----/\----- *-/ - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - StatePTWPending: - if (HPTWTranslate & ~DataStall) NextState = StatePTWActive; - else if (HPTWTranslate & DataStall) NextState = StatePTWPending; - else NextState = StateReady; - StatePTWActive: - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - default: NextState = StateReady; - endcase - end - - -----/\----- EXCLUDED -----/\----- */ - // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. - assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate); assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM; generate diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 282d5bf2..8948badf 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -9,21 +9,21 @@ // // Purpose: Page Table Walker // Part of the Memory Management Unit (MMU) -// +// // A component of the Wally configurable RISC-V project. -// +// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software // is furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// @@ -37,107 +37,94 @@ module pagetablewalker ( // Control signals - input logic clk, reset, + input logic clk, reset, input logic [`XLEN-1:0] SATP_REGW, // Signals from TLBs (addresses to translate) input logic [`XLEN-1:0] PCF, MemAdrM, - input logic ITLBMissF, DTLBMissM, - input logic [1:0] MemRWM, + input logic ITLBMissF, DTLBMissM, + input logic [1:0] MemRWM, // Outputs to the TLBs (PTEs to write) output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM, - output logic [1:0] PageTypeF, PageTypeM, - output logic ITLBWriteF, DTLBWriteM, - - + output logic [1:0] PageTypeF, PageTypeM, + output logic ITLBWriteF, DTLBWriteM, + output logic SelPTW, // *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU input logic [`XLEN-1:0] HPTWReadPTE, - input logic MMUReady, - input logic HPTWStall, + input logic MMUReady, + input logic HPTWStall, // *** modify to send to LSU output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide - output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide - output logic HPTWTranslate, // *** rename to HPTWReq - output logic HPTWReadM, + output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide + output logic HPTWReadM, // Faults - output logic WalkerInstrPageFaultF, - output logic WalkerLoadPageFaultM, - output logic WalkerStorePageFaultM + output logic WalkerInstrPageFaultF, + output logic WalkerLoadPageFaultM, + output logic WalkerStorePageFaultM ); - logic HPTWReadE; + logic HPTWReadE; generate if (`MEM_VIRTMEM) begin // Internal signals // register TLBs translation miss requests - logic ITLBMissFQ, DTLBMissMQ; - - logic [`PPN_BITS-1:0] BasePageTablePPN; - logic [`XLEN-1:0] TranslationVAdr; - logic [`XLEN-1:0] SavedPTE, CurrentPTE; - logic [`PA_BITS-1:0] TranslationPAdr; - logic [`PPN_BITS-1:0] CurrentPPN; - logic [`SVMODE_BITS-1:0] SvMode; - logic MemStore; - logic DTLBWriteM_d; + logic ITLBMissFQ, DTLBMissMQ; + + logic [`PPN_BITS-1:0] BasePageTablePPN; + logic [`XLEN-1:0] TranslationVAdr; + logic [`XLEN-1:0] SavedPTE, CurrentPTE; + logic [`PA_BITS-1:0] TranslationPAdr; + logic [`PPN_BITS-1:0] CurrentPPN; + logic [`SVMODE_BITS-1:0] SvMode; + logic MemStore; // PTE Control Bits - logic Dirty, Accessed, Global, User, + logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid; // PTE descriptions - logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; + logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; // Outputs of walker - logic [`XLEN-1:0] PageTableEntry; - logic [1:0] PageType; - logic StartWalk; - logic EndWalk; - - typedef enum {LEVEL0_WDV, + logic [`XLEN-1:0] PageTableEntry; + logic [1:0] PageType; + logic StartWalk; + logic EndWalk; + + typedef enum {LEVEL0_SET_ADRE, + LEVEL0_WDV, LEVEL0, + LEVEL1_SET_ADRE, LEVEL1_WDV, LEVEL1, + LEVEL2_SET_ADRE, LEVEL2_WDV, LEVEL2, + LEVEL3_SET_ADRE, LEVEL3_WDV, LEVEL3, LEAF, IDLE, - START, FAULT} statetype; - statetype WalkerState, NextWalkerState; + statetype WalkerState, NextWalkerState, PreviousWalkerState; - logic PRegEn; - logic SelDataTranslation; - - - flop #(`XLEN) HPTWPAdrMReg(.clk(clk), - .d(HPTWPAdrE), - .q(HPTWPAdrM)); + logic PRegEn; + logic SelDataTranslation; + logic AnyTLBMissM; - flop #(2) PageTypeReg(.clk(clk), - .d(PageType), - .q(PageTypeM)); - flop #(`XLEN) PageTableEntryReg(.clk(clk), - .d(PageTableEntry), - .q(PageTableEntryM)); - - flop #(1) DTLBWriteReg(.clk(clk), - .d(DTLBWriteM_d), - .q(DTLBWriteM)); - flop #(1) HPTWReadMReg(.clk(clk), - .d(HPTWReadE), - .q(HPTWReadM)); + flop #(`XLEN) HPTWPAdrMReg(.clk(clk), + .d(HPTWPAdrE), + .q(HPTWPAdrM)); + assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; @@ -147,7 +134,7 @@ module pagetablewalker assign MemStore = MemRWM[0]; // Prefer data address translations over instruction address translations - assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr + assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; assign SelDataTranslation = DTLBMissMQ | DTLBMissM; flopenrc #(1) @@ -157,7 +144,7 @@ module pagetablewalker .clear(EndWalk), .d(DTLBMissM), .q(DTLBMissMQ)); - + flopenrc #(1) ITLBMissMReg(.clk(clk), .reset(reset), @@ -165,22 +152,16 @@ module pagetablewalker .clear(EndWalk), .d(ITLBMissF), .q(ITLBMissFQ)); - - assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); - assign EndWalk = WalkerState == LEAF || - //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || - //(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || - //(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || - //(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == FAULT); - - assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ); - //assign HPTWTranslate = DTLBMissM | ITLBMissF; + + assign AnyTLBMissM = DTLBMissM | ITLBMissF; + + assign StartWalk = WalkerState == IDLE & AnyTLBMissM; + assign EndWalk = WalkerState == LEAF || WalkerState == FAULT; // unswizzle PTE bits assign {Dirty, Accessed, Global, User, - Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; + Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; // Assign PTE descriptors common across all XLEN values assign LeafPTE = Executable | Writable | Readable; @@ -189,398 +170,391 @@ module pagetablewalker // Assign specific outputs to general outputs assign PageTableEntryF = PageTableEntry; - //assign PageTableEntryM = PageTableEntry; + assign PageTableEntryM = PageTableEntry; assign PageTypeF = PageType; - //assign PageTypeM = PageType; + assign PageTypeM = PageType; // generate if (`XLEN == 32) begin - logic [9:0] VPN1, VPN0; + logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; -----/\----- EXCLUDED -----/\----- */ - // State transition logic - always_comb begin + // State transition logic + always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; HPTWReadE = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM_d = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; - case (WalkerState) - IDLE: begin - if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - START: begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWReadE = 1'b1; - end - - LEVEL1_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; + SelPTW = 1'b1; + + case (WalkerState) + IDLE: begin + SelPTW = 1'b0; + if (AnyTLBMissM & SvMode == `SV32) begin + NextWalkerState = LEVEL1_SET_ADRE; + end else begin + NextWalkerState = IDLE; + end + end + + LEVEL1_SET_ADRE: begin + NextWalkerState = LEVEL1_WDV; + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + end + + LEVEL1_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; PRegEn = 1'b1; - end - end - - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin + end + end + + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_SET_ADRE; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end - - LEVEL0_WDV: begin - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWReadE = 1'b1; - if (HPTWStall) begin + end else begin + NextWalkerState = FAULT; + end + end + + LEVEL0_SET_ADRE: begin + NextWalkerState = LEVEL0_WDV; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + end + + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; - end else begin + end else begin NextWalkerState = LEVEL0; PRegEn = 1'b1; - end - end + end + end - LEVEL0: begin - if (ValidPTE & LeafPTE & ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; - end else begin - NextWalkerState = FAULT; - end - end - - LEAF: begin - NextWalkerState = IDLE; - end + LEVEL0: begin + if (ValidPTE & LeafPTE & ~AccessAlert) begin + NextWalkerState = LEAF; + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end else begin + NextWalkerState = FAULT; + end + end - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end - - // Default case should never happen, but is included for linter. - default: NextWalkerState = IDLE; - endcase - end + LEAF: begin + NextWalkerState = IDLE; + PageTableEntry = CurrentPTE; + PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[9:0]); - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end - assign VPN1 = TranslationVAdr[31:22]; - assign VPN0 = TranslationVAdr[21:12]; + // Default case should never happen, but is included for linter. + default: NextWalkerState = IDLE; + endcase + end - + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[9:0]); + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - // Capture page table entry from data cache - // *** may need to delay reading this value until the next clock cycle. - // The clk to q latency of the SRAM in the data cache will be long. - // I cannot see directly using this value. This is no different than - // a load delay hazard. This will require rewriting the walker fsm. - // also need a new signal to save. Should be a mealy output of the fsm - // request followed by ~stall. - flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + assign VPN1 = TranslationVAdr[31:22]; + assign VPN0 = TranslationVAdr[21:12]; - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdrE = TranslationPAdr[31:0]; + + + // Capture page table entry from data cache + // *** may need to delay reading this value until the next clock cycle. + // The clk to q latency of the SRAM in the data cache will be long. + // I cannot see directly using this value. This is no different than + // a load delay hazard. This will require rewriting the walker fsm. + // also need a new signal to save. Should be a mealy output of the fsm + // request followed by ~stall. + flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + + // Assign outputs to ahblite + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = TranslationPAdr[31:0]; end else begin - - logic [8:0] VPN3, VPN2, VPN1, VPN0; - logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; + logic [8:0] VPN3, VPN2, VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || - WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || - // WalkerState == LEVEL2 || WalkerState == LEVEL1; - + /* -----\/----- EXCLUDED -----\/----- + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || + WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; + -----/\----- EXCLUDED -----/\----- */ - always_comb begin + //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || + // WalkerState == LEVEL2 || WalkerState == LEVEL1; + + + always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; HPTWReadE = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM_d = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; - case (WalkerState) - IDLE: begin - if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - START: begin - if (HPTWTranslate && SvMode == `SV48) begin + SelPTW = 1'b1; + + case (WalkerState) + IDLE: begin + SelPTW = 1'b0; + if (AnyTLBMissM & SvMode == `SV48) begin + NextWalkerState = LEVEL3_SET_ADRE; + end else if (AnyTLBMissM & SvMode == `SV39) begin + NextWalkerState = LEVEL2_SET_ADRE; + end else begin + NextWalkerState = IDLE; + end + end + + LEVEL3_SET_ADRE: begin + NextWalkerState = LEVEL3_WDV; + TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + end + + LEVEL3_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin NextWalkerState = LEVEL3_WDV; - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWReadE = 1'b1; - end else if (HPTWTranslate && SvMode == `SV39) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; - end else begin // *** should not get here - NextWalkerState = IDLE; - TranslationPAdr = '0; - end - end - - LEVEL3_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL3_WDV; - end else begin + end else begin NextWalkerState = LEVEL3; PRegEn = 1'b1; - end - end - - LEVEL3: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadTerapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end + end + end - end + LEVEL3: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadTerapage) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL2_SET_ADRE; + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + end else begin + NextWalkerState = FAULT; + end + end - LEVEL2_WDV: begin - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL2_WDV; - end else begin - NextWalkerState = LEVEL2; - PRegEn = 1'b1; - end - end - - LEVEL2: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadGigapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end + LEVEL2_SET_ADRE: begin + NextWalkerState = LEVEL2_WDV; + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + end - end + LEVEL2_WDV: begin + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL2_WDV; + end else begin + NextWalkerState = LEVEL2; + PRegEn = 1'b1; + end + end - LEVEL1_WDV: begin - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; - end - end + LEVEL2: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadGigapage) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL1_SET_ADRE; + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + end else begin + NextWalkerState = FAULT; + end + end - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end + LEVEL1_SET_ADRE: begin + NextWalkerState = LEVEL1_WDV; + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + end - LEVEL0_WDV: begin - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; - end - end + LEVEL1_WDV: begin + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; + PRegEn = 1'b1; + end + end - LEVEL0: begin - if (ValidPTE && LeafPTE && ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end else begin - NextWalkerState = FAULT; - end - end - - LEAF: begin - NextWalkerState = IDLE; - end + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_SET_ADRE; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + end else begin + NextWalkerState = FAULT; + end + end - // Default case should never happen - default: begin - NextWalkerState = IDLE; - end + LEVEL0_SET_ADRE: begin + NextWalkerState = LEVEL0_WDV; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + end - endcase - end + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL0_WDV; + end else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; + end + end - // A terapage is a level 3 leaf page. This page must have zero PPN[2], - // zero PPN[1], and zero PPN[0] - assign TerapageMisaligned = |(CurrentPPN[26:0]); - // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and - // zero PPN[0] - assign GigapageMisaligned = |(CurrentPPN[17:0]); - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[8:0]); + LEVEL0: begin + if (ValidPTE && LeafPTE && ~AccessAlert) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end else begin + NextWalkerState = FAULT; + end + end - assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + LEAF: begin + PageTableEntry = CurrentPTE; + PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? + ((PreviousWalkerState == LEVEL2) ? 2'b10 : + ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + NextWalkerState = IDLE; + end - assign VPN3 = TranslationVAdr[47:39]; - assign VPN2 = TranslationVAdr[38:30]; - assign VPN1 = TranslationVAdr[29:21]; - assign VPN0 = TranslationVAdr[20:12]; + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end + + // Default case should never happen + default: begin + NextWalkerState = IDLE; + end + + endcase + end + + // A terapage is a level 3 leaf page. This page must have zero PPN[2], + // zero PPN[1], and zero PPN[0] + assign TerapageMisaligned = |(CurrentPPN[26:0]); + // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and + // zero PPN[0] + assign GigapageMisaligned = |(CurrentPPN[17:0]); + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[8:0]); + + assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + + assign VPN3 = TranslationVAdr[47:39]; + assign VPN2 = TranslationVAdr[38:30]; + assign VPN1 = TranslationVAdr[29:21]; + assign VPN0 = TranslationVAdr[20:12]; - // Capture page table entry from ahblite - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + // Capture page table entry from ahblite + flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + // *** Major issue. We need the full virtual address here. + // When the TLB's are update it use use the orignal address + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; end //endgenerate end else begin assign HPTWPAdrE = 0; - assign HPTWTranslate = 0; assign HPTWReadE = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; + assign SelPTW = 0; end endgenerate From 01ca22af49fdf982555a06ef9e924e3e5bbf67f6 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 12:27:15 -0400 Subject: [PATCH 067/112] changed stop of linux boot from arch_cpu_idle to do_idle --- .../testvector-generation/gdbinit_qemulog | 2 +- .../testvector-generation/logAllBuildroot.sh | 4 +- .../regression/wave-dos/peripheral-waves.do | 51 +++++++++++++++---- 3 files changed, 45 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog b/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog index f4318ad1..42137c05 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog +++ b/wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog @@ -1,7 +1,7 @@ set pagination off target extended-remote :1236 file ../buildroot-image-output/vmlinux -b arch_cpu_idle +b do_idle c c c diff --git a/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh b/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh index 52f0fe6f..797b9f7d 100755 --- a/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh +++ b/wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh @@ -14,7 +14,7 @@ outDir="../linux-testvectors" # Uncomment this version for QEMU debugging of kernel # - good for poking around VM if it boots up # - good for running QEMU commands (press "Ctrl-A" then "c" to open QEMU command prompt) -$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio +#$customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio # Uncomment this version for GDB debugging of kernel # - attempts to load in symbols from "vmlinux" # - good for looking at backtraces when Linux gets stuck for some reason @@ -41,4 +41,4 @@ $customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Ima # =========== Just Do the Thing ========== # Uncomment this version for the whole thing # - Logs info needed by buildroot testbench -#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog +($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do index a42bfbd4..59515fd0 100644 --- a/wally-pipelined/regression/wave-dos/peripheral-waves.do +++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do @@ -42,7 +42,6 @@ add wave -hex /testbench/dut/hart/ifu/InstrM add wave -hex /testbench/dut/hart/ieu/c/InstrValidM add wave /testbench/InstrMName add wave /testbench/dut/uncore/dtim/memwrite -add wave -hex /testbench/dut/hart/MemPAdrM add wave -hex /testbench/dut/hart/WriteDataM add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA @@ -63,16 +62,50 @@ add wave -hex /testbench/dut/hart/priv/csr/TrapM add wave -hex /testbench/dut/hart/priv/csr/UnalignedNextEPCM add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEPCM add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW -add wave -divider + +add wave -divider RegFile +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[1] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[2] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[3] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[4] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[5] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[6] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[7] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[8] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[9] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[10] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[11] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[12] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[13] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[14] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[15] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[16] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[17] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[18] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[19] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[20] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[21] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[22] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[23] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[24] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[25] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[26] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[27] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[28] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30] +add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31] # peripherals -#add wave -hex /testbench/dut/uncore/plic/* -#add wave -hex /testbench/dut/uncore/plic/intPriority -#add wave -hex /testbench/dut/uncore/plic/pendingArray -#add wave -divider -#add wave -hex /testbench/dut/uncore/uart/u/* -#add wave -divider -#add wave -hex /testbench/dut/uncore/gpio/* +add wave -divider PLIC +add wave -hex /testbench/dut/hart/priv/csr/TrapM +add wave -hex /testbench/dut/uncore/genblk2/plic/* +add wave -hex /testbench/dut/uncore/genblk2/plic/intPriority +add wave -hex /testbench/dut/uncore/genblk2/plic/pendingArray +add wave -divider UART +add wave -hex /testbench/dut/uncore/genblk4/uart/u/* +add wave -divider GPIO +add wave -hex /testbench/dut/uncore/genblk3/gpio/* #add wave -divider #add wave -hex /testbench/dut/hart/ebu/* #add wave -divider From b0fcfc2773820c3f3957261a50f4241d8547294f Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 16 Jul 2021 12:42:29 -0400 Subject: [PATCH 068/112] reduce number of UART ports to 1 --- .../linux-testgen/buildroot-config-src/linux.config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config index aec52f6d..3c8503dd 100644 --- a/wally-pipelined/linux-testgen/buildroot-config-src/linux.config +++ b/wally-pipelined/linux-testgen/buildroot-config-src/linux.config @@ -507,8 +507,8 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 # CONFIG_SERIAL_8250_EXTENDED is not set # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set From 46bce70e42c474abe12e5a1be860c872096f8bb2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 12:22:13 -0500 Subject: [PATCH 069/112] Fixed walker fault interaction with dcache. --- wally-pipelined/regression/wave.do | 231 +++++++++++---------- wally-pipelined/src/cache/dcache.sv | 16 +- wally-pipelined/src/lsu/lsu.sv | 8 +- wally-pipelined/src/lsu/lsuArb.sv | 4 +- wally-pipelined/src/mmu/mmu.sv | 7 +- wally-pipelined/src/mmu/pagetablewalker.sv | 33 +-- 6 files changed, 163 insertions(+), 136 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 6c4b1d79..73b6f9fb 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -13,19 +13,19 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM @@ -241,81 +241,83 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/CurrState add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -expand -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable @@ -325,27 +327,36 @@ add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWTranslate -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM -add wave -noupdate -expand -group lsu -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -group ptwalker -divider data -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead +add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -417,7 +428,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {10516 ns} 0} +WaveRestoreCursors {{Cursor 4} {29656 ns} 0} {{Cursor 2} {28907 ns} 0} {{Cursor 3} {27874 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -433,4 +444,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {10473 ns} {10589 ns} +WaveRestoreZoom {29565 ns} {29803 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index e5ef5f35..85a34158 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -53,7 +53,9 @@ module dcache input logic DTLBMissM, input logic CacheableM, input logic DTLBWriteM, - input logic SelPTW, + // from ptw + input logic SelPTW, + input logic WalkerPageFaultM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -164,8 +166,8 @@ module dcache STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, STATE_PTW_READ_MISS_READ_WORD, STATE_PTW_READ_MISS_READ_WORD_DELAY, - STATE_PTW_ACCESS_AFTER_WALK, - STATE_PTW_UPDATE_TLB, + STATE_PTW_ACCESS_AFTER_WALK, + STATE_PTW_UPDATE_TLB, STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, @@ -599,7 +601,7 @@ module dcache // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. - if (~SelPTW) begin + if (~SelPTW & ~WalkerPageFaultM) begin NextState = STATE_PTW_ACCESS_AFTER_WALK; // read hit valid cached @@ -614,6 +616,12 @@ module dcache CntReset = 1'b1; DCacheStall = 1'b1; end + + // walker has issue abort back to ready + else if(~SelPTW & WalkerPageFaultM) begin + NextState = STATE_READY; + DCacheStall = 1'b0; + end end STATE_PTW_READ_MISS_FETCH_WDV: begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 56d0cb9c..30971c13 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -147,6 +147,7 @@ module lsu logic CommittedMfromDCache; logic PendingInterruptMtoDCache; logic FlushWtoDCache; + logic WalkerPageFaultM; pagetablewalker pagetablewalker( @@ -169,20 +170,20 @@ module lsu .HPTWStall(HPTWStall), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), - .HPTWReadM(HPTWReadM), + .HPTWRead(HPTWRead), .SelPTW(SelPTW), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM)); - + assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; // arbiter between IEU and pagetablewalker lsuArb arbiter(.clk(clk), .reset(reset), // HPTW connection .SelPTW(SelPTW), - .HPTWReadM(HPTWReadM), + .HPTWRead(HPTWRead), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), //.HPTWReadPTE(HPTWReadPTE), @@ -338,6 +339,7 @@ module lsu .CacheableM(CacheableMtoDCache), .DTLBWriteM(DTLBWriteM), .SelPTW(SelPTW), + .WalkerPageFaultM(WalkerPageFaultM), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 4feec655..13a77243 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -31,7 +31,7 @@ module lsuArb // from page table walker input logic SelPTW, - input logic HPTWReadM, + input logic HPTWRead, input logic [`XLEN-1:0] HPTWPAdrE, input logic [`XLEN-1:0] HPTWPAdrM, // to page table walker. @@ -77,7 +77,7 @@ module lsuArb // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. - assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM; + assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM; generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index b836218c..72abc7ba 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -117,9 +117,10 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries pmpchecker pmpchecker(.*); + // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess; - assign InstrAccessFaultF = PMAInstrAccessFaultF | PMPInstrAccessFaultF; - assign LoadAccessFaultM = PMALoadAccessFaultM | PMPLoadAccessFaultM; - assign StoreAccessFaultM = PMAStoreAccessFaultM | PMPStoreAccessFaultM; + assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit); + assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit); + assign StoreAccessFaultM = (PMAStoreAccessFaultM | PMPStoreAccessFaultM) & ~(Translate & ~TLBHit); endmodule diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 8948badf..a41f5ca0 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -60,7 +60,7 @@ module pagetablewalker // *** modify to send to LSU output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide - output logic HPTWReadM, + output logic HPTWRead, // Faults @@ -69,7 +69,6 @@ module pagetablewalker output logic WalkerStorePageFaultM ); - logic HPTWReadE; generate if (`MEM_VIRTMEM) begin @@ -179,8 +178,10 @@ module pagetablewalker if (`XLEN == 32) begin logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); + /* -----\/----- EXCLUDED -----\/----- assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; -----/\----- EXCLUDED -----/\----- */ @@ -189,7 +190,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; - HPTWReadE = 1'b0; + HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; DTLBWriteM = '0; @@ -218,7 +219,7 @@ module pagetablewalker LEVEL1_WDV: begin TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL1_WDV; end else begin @@ -240,7 +241,7 @@ module pagetablewalker else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL0_SET_ADRE; TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; end else begin NextWalkerState = FAULT; end @@ -253,7 +254,7 @@ module pagetablewalker LEVEL0_WDV: begin TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; end else begin @@ -281,6 +282,7 @@ module pagetablewalker end FAULT: begin + SelPTW = 1'b0; NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; @@ -324,7 +326,9 @@ module pagetablewalker logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) WalkerStageReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + + flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); /* -----\/----- EXCLUDED -----\/----- assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || @@ -338,7 +342,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; - HPTWReadE = 1'b0; + HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; DTLBWriteM = '0; @@ -369,7 +373,7 @@ module pagetablewalker LEVEL3_WDV: begin TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL3_WDV; end else begin @@ -403,7 +407,7 @@ module pagetablewalker LEVEL2_WDV: begin TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL2_WDV; end else begin @@ -437,7 +441,7 @@ module pagetablewalker LEVEL1_WDV: begin TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL1_WDV; end else begin @@ -472,7 +476,7 @@ module pagetablewalker LEVEL0_WDV: begin TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; end else begin @@ -502,6 +506,7 @@ module pagetablewalker end FAULT: begin + SelPTW = 1'b0; NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; @@ -550,7 +555,7 @@ module pagetablewalker //endgenerate end else begin assign HPTWPAdrE = 0; - assign HPTWReadE = 0; + assign HPTWRead = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; From b3bf04d474af2f3bac6051483e3c587df69c6e8e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 12:34:37 -0500 Subject: [PATCH 070/112] Updated wave file. --- wally-pipelined/regression/wave.do | 385 +++++++++++++++-------------- 1 file changed, 194 insertions(+), 191 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 73b6f9fb..33839c98 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -13,41 +13,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -182,43 +182,43 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0 -add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState -add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState -add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF -add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit -add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData -add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF -add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF -add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF +add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF +add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit +add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData +add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF +add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF +add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM @@ -241,122 +241,122 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -expand -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead -add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState +add wave -noupdate -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead +add wave -noupdate -group lsu -expand -group ptwalker -divider data +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -421,14 +421,17 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb -add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/Address add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {29656 ns} 0} {{Cursor 2} {28907 ns} 0} {{Cursor 3} {27874 ns} 0} +WaveRestoreCursors {{Cursor 4} {37704 ns} 0} {{Cursor 2} {28907 ns} 0} {{Cursor 3} {27874 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -444,4 +447,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {29565 ns} {29803 ns} +WaveRestoreZoom {37554 ns} {37770 ns} From 1aabee0478a223892b9f428d3d2238e45fccd5e1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 12:35:00 -0500 Subject: [PATCH 071/112] Updated the config so the tim has a bigger range. --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 44a90e1c..56bfade5 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h07FFFFFF +`define TIM_RANGE 56'h7FFFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF From 5e18a15a4c5387c733b3d816d6307390132e5d94 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 15:04:30 -0500 Subject: [PATCH 074/112] Added guide for Ben to do linux conversion. --- wally-pipelined/testbench/linux_comments.txt | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 wally-pipelined/testbench/linux_comments.txt diff --git a/wally-pipelined/testbench/linux_comments.txt b/wally-pipelined/testbench/linux_comments.txt new file mode 100644 index 00000000..5d5cc9ce --- /dev/null +++ b/wally-pipelined/testbench/linux_comments.txt @@ -0,0 +1,9 @@ +dut.HRDATA => dut.hart.lsu.dcache.ReadDataM +HADDR => dut.hart.lsu.dcache.MemPAdrM +HWDATA => dut.hart.lsu.dcache.WriteDataM +HWRITE => dut.hart.lsu.dcache.MemRWM +HTRANS => |dut.hart.lsu.dcache.MemRWM | |dut.hart.lsu.dcache.AtomicM + +HSIZE (probalby don't need anymore, read masking not necessary) +HRDATA (no physical change, just rename to something else) + From 0b3dc288ec100fddcaadb1d6c576202b5193c5d6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 15:56:06 -0500 Subject: [PATCH 075/112] Made furture progress in the mmu tests. --- wally-pipelined/src/cache/dcache.sv | 44 +++++++++++++++++++++++++---- wally-pipelined/src/lsu/lsu.sv | 1 + 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 66c857fd..476610f5 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -53,6 +53,7 @@ module dcache input logic DTLBMissM, input logic CacheableM, input logic DTLBWriteM, + input logic ITLBWriteF, // from ptw input logic SelPTW, input logic WalkerPageFaultM, @@ -164,6 +165,7 @@ module dcache STATE_PTW_READ_MISS_FETCH_WDV, STATE_PTW_READ_MISS_FETCH_DONE, STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_READ_MISS_EVICT_DIRTY, STATE_PTW_READ_MISS_READ_WORD, STATE_PTW_READ_MISS_READ_WORD_DELAY, STATE_PTW_ACCESS_AFTER_WALK, @@ -604,10 +606,22 @@ module dcache STATE_PTW_READY: begin // now all output connect to PTW instead of CPU. CommittedM = 1'b1; - // return to ready if page table walk completed. - if (~SelPTW & ~WalkerPageFaultM) begin - NextState = STATE_PTW_ACCESS_AFTER_WALK; + if (ITLBWriteF) begin + NextState = STATE_READY; + end + + // return to ready if page table walk completed. + else if (~SelPTW & ~WalkerPageFaultM & CacheHit & CacheableM & ~ExceptionM) begin + NextState = STATE_PTW_ACCESS_AFTER_WALK; + end + + // read or write miss valid cached + else if (~SelPTW & ~WalkerPageFaultM & ~CacheHit & CacheableM & ~ExceptionM) begin + NextState = STATE_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + // read hit valid cached end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin NextState = STATE_PTW_READY; @@ -615,7 +629,7 @@ module dcache end // read miss valid cached - else if((MemRWM[1]) & CacheableM & ~ExceptionM & ~CacheHit) begin + else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin NextState = STATE_PTW_READ_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; @@ -647,9 +661,29 @@ module dcache SelAdrM = 1'b1; CntReset = 1'b1; CommittedM = 1'b1; - NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK; + CntReset = 1'b1; + if(VictimDirty) begin + NextState = STATE_PTW_READ_MISS_EVICT_DIRTY; + end else begin + NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK; + end end + STATE_PTW_READ_MISS_EVICT_DIRTY: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + AHBWrite = 1'b1; + SelAdrM = 1'b1; + CommittedM = 1'b1; + SelEvict = 1'b1; + if( FetchCountFlag & AHBAck) begin + NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK; + end else begin + NextState = STATE_PTW_READ_MISS_EVICT_DIRTY; + end + end + + STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin SRAMBlockWriteEnableM = 1'b1; DCacheStall = 1'b1; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index f1db2099..cf11e717 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -338,6 +338,7 @@ module lsu .DTLBMissM(DTLBMissM), .CacheableM(CacheableMtoDCache), .DTLBWriteM(DTLBWriteM), + .ITLBWriteF(ITLBWriteF), .SelPTW(SelPTW), .WalkerPageFaultM(WalkerPageFaultM), From d10fd25c33d629d61d8d70ed9083668de38f0e92 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 16 Jul 2021 17:57:24 -0400 Subject: [PATCH 082/112] included virtual memory tests in testbench --- wally-pipelined/testbench/testbench-imperas.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 9160e4a4..be6fdf92 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -542,7 +542,7 @@ string tests32f[] = '{ //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - //if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; + if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 @@ -558,7 +558,7 @@ string tests32f[] = '{ if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; //if (`A_SUPPORTED) tests = {tests, tests32a}; if (`F_SUPPORTED) tests = {tests32f, tests}; - //if (`MEM_VIRTMEM) tests = {tests, tests32mmu}; + if (`MEM_VIRTMEM) tests = {tests32mmu, tests}; end end end From 1bd5c137a6e4c4bf17597aae7109a5bf69278b59 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jul 2021 20:10:12 -0400 Subject: [PATCH 083/112] Reduced size of physical memory by 16 for performance --- wally-pipelined/config/rv32ic/wally-config.vh | 2 +- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 68765c6c..090da8d6 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -67,7 +67,7 @@ `define BOOTTIM_RANGE 34'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 34'h80000000 -`define TIM_RANGE 34'h7FFFFFFF +`define TIM_RANGE 34'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 56bfade5..44a90e1c 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h7FFFFFFF +`define TIM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF From e3dc59c5a294b9e73ee16c35065eeec3d72fa59a Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jul 2021 20:17:03 -0400 Subject: [PATCH 084/112] renamed or_rows.sv --- wally-pipelined/src/generic/{or.sv => or_rows.sv} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename wally-pipelined/src/generic/{or.sv => or_rows.sv} (99%) diff --git a/wally-pipelined/src/generic/or.sv b/wally-pipelined/src/generic/or_rows.sv similarity index 99% rename from wally-pipelined/src/generic/or.sv rename to wally-pipelined/src/generic/or_rows.sv index 517a7b2c..4ea1dba7 100644 --- a/wally-pipelined/src/generic/or.sv +++ b/wally-pipelined/src/generic/or_rows.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// or.sv +// or_rows.sv // // Written: David_Harris@hmc.edu 13 July 2021 // Modified: From a19d3f126fac57bd5261ce5726e8e2956de3759e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 02:10:57 -0400 Subject: [PATCH 085/112] Commented out HRDATAW logic in ebu --- wally-pipelined/src/ebu/ahblite.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 302b5075..bb2fc6ca 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -180,7 +180,7 @@ module ahblite ( CapturedDataAvailable <= #1 1'b0; else CapturedDataAvailable <= #1 (StallW) ? (CaptureDataM | CapturedDataAvailable) : 1'b0; - always_comb +/* always_comb casez({StallW && (BusState != ATOMICREAD),CapturedDataAvailable}) 2'b00: HRDATANext = HRDATAMasked; 2'b01: HRDATANext = CapturedHRDATAMasked; @@ -192,8 +192,9 @@ module ahblite ( subwordread swr(.HRDATA(HRDATA), .HADDRD(HADDRD), .HSIZED(HSIZED), - .HRDATAMasked(HRDATAMasked)); + .HRDATAMasked(HRDATAMasked));*/ + // *** AMO portion will go away when it is moved into the LSU // Handle AMO instructions if applicable generate if (`A_SUPPORTED) begin From a898bbb991c2505fa7c8b171d0564ac5539eae9b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 02:15:24 -0400 Subject: [PATCH 086/112] Removed rest of HRDATAW from ahblite --- wally-pipelined/src/ebu/ahblite.sv | 16 ++-------------- wally-pipelined/src/wally/wallypipelinedhart.sv | 2 +- 2 files changed, 3 insertions(+), 15 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index bb2fc6ca..85a2fcfb 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -55,7 +55,7 @@ module ahblite ( input logic [1:0] MemSizeM, // *** remove output logic DCfromAHBAck, // Return from bus - output logic [`XLEN-1:0] HRDATAW, +// output logic [`XLEN-1:0] HRDATAW, // AHB-Lite external signals input logic [`AHBW-1:0] HRDATA, input logic HREADY, HRESP, @@ -180,25 +180,13 @@ module ahblite ( CapturedDataAvailable <= #1 1'b0; else CapturedDataAvailable <= #1 (StallW) ? (CaptureDataM | CapturedDataAvailable) : 1'b0; -/* always_comb - casez({StallW && (BusState != ATOMICREAD),CapturedDataAvailable}) - 2'b00: HRDATANext = HRDATAMasked; - 2'b01: HRDATANext = CapturedHRDATAMasked; - 2'b1?: HRDATANext = HRDATAW; - endcase - flopr #(`XLEN) ReadDataOldWReg(clk, reset, HRDATANext, HRDATAW); - - // Extract and sign-extend subwords if necessary - subwordread swr(.HRDATA(HRDATA), - .HADDRD(HADDRD), - .HSIZED(HSIZED), - .HRDATAMasked(HRDATAMasked));*/ // *** AMO portion will go away when it is moved into the LSU // Handle AMO instructions if applicable generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; + logic [`XLEN-1:0] HRDATAW; amoalu amoalu(.srca(HRDATAW), .srcb(DCtoAHBWriteData), .funct(Funct7M), .width(MemSizeM), .result(AMOResult)); mux2 #(`XLEN) wdmux(DCtoAHBWriteData, AMOResult, AtomicMaskedM[1], WriteData); diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 98e35d70..3560cae5 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -255,7 +255,7 @@ module wallypipelinedhart .MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed .UnsignedLoadM(1'b0), .Funct7M(7'b0), - .HRDATAW(), +// .HRDATAW(), .StallW(1'b0), .AtomicMaskedM(2'b00), .*); From dac22d50167888920a38361362922d480090cc4a Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 02:21:54 -0400 Subject: [PATCH 087/112] Removed more unused signals from ahblite --- wally-pipelined/src/ebu/ahblite.sv | 17 +++-------------- wally-pipelined/testbench/testbench-imperas.sv | 2 +- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 85a2fcfb..b7280a56 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -54,8 +54,6 @@ module ahblite ( output logic [`XLEN-1:0] DCfromAHBReadData, input logic [1:0] MemSizeM, // *** remove output logic DCfromAHBAck, - // Return from bus -// output logic [`XLEN-1:0] HRDATAW, // AHB-Lite external signals input logic [`AHBW-1:0] HRDATA, input logic HREADY, HRESP, @@ -78,7 +76,7 @@ module ahblite ( logic GrantData; logic [31:0] AccessAddress; - logic [2:0] AccessSize, PTESize, ISize; + logic [2:0] ISize; logic [`AHBW-1:0] HRDATAMasked, ReadDataM, HRDATANext, CapturedHRDATAMasked, WriteData; logic IReady, DReady; logic CaptureDataM,CapturedDataAvailable; @@ -135,14 +133,8 @@ module ahblite ( assign #1 AccessAddress = (GrantData) ? DCtoAHBPAdrM[31:0] : InstrPAdrF[31:0]; //assign #1 HADDR = (MMUTranslate) ? MMUPAdr[31:0] : AccessAddress; assign #1 HADDR = AccessAddress; - generate - if (`XLEN == 32) assign PTESize = 3'b010; // in rv32, PTEs are 4 bytes - else assign PTESize = 3'b011; // in rv64, PTEs are 8 bytes - endgenerate assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign #1 AccessSize = (GrantData) ? {1'b0, MemSizeM} : ISize; - //assign #1 HSIZE = (MMUTranslate) ? PTESize : AccessSize; - assign #1 HSIZE = AccessSize; + assign HSIZE = (GrantData) ? {1'b0, MemSizeM} : ISize; assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise @@ -158,15 +150,12 @@ module ahblite ( // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN - //assign MMUReady = (BusState == MMUTRANSLATE && HREADY); - + assign InstrRData = HRDATA; assign DCfromAHBReadData = HRDATA; assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); assign CommitM = (BusState == MEMREAD) || (BusState == MEMWRITE) || (BusState == ATOMICREAD) || (BusState == ATOMICWRITE); - // *** Bracker 6/5/21: why is this W stage? assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); - //assign MMUReadPTE = HRDATA; // Carefully decide when to update ReadDataW // ReadDataMstored holds the most recent memory read. // We need to wait until the pipeline actually advances before we can update the contents of ReadDataW diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index be6fdf92..46dfd00b 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -633,7 +633,7 @@ string tests32f[] = '{ dut.hart.ieu.dp.regf.wd3 == 1))) begin -----/\----- EXCLUDED -----/\----- */ if (DCacheFlushDone) begin - $display("Code ended with ecall with gp = 1"); + //$display("Code ended with ecall with gp = 1"); #600; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests From b65788d165a9ed0b2e97a6985249f256139fbd79 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 02:31:23 -0400 Subject: [PATCH 088/112] Replaced separate PageTypeF and PageTypeM with common PageType --- wally-pipelined/src/ifu/ifu.sv | 4 ++-- wally-pipelined/src/lsu/lsu.sv | 8 +++----- wally-pipelined/src/mmu/pagetablewalker.sv | 10 +--------- wally-pipelined/src/wally/wallypipelinedhart.sv | 4 ++-- 4 files changed, 8 insertions(+), 18 deletions(-) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index a0728a1a..9c2e9291 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -68,7 +68,7 @@ module ifu ( // mmu management input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] PageTableEntryF, - input logic [1:0] PageTypeF, + input logic [1:0] PageType, input logic [`XLEN-1:0] SATP_REGW, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic [1:0] STATUS_MPP, @@ -117,7 +117,7 @@ module ifu ( immu(.Address(PCF), .Size(2'b10), .PTE(PageTableEntryF), - .PageTypeWriteVal(PageTypeF), + .PageTypeWriteVal(PageType), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), .PhysicalAddress(PCPFmmu), diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index cf11e717..46f174a9 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -82,7 +82,7 @@ module lsu input logic [`XLEN-1:0] PCF, input logic ITLBMissF, output logic [`XLEN-1:0] PageTableEntryF, - output logic [1:0] PageTypeF, + output logic [1:0] PageType, output logic ITLBWriteF, output logic WalkerInstrPageFaultF, output logic WalkerLoadPageFaultM, @@ -119,7 +119,6 @@ module lsu logic DTLBMissM; logic [`XLEN-1:0] PageTableEntryM; - logic [1:0] PageTypeM; logic DTLBWriteM; logic [`XLEN-1:0] HPTWReadPTE; logic MMUReady; @@ -161,8 +160,7 @@ module lsu .MemRWM(MemRWM), .PageTableEntryF(PageTableEntryF), .PageTableEntryM(PageTableEntryM), - .PageTypeF(PageTypeF), - .PageTypeM(PageTypeM), + .PageType, .ITLBWriteF(ITLBWriteF), .DTLBWriteM(DTLBWriteM), .HPTWReadPTE(HPTWReadPTE), @@ -223,7 +221,7 @@ module lsu dmmu(.Address(MemAdrMtoDCache), .Size(Funct3MtoDCache[1:0]), .PTE(PageTableEntryM), - .PageTypeWriteVal(PageTypeM), + .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), .PhysicalAddress(MemPAdrM), diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index a41f5ca0..ea4c4de3 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -47,7 +47,7 @@ module pagetablewalker // Outputs to the TLBs (PTEs to write) output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM, - output logic [1:0] PageTypeF, PageTypeM, + output logic [1:0] PageType, output logic ITLBWriteF, DTLBWriteM, output logic SelPTW, @@ -92,7 +92,6 @@ module pagetablewalker // Outputs of walker logic [`XLEN-1:0] PageTableEntry; - logic [1:0] PageType; logic StartWalk; logic EndWalk; @@ -170,9 +169,6 @@ module pagetablewalker // Assign specific outputs to general outputs assign PageTableEntryF = PageTableEntry; assign PageTableEntryM = PageTableEntry; - assign PageTypeF = PageType; - assign PageTypeM = PageType; - // generate if (`XLEN == 32) begin @@ -182,10 +178,6 @@ module pagetablewalker flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ - // State transition logic always_comb begin PRegEn = 1'b0; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 3560cae5..fc71e6c1 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -118,7 +118,7 @@ module wallypipelinedhart logic [1:0] STATUS_MPP; logic [1:0] PrivilegeModeW; logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM; - logic [1:0] PageTypeF, PageTypeM; + logic [1:0] PageType; // PMA checker signals logic DSquashBusAccessM, ISquashBusAccessF; @@ -226,7 +226,7 @@ module wallypipelinedhart .PCF(PCF), .ITLBMissF(ITLBMissF), .PageTableEntryF(PageTableEntryF), - .PageTypeF(PageTypeF), + .PageType, .ITLBWriteF(ITLBWriteF), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), From a8a5fa4b3c0b2fc098ab083f54667f18c9cf9631 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 02:53:52 -0400 Subject: [PATCH 089/112] Started pagetablewalker cleanup: combined state flops shared for both RV versions --- wally-pipelined/src/mmu/pagetablewalker.sv | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index ea4c4de3..528b7292 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -151,6 +151,8 @@ module pagetablewalker .d(ITLBMissF), .q(ITLBMissFQ)); + flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); assign AnyTLBMissM = DTLBMissM | ITLBMissF; @@ -174,9 +176,6 @@ module pagetablewalker if (`XLEN == 32) begin logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - - flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); // State transition logic always_comb begin @@ -318,19 +317,6 @@ module pagetablewalker logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - flopenl #(.TYPE(statetype)) WalkerStageReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - - flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); - - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || - WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ - - //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || - // WalkerState == LEVEL2 || WalkerState == LEVEL1; - - always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; From 37691b84d0622883f77dc403f6c08d1d6dcef3ec Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 02:59:35 -0400 Subject: [PATCH 090/112] Flip-flop clean-up --- wally-pipelined/src/mmu/pagetablewalker.sv | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 528b7292..eed2c5ef 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -119,9 +119,6 @@ module pagetablewalker - flop #(`XLEN) HPTWPAdrMReg(.clk(clk), - .d(HPTWPAdrE), - .q(HPTWPAdrM)); @@ -135,9 +132,9 @@ module pagetablewalker assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; assign SelDataTranslation = DTLBMissMQ | DTLBMissM; - flopenrc #(1) - DTLBMissMReg(.clk(clk), - .reset(reset), + flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); + flopenrc #(2) TLBMissMReg(clk, reset, StartWalk | EndWalk, EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ}); +/* .reset(reset), .en(StartWalk | EndWalk), .clear(EndWalk), .d(DTLBMissM), @@ -149,7 +146,7 @@ module pagetablewalker .en(StartWalk | EndWalk), .clear(EndWalk), .d(ITLBMissF), - .q(ITLBMissFQ)); + .q(ITLBMissFQ)); */ flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); From 8241dd4599b0bc3f1db21836e40faf7a61e8d6b8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 03:10:17 -0400 Subject: [PATCH 091/112] Flip-flop clean-up --- wally-pipelined/src/mmu/pagetablewalker.sv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 528b7292..1a051c8f 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -119,9 +119,7 @@ module pagetablewalker - flop #(`XLEN) HPTWPAdrMReg(.clk(clk), - .d(HPTWPAdrE), - .q(HPTWPAdrM)); + flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); From 9a15a2f7df8c5685117c6868a9ae256a129fc345 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 03:12:24 -0400 Subject: [PATCH 092/112] Flip-flop clean-up --- wally-pipelined/src/mmu/pagetablewalker.sv | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 1a051c8f..13a297c3 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -121,8 +121,6 @@ module pagetablewalker flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); - - assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; @@ -133,7 +131,8 @@ module pagetablewalker assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; assign SelDataTranslation = DTLBMissMQ | DTLBMissM; - flopenrc #(1) + flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ}); + /* flopenrc #(1) DTLBMissMReg(.clk(clk), .reset(reset), .en(StartWalk | EndWalk), @@ -147,7 +146,7 @@ module pagetablewalker .en(StartWalk | EndWalk), .clear(EndWalk), .d(ITLBMissF), - .q(ITLBMissFQ)); + .q(ITLBMissFQ));*/ flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); From 86ca9abe42e0b4dbf8d2e76f7b98ea5af66a0c85 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 03:15:47 -0400 Subject: [PATCH 093/112] Flip-flop clean-up --- wally-pipelined/src/mmu/pagetablewalker.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 13a297c3..d71248a8 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -119,7 +119,6 @@ module pagetablewalker - flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; @@ -131,7 +130,6 @@ module pagetablewalker assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; assign SelDataTranslation = DTLBMissMQ | DTLBMissM; - flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ}); /* flopenrc #(1) DTLBMissMReg(.clk(clk), .reset(reset), @@ -148,6 +146,8 @@ module pagetablewalker .d(ITLBMissF), .q(ITLBMissFQ));*/ + flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); + flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ}); flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); From ac67342dd44c374a259c3f6d1039a216e173ca35 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 03:21:09 -0400 Subject: [PATCH 094/112] Pulled out shared PTEReg --- wally-pipelined/src/mmu/pagetablewalker.sv | 48 ++++------------------ 1 file changed, 8 insertions(+), 40 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index d71248a8..bb5ae854 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -78,7 +78,7 @@ module pagetablewalker logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`XLEN-1:0] TranslationVAdr; - logic [`XLEN-1:0] SavedPTE, CurrentPTE; + logic [`XLEN-1:0] CurrentPTE; logic [`PA_BITS-1:0] TranslationPAdr; logic [`PPN_BITS-1:0] CurrentPPN; logic [`SVMODE_BITS-1:0] SvMode; @@ -130,31 +130,18 @@ module pagetablewalker assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; assign SelDataTranslation = DTLBMissMQ | DTLBMissM; - /* flopenrc #(1) - DTLBMissMReg(.clk(clk), - .reset(reset), - .en(StartWalk | EndWalk), - .clear(EndWalk), - .d(DTLBMissM), - .q(DTLBMissMQ)); - - flopenrc #(1) - ITLBMissMReg(.clk(clk), - .reset(reset), - .en(StartWalk | EndWalk), - .clear(EndWalk), - .d(ITLBMissF), - .q(ITLBMissFQ));*/ - flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ}); - flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); + flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); + flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + assign AnyTLBMissM = DTLBMissM | ITLBMissF; - assign StartWalk = WalkerState == IDLE & AnyTLBMissM; - assign EndWalk = WalkerState == LEAF || WalkerState == FAULT; + assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM; + assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT); // unswizzle PTE bits assign {Dirty, Accessed, Global, User, @@ -291,18 +278,6 @@ module pagetablewalker - // Capture page table entry from data cache - // *** may need to delay reading this value until the next clock cycle. - // The clk to q latency of the SRAM in the data cache will be long. - // I cannot see directly using this value. This is no different than - // a load delay hazard. This will require rewriting the walker fsm. - // also need a new signal to save. Should be a mealy output of the fsm - // request followed by ~stall. - flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - // Assign outputs to ahblite // *** Currently truncate address to 32 bits. This must be changed if // we support larger physical address spaces @@ -514,13 +489,6 @@ module pagetablewalker assign VPN1 = TranslationVAdr[29:21]; assign VPN0 = TranslationVAdr[20:12]; - - // Capture page table entry from ahblite - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - // *** Major issue. We need the full virtual address here. // When the TLB's are update it use use the orignal address // *** Currently truncate address to 32 bits. This must be changed if From 569843346387b85c1503de5550907df32ce40939 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 03:30:17 -0400 Subject: [PATCH 095/112] Simplified bad PTE detection --- wally-pipelined/src/mmu/pagetablewalker.sv | 59 ++++++++++------------ 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index bb5ae854..bd71538f 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -88,7 +88,7 @@ module pagetablewalker logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid; // PTE descriptions - logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; + logic ValidPTE, ADPageFault, MegapageMisaligned, BadMegapage, LeafPTE; // Outputs of walker logic [`XLEN-1:0] PageTableEntry; @@ -134,7 +134,7 @@ module pagetablewalker flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ}); flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache + flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; @@ -150,7 +150,7 @@ module pagetablewalker // Assign PTE descriptors common across all XLEN values assign LeafPTE = Executable | Writable | Readable; assign ValidPTE = Valid && ~(Writable && ~Readable); - assign AccessAlert = ~Accessed | (MemStore & ~Dirty); + assign ADPageFault = ~Accessed | (MemStore & ~Dirty); // Assign specific outputs to general outputs assign PageTableEntryF = PageTableEntry; @@ -159,6 +159,11 @@ module pagetablewalker // generate if (`XLEN == 32) begin logic [9:0] VPN1, VPN0; + assign VPN1 = TranslationVAdr[31:22]; + assign VPN0 = TranslationVAdr[21:12]; + + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[9:0]); // State transition logic @@ -208,7 +213,7 @@ module pagetablewalker // fault upon finding a superpage that is misaligned or has 0 // access bit. The following commented line of code is // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin + if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) begin NextWalkerState = LEAF; TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end @@ -239,7 +244,7 @@ module pagetablewalker end LEVEL0: begin - if (ValidPTE & LeafPTE & ~AccessAlert) begin + if (ValidPTE & LeafPTE & ~ADPageFault) begin NextWalkerState = LEAF; TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end else begin @@ -269,12 +274,7 @@ module pagetablewalker endcase end - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[9:0]); - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign VPN1 = TranslationVAdr[31:22]; - assign VPN0 = TranslationVAdr[21:12]; @@ -286,8 +286,20 @@ module pagetablewalker end else begin logic [8:0] VPN3, VPN2, VPN1, VPN0; + assign VPN3 = TranslationVAdr[47:39]; + assign VPN2 = TranslationVAdr[38:30]; + assign VPN1 = TranslationVAdr[29:21]; + assign VPN0 = TranslationVAdr[20:12]; - logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; + logic TerapageMisaligned, GigapageMisaligned; + // A terapage is a level 3 leaf page. This page must have zero PPN[2], + // zero PPN[1], and zero PPN[0] + assign TerapageMisaligned = |(CurrentPPN[26:0]); + // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and + // zero PPN[0] + assign GigapageMisaligned = |(CurrentPPN[17:0]); + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[8:0]); always_comb begin PRegEn = 1'b0; @@ -337,7 +349,7 @@ module pagetablewalker // fault upon finding a superpage that is misaligned or has 0 // access bit. The following commented line of code is // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadTerapage) begin + if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) begin NextWalkerState = LEAF; TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end @@ -371,7 +383,7 @@ module pagetablewalker // fault upon finding a superpage that is misaligned or has 0 // access bit. The following commented line of code is // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadGigapage) begin + if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) begin NextWalkerState = LEAF; TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end @@ -405,7 +417,7 @@ module pagetablewalker // fault upon finding a superpage that is misaligned or has 0 // access bit. The following commented line of code is // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin + if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) begin NextWalkerState = LEAF; TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; @@ -436,7 +448,7 @@ module pagetablewalker end LEVEL0: begin - if (ValidPTE && LeafPTE && ~AccessAlert) begin + if (ValidPTE && LeafPTE && ~ADPageFault) begin NextWalkerState = LEAF; TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end else begin @@ -471,23 +483,6 @@ module pagetablewalker endcase end - // A terapage is a level 3 leaf page. This page must have zero PPN[2], - // zero PPN[1], and zero PPN[0] - assign TerapageMisaligned = |(CurrentPPN[26:0]); - // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and - // zero PPN[0] - assign GigapageMisaligned = |(CurrentPPN[17:0]); - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[8:0]); - - assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - - assign VPN3 = TranslationVAdr[47:39]; - assign VPN2 = TranslationVAdr[38:30]; - assign VPN1 = TranslationVAdr[29:21]; - assign VPN0 = TranslationVAdr[20:12]; // *** Major issue. We need the full virtual address here. // When the TLB's are update it use use the orignal address From 03ef3f7f1740a76203e0be9373b049740b21bdc1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 04:06:26 -0400 Subject: [PATCH 096/112] Pulled TranslationPAdr mux out of HPTW FSM --- wally-pipelined/src/mmu/pagetablewalker.sv | 121 ++++++++++++++------- 1 file changed, 79 insertions(+), 42 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index bd71538f..3fb13e99 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -156,12 +156,59 @@ module pagetablewalker assign PageTableEntryF = PageTableEntry; assign PageTableEntryM = PageTableEntry; + // *** is there a way to speed up HPTW? + + // TranslationPAdr mux + if (`XLEN==32) begin + logic [9:0] VPN1, VPN0; + assign VPN1 = TranslationVAdr[31:22]; + assign VPN0 = TranslationVAdr[21:12]; + always_comb + case (WalkerState) + LEVEL1_SET_ADRE: TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + LEVEL1_WDV: TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + LEVEL1: if (NextWalkerState == LEAF) TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; // ***check this and similar + else TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + LEVEL0_SET_ADRE: TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + LEVEL0_WDV: TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + LEVEL0: TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + LEAF: TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + default: TranslationPAdr = 0; // cause seg fault if this is improperly used + endcase + end else begin + logic [8:0] VPN3, VPN2, VPN1, VPN0; + assign VPN3 = TranslationVAdr[47:39]; + assign VPN2 = TranslationVAdr[38:30]; + assign VPN1 = TranslationVAdr[29:21]; + assign VPN0 = TranslationVAdr[20:12]; + always_comb + case (WalkerState) + LEVEL3_SET_ADRE: TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + LEVEL3_WDV: TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + LEVEL3: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + else TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + LEVEL2_SET_ADRE: TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + LEVEL2_WDV: TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + LEVEL2: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + else TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + LEVEL1_SET_ADRE: TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + LEVEL1_WDV: TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + LEVEL1: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + else TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + LEVEL0_SET_ADRE: TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + LEVEL0_WDV: TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + LEVEL0: TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + LEAF: TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + default: TranslationPAdr = 0; // cause seg fault if this is improperly used + endcase + end // generate if (`XLEN == 32) begin - logic [9:0] VPN1, VPN0; - assign VPN1 = TranslationVAdr[31:22]; - assign VPN0 = TranslationVAdr[21:12]; - + // *** make sure 32/34 bit addresses are being handled properly + //logic [9:0] VPN1, VPN0; + //assign VPN1 = TranslationVAdr[31:22]; + //assign VPN0 = TranslationVAdr[21:12]; + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. assign MegapageMisaligned = |(CurrentPPN[9:0]); @@ -169,7 +216,7 @@ module pagetablewalker // State transition logic always_comb begin PRegEn = 1'b0; - TranslationPAdr = '0; + // TranslationPAdr = '0; HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; @@ -194,11 +241,11 @@ module pagetablewalker LEVEL1_SET_ADRE: begin NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + //TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; end LEVEL1_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + //TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL1_WDV; @@ -209,18 +256,13 @@ module pagetablewalker end LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) begin NextWalkerState = LEAF; - TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + //TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; // ***check this end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL0_SET_ADRE; - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + //TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; HPTWRead = 1'b1; end else begin NextWalkerState = FAULT; @@ -229,11 +271,11 @@ module pagetablewalker LEVEL0_SET_ADRE: begin NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + //TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; end LEVEL0_WDV: begin - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + //TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; @@ -246,7 +288,7 @@ module pagetablewalker LEVEL0: begin if (ValidPTE & LeafPTE & ~ADPageFault) begin NextWalkerState = LEAF; - TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + //TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end else begin NextWalkerState = FAULT; end @@ -258,7 +300,7 @@ module pagetablewalker PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? DTLBWriteM = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + //TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end FAULT: begin @@ -285,11 +327,11 @@ module pagetablewalker end else begin - logic [8:0] VPN3, VPN2, VPN1, VPN0; +/* logic [8:0] VPN3, VPN2, VPN1, VPN0; assign VPN3 = TranslationVAdr[47:39]; assign VPN2 = TranslationVAdr[38:30]; assign VPN1 = TranslationVAdr[29:21]; - assign VPN0 = TranslationVAdr[20:12]; + assign VPN0 = TranslationVAdr[20:12];*/ logic TerapageMisaligned, GigapageMisaligned; // A terapage is a level 3 leaf page. This page must have zero PPN[2], @@ -303,7 +345,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; - TranslationPAdr = '0; + //TranslationPAdr = '0; HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; @@ -330,11 +372,11 @@ module pagetablewalker LEVEL3_SET_ADRE: begin NextWalkerState = LEVEL3_WDV; - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + //TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; end LEVEL3_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + //TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL3_WDV; @@ -345,18 +387,13 @@ module pagetablewalker end LEVEL3: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) begin NextWalkerState = LEAF; - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL2_SET_ADRE; - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + //TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; end else begin NextWalkerState = FAULT; end @@ -364,11 +401,11 @@ module pagetablewalker LEVEL2_SET_ADRE: begin NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + //TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; end LEVEL2_WDV: begin - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + //TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL2_WDV; @@ -385,12 +422,12 @@ module pagetablewalker // supposed to perform that check. However, it is untested. if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) begin NextWalkerState = LEAF; - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL1_SET_ADRE; - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + //TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; end else begin NextWalkerState = FAULT; end @@ -398,11 +435,11 @@ module pagetablewalker LEVEL1_SET_ADRE: begin NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + //TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; end LEVEL1_WDV: begin - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + //TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL1_WDV; @@ -419,13 +456,13 @@ module pagetablewalker // supposed to perform that check. However, it is untested. if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) begin NextWalkerState = LEAF; - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL0_SET_ADRE; - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + //TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; end else begin NextWalkerState = FAULT; end @@ -433,11 +470,11 @@ module pagetablewalker LEVEL0_SET_ADRE: begin NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + //TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; end LEVEL0_WDV: begin - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + //TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; @@ -450,7 +487,7 @@ module pagetablewalker LEVEL0: begin if (ValidPTE && LeafPTE && ~ADPageFault) begin NextWalkerState = LEAF; - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end else begin NextWalkerState = FAULT; end @@ -463,7 +500,7 @@ module pagetablewalker ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); DTLBWriteM = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; NextWalkerState = IDLE; end From 330e500442e901260c941f429edb834e06891637 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 04:12:31 -0400 Subject: [PATCH 097/112] Simplify FSM --- wally-pipelined/src/mmu/pagetablewalker.sv | 51 +++++++--------------- 1 file changed, 16 insertions(+), 35 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 3fb13e99..d365dc30 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -156,6 +156,9 @@ module pagetablewalker assign PageTableEntryF = PageTableEntry; assign PageTableEntryM = PageTableEntry; + assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT); + + // *** is there a way to speed up HPTW? // TranslationPAdr mux @@ -216,7 +219,6 @@ module pagetablewalker // State transition logic always_comb begin PRegEn = 1'b0; - // TranslationPAdr = '0; HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; @@ -227,46 +229,27 @@ module pagetablewalker WalkerLoadPageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0; - SelPTW = 1'b1; + // SelPTW = 1'b1; case (WalkerState) - IDLE: begin - SelPTW = 1'b0; - if (AnyTLBMissM & SvMode == `SV32) begin - NextWalkerState = LEVEL1_SET_ADRE; - end else begin - NextWalkerState = IDLE; - end - end - - LEVEL1_SET_ADRE: begin - NextWalkerState = LEVEL1_WDV; - //TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - end - + IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; + else NextWalkerState = IDLE; + LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; LEVEL1_WDV: begin - //TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin + if (HPTWStall) NextWalkerState = LEVEL1_WDV; + else begin NextWalkerState = LEVEL1; PRegEn = 1'b1; end end LEVEL1: begin - if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) begin - NextWalkerState = LEAF; - //TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; // ***check this - end + if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_SET_ADRE; - //TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end + NextWalkerState = LEVEL0_SET_ADRE; + HPTWRead = 1'b1; + end else NextWalkerState = FAULT; end LEVEL0_SET_ADRE: begin @@ -304,7 +287,7 @@ module pagetablewalker end FAULT: begin - SelPTW = 1'b0; + //SelPTW = 1'b0; NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; @@ -356,11 +339,9 @@ module pagetablewalker WalkerLoadPageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0; - SelPTW = 1'b1; - case (WalkerState) IDLE: begin - SelPTW = 1'b0; + //SelPTW = 1'b0; if (AnyTLBMissM & SvMode == `SV48) begin NextWalkerState = LEVEL3_SET_ADRE; end else if (AnyTLBMissM & SvMode == `SV39) begin @@ -505,7 +486,7 @@ module pagetablewalker end FAULT: begin - SelPTW = 1'b0; + //SelPTW = 1'b0; NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; From 6d8a6eeba0edaf3461c458be6e1ae824ca6cf157 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 04:26:41 -0400 Subject: [PATCH 098/112] cleaning up FSM --- wally-pipelined/src/mmu/pagetablewalker.sv | 57 +++++----------------- 1 file changed, 12 insertions(+), 45 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index d365dc30..6af6a9fd 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -229,8 +229,6 @@ module pagetablewalker WalkerLoadPageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0; - // SelPTW = 1'b1; - case (WalkerState) IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; else NextWalkerState = IDLE; @@ -239,8 +237,8 @@ module pagetablewalker HPTWRead = 1'b1; if (HPTWStall) NextWalkerState = LEVEL1_WDV; else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; + NextWalkerState = LEVEL1; + PRegEn = 1'b1; end end @@ -251,33 +249,19 @@ module pagetablewalker HPTWRead = 1'b1; end else NextWalkerState = FAULT; end - - LEVEL0_SET_ADRE: begin - NextWalkerState = LEVEL0_WDV; - //TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - end - + LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; LEVEL0_WDV: begin - //TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; + if (HPTWStall) NextWalkerState = LEVEL0_WDV; + else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; end end - LEVEL0: begin - if (ValidPTE & LeafPTE & ~ADPageFault) begin - NextWalkerState = LEAF; - //TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; - end else begin - NextWalkerState = FAULT; - end - end - - LEAF: begin + LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; + else NextWalkerState = FAULT; + LEAF: begin // *** pull out datapath stuff NextWalkerState = IDLE; PageTableEntry = CurrentPTE; PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? @@ -287,7 +271,6 @@ module pagetablewalker end FAULT: begin - //SelPTW = 1'b0; NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; @@ -309,13 +292,6 @@ module pagetablewalker assign HPTWPAdrE = TranslationPAdr[31:0]; end else begin - -/* logic [8:0] VPN3, VPN2, VPN1, VPN0; - assign VPN3 = TranslationVAdr[47:39]; - assign VPN2 = TranslationVAdr[38:30]; - assign VPN1 = TranslationVAdr[29:21]; - assign VPN0 = TranslationVAdr[20:12];*/ - logic TerapageMisaligned, GigapageMisaligned; // A terapage is a level 3 leaf page. This page must have zero PPN[2], // zero PPN[1], and zero PPN[0] @@ -328,7 +304,6 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; - //TranslationPAdr = '0; HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; @@ -340,16 +315,8 @@ module pagetablewalker WalkerStorePageFaultM = 1'b0; case (WalkerState) - IDLE: begin - //SelPTW = 1'b0; - if (AnyTLBMissM & SvMode == `SV48) begin - NextWalkerState = LEVEL3_SET_ADRE; - end else if (AnyTLBMissM & SvMode == `SV39) begin - NextWalkerState = LEVEL2_SET_ADRE; - end else begin - NextWalkerState = IDLE; - end - end + IDLE: if (AnyTLBMissM) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; + else NextWalkerState = IDLE; LEVEL3_SET_ADRE: begin NextWalkerState = LEVEL3_WDV; From bd270acdb61a04460b32eb51ec542de85dd172d0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 04:35:51 -0400 Subject: [PATCH 099/112] more cleaning up FSM --- wally-pipelined/src/mmu/pagetablewalker.sv | 159 +++++---------------- 1 file changed, 36 insertions(+), 123 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 6af6a9fd..596b400f 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -207,10 +207,6 @@ module pagetablewalker end // generate if (`XLEN == 32) begin - // *** make sure 32/34 bit addresses are being handled properly - //logic [9:0] VPN1, VPN0; - //assign VPN1 = TranslationVAdr[31:22]; - //assign VPN0 = TranslationVAdr[21:12]; // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. assign MegapageMisaligned = |(CurrentPPN[9:0]); @@ -317,130 +313,57 @@ module pagetablewalker case (WalkerState) IDLE: if (AnyTLBMissM) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; else NextWalkerState = IDLE; - - LEVEL3_SET_ADRE: begin - NextWalkerState = LEVEL3_WDV; - //TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - end - + LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV; LEVEL3_WDV: begin - //TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL3_WDV; - end else begin - NextWalkerState = LEVEL3; - PRegEn = 1'b1; + if (HPTWStall) NextWalkerState = LEVEL3_WDV; + else begin + NextWalkerState = LEVEL3; + PRegEn = 1'b1; end end - - LEVEL3: begin - if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) begin - NextWalkerState = LEAF; - //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL2_SET_ADRE; - //TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - end else begin - NextWalkerState = FAULT; - end - end - - LEVEL2_SET_ADRE: begin - NextWalkerState = LEVEL2_WDV; - //TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - end - + LEVEL3: + if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) NextWalkerState = LEAF; + else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL2_SET_ADRE; + else NextWalkerState = FAULT; + LEVEL2_SET_ADRE: NextWalkerState = LEVEL2_WDV; LEVEL2_WDV: begin - //TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL2_WDV; - end else begin - NextWalkerState = LEVEL2; - PRegEn = 1'b1; + if (HPTWStall) NextWalkerState = LEVEL2_WDV; + else begin + NextWalkerState = LEVEL2; + PRegEn = 1'b1; end end - - LEVEL2: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) begin - NextWalkerState = LEAF; - //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL1_SET_ADRE; - //TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - end else begin - NextWalkerState = FAULT; - end - end - - LEVEL1_SET_ADRE: begin - NextWalkerState = LEVEL1_WDV; - //TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - end - + LEVEL2: + if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) NextWalkerState = LEAF; + else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1_SET_ADRE; + else NextWalkerState = FAULT; + LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; LEVEL1_WDV: begin - //TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; + if (HPTWStall) NextWalkerState = LEVEL1_WDV; + else begin + NextWalkerState = LEVEL1; + PRegEn = 1'b1; end end - - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) begin - NextWalkerState = LEAF; - //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_SET_ADRE; - //TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - end else begin - NextWalkerState = FAULT; - end - end - - LEVEL0_SET_ADRE: begin - NextWalkerState = LEVEL0_WDV; - //TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - end - + LEVEL1: + if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) NextWalkerState = LEAF; + else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0_SET_ADRE; + else NextWalkerState = FAULT; + LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; LEVEL0_WDV: begin - //TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; + if (HPTWStall) NextWalkerState = LEVEL0_WDV; + else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; end end - - LEVEL0: begin - if (ValidPTE && LeafPTE && ~ADPageFault) begin - NextWalkerState = LEAF; - //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end else begin - NextWalkerState = FAULT; - end - end - + LEVEL0: + if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; + else NextWalkerState = FAULT; LEAF: begin PageTableEntry = CurrentPTE; PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? @@ -448,12 +371,9 @@ module pagetablewalker ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); DTLBWriteM = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - //TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; NextWalkerState = IDLE; end - - FAULT: begin - //SelPTW = 1'b0; + FAULT: begin // *** why do these only get raised on TLB misses? Should they always fault? NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; @@ -467,15 +387,8 @@ module pagetablewalker endcase end - - - // *** Major issue. We need the full virtual address here. - // When the TLB's are update it use use the orignal address - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; end - //endgenerate end else begin assign HPTWPAdrE = 0; assign HPTWRead = 0; From 08e494dd7deb96937a4a7a23dc81c8b6dac91125 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 04:40:01 -0400 Subject: [PATCH 100/112] HPTW: factored out PageTableENtry --- wally-pipelined/src/mmu/pagetablewalker.sv | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 596b400f..41012415 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -91,7 +91,7 @@ module pagetablewalker logic ValidPTE, ADPageFault, MegapageMisaligned, BadMegapage, LeafPTE; // Outputs of walker - logic [`XLEN-1:0] PageTableEntry; + //logic [`XLEN-1:0] PageTableEntry; logic StartWalk; logic EndWalk; @@ -153,11 +153,13 @@ module pagetablewalker assign ADPageFault = ~Accessed | (MemStore & ~Dirty); // Assign specific outputs to general outputs - assign PageTableEntryF = PageTableEntry; - assign PageTableEntryM = PageTableEntry; + // *** try to eliminate this duplication, but attempts caused MMU to hang + assign PageTableEntryF = CurrentPTE; + assign PageTableEntryM = CurrentPTE; assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT); - + assign DTLBWriteM = (WalkerState == LEAF) & DTLBMissMQ; + assign DTLBWriteM = (WalkerState == LEAF) & ~DTLBMissMQ; // *** is there a way to speed up HPTW? @@ -216,7 +218,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; HPTWRead = 1'b0; - PageTableEntry = '0; + //PageTableEntry = '0; PageType = '0; DTLBWriteM = '0; ITLBWriteF = '0; @@ -259,7 +261,7 @@ module pagetablewalker else NextWalkerState = FAULT; LEAF: begin // *** pull out datapath stuff NextWalkerState = IDLE; - PageTableEntry = CurrentPTE; + //PageTableEntry = CurrentPTE; PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? DTLBWriteM = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions @@ -301,7 +303,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; HPTWRead = 1'b0; - PageTableEntry = '0; + //PageTableEntry = '0; PageType = '0; DTLBWriteM = '0; ITLBWriteF = '0; @@ -365,7 +367,7 @@ module pagetablewalker if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; LEAF: begin - PageTableEntry = CurrentPTE; + //PageTableEntry = CurrentPTE; PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? ((PreviousWalkerState == LEVEL2) ? 2'b10 : ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); From a0f6c9aec194d59dba2e46577825469944fa8a9a Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 04:44:23 -0400 Subject: [PATCH 101/112] HPTW: factored out DTLBWrite/ITLBWrite --- wally-pipelined/src/mmu/pagetablewalker.sv | 25 +++------------------- 1 file changed, 3 insertions(+), 22 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 41012415..b6c23345 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -159,7 +159,7 @@ module pagetablewalker assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT); assign DTLBWriteM = (WalkerState == LEAF) & DTLBMissMQ; - assign DTLBWriteM = (WalkerState == LEAF) & ~DTLBMissMQ; + assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBMissMQ; // *** is there a way to speed up HPTW? @@ -218,10 +218,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; HPTWRead = 1'b0; - //PageTableEntry = '0; PageType = '0; - DTLBWriteM = '0; - ITLBWriteF = '0; WalkerInstrPageFaultF = 1'b0; WalkerLoadPageFaultM = 1'b0; @@ -239,7 +236,6 @@ module pagetablewalker PRegEn = 1'b1; end end - LEVEL1: begin if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) begin @@ -256,16 +252,11 @@ module pagetablewalker PRegEn = 1'b1; end end - LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; - LEAF: begin // *** pull out datapath stuff + LEAF: begin NextWalkerState = IDLE; - //PageTableEntry = CurrentPTE; PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - //TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end FAULT: begin @@ -303,10 +294,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; HPTWRead = 1'b0; - //PageTableEntry = '0; PageType = '0; - DTLBWriteM = '0; - ITLBWriteF = '0; WalkerInstrPageFaultF = 1'b0; WalkerLoadPageFaultM = 1'b0; @@ -367,12 +355,9 @@ module pagetablewalker if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; LEAF: begin - //PageTableEntry = CurrentPTE; PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? ((PreviousWalkerState == LEVEL2) ? 2'b10 : ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions NextWalkerState = IDLE; end FAULT: begin // *** why do these only get raised on TLB misses? Should they always fault? @@ -381,11 +366,7 @@ module pagetablewalker WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; WalkerStorePageFaultM = DTLBMissMQ && MemStore; end - - // Default case should never happen - default: begin - NextWalkerState = IDLE; - end + default: NextWalkerState = IDLE; // should never be reached endcase end From 880aa1c03aee68b8fda4c2399a9047eced1aac53 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 04:55:01 -0400 Subject: [PATCH 102/112] HPTW: more cleanup --- wally-pipelined/src/mmu/pagetablewalker.sv | 76 +++++----------------- 1 file changed, 17 insertions(+), 59 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index b6c23345..f60281d4 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -95,21 +95,11 @@ module pagetablewalker logic StartWalk; logic EndWalk; - typedef enum {LEVEL0_SET_ADRE, - LEVEL0_WDV, - LEVEL0, - LEVEL1_SET_ADRE, - LEVEL1_WDV, - LEVEL1, - LEVEL2_SET_ADRE, - LEVEL2_WDV, - LEVEL2, - LEVEL3_SET_ADRE, - LEVEL3_WDV, - LEVEL3, - LEAF, - IDLE, - FAULT} statetype; + typedef enum {LEVEL0_SET_ADRE, LEVEL0_WDV, LEVEL0, + LEVEL1_SET_ADRE, LEVEL1_WDV, LEVEL1, + LEVEL2_SET_ADRE, LEVEL2_WDV, LEVEL2, + LEVEL3_SET_ADRE, LEVEL3_WDV, LEVEL3, + LEAF, IDLE, FAULT} statetype; statetype WalkerState, NextWalkerState, PreviousWalkerState; @@ -117,13 +107,8 @@ module pagetablewalker logic SelDataTranslation; logic AnyTLBMissM; - - - assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; - assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; - assign MemStore = MemRWM[0]; // Prefer data address translations over instruction address translations @@ -137,7 +122,6 @@ module pagetablewalker flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - assign AnyTLBMissM = DTLBMissM | ITLBMissF; assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM; @@ -161,6 +145,14 @@ module pagetablewalker assign DTLBWriteM = (WalkerState == LEAF) & DTLBMissMQ; assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBMissMQ; + assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBMissMQ; //*** why do these only get raised on TLB misses? Should they always fault even for ADpagefaults, invalid addresses,etc?? + assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBMissMQ & ~MemStore; + assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBMissMQ & MemStore; + + assign PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? + ((PreviousWalkerState == LEVEL2) ? 2'b10 : + ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); + // *** is there a way to speed up HPTW? // TranslationPAdr mux @@ -218,11 +210,6 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; HPTWRead = 1'b0; - PageType = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; case (WalkerState) IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; @@ -254,27 +241,13 @@ module pagetablewalker end LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; - LEAF: begin - NextWalkerState = IDLE; - PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - end - - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end - + LEAF: NextWalkerState = IDLE; + FAULT: NextWalkerState = IDLE; // Default case should never happen, but is included for linter. default: NextWalkerState = IDLE; endcase end - - - - // Assign outputs to ahblite // *** Currently truncate address to 32 bits. This must be changed if // we support larger physical address spaces @@ -294,11 +267,6 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; HPTWRead = 1'b0; - PageType = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; case (WalkerState) IDLE: if (AnyTLBMissM) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; @@ -354,18 +322,8 @@ module pagetablewalker LEVEL0: if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; - LEAF: begin - PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? - ((PreviousWalkerState == LEVEL2) ? 2'b10 : - ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); - NextWalkerState = IDLE; - end - FAULT: begin // *** why do these only get raised on TLB misses? Should they always fault? - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end + LEAF: NextWalkerState = IDLE; + FAULT: NextWalkerState = IDLE; default: NextWalkerState = IDLE; // should never be reached endcase From ef63e1ab526d2af528ffecd1ad7dcde2e8af37be Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 11:11:10 -0400 Subject: [PATCH 103/112] hptw: factored pregen --- wally-pipelined/src/mmu/pagetablewalker.sv | 23 ++++++++----------- .../testbench/testbench-imperas.sv | 1 + 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index f60281d4..d421a79c 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -29,11 +29,6 @@ `include "wally-config.vh" -/* *** - TO-DO: - - Implement faults on accessed/dirty behavior - */ - module pagetablewalker ( // Control signals @@ -152,6 +147,7 @@ module pagetablewalker assign PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? ((PreviousWalkerState == LEVEL2) ? 2'b10 : ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); + assign PRegEn = (NextWalkerState == LEVEL3) | (NextWalkerState == LEVEL2) | (NextWalkerState == LEVEL1) | (NextWalkerState == LEVEL0); // *** is there a way to speed up HPTW? @@ -205,10 +201,9 @@ module pagetablewalker // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. assign MegapageMisaligned = |(CurrentPPN[9:0]); - // State transition logic always_comb begin - PRegEn = 1'b0; + //PRegEn = 1'b0; HPTWRead = 1'b0; case (WalkerState) @@ -220,7 +215,7 @@ module pagetablewalker if (HPTWStall) NextWalkerState = LEVEL1_WDV; else begin NextWalkerState = LEVEL1; - PRegEn = 1'b1; + //PRegEn = 1'b1; end end LEVEL1: begin @@ -236,7 +231,7 @@ module pagetablewalker if (HPTWStall) NextWalkerState = LEVEL0_WDV; else begin NextWalkerState = LEVEL0; - PRegEn = 1'b1; + //PRegEn = 1'b1; end end LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; @@ -265,7 +260,7 @@ module pagetablewalker assign MegapageMisaligned = |(CurrentPPN[8:0]); always_comb begin - PRegEn = 1'b0; + //PRegEn = 1'b0; HPTWRead = 1'b0; case (WalkerState) @@ -277,7 +272,7 @@ module pagetablewalker if (HPTWStall) NextWalkerState = LEVEL3_WDV; else begin NextWalkerState = LEVEL3; - PRegEn = 1'b1; + //PRegEn = 1'b1; end end LEVEL3: @@ -290,7 +285,7 @@ module pagetablewalker if (HPTWStall) NextWalkerState = LEVEL2_WDV; else begin NextWalkerState = LEVEL2; - PRegEn = 1'b1; + //PRegEn = 1'b1; end end LEVEL2: @@ -303,7 +298,7 @@ module pagetablewalker if (HPTWStall) NextWalkerState = LEVEL1_WDV; else begin NextWalkerState = LEVEL1; - PRegEn = 1'b1; + //PRegEn = 1'b1; end end LEVEL1: @@ -316,7 +311,7 @@ module pagetablewalker if (HPTWStall) NextWalkerState = LEVEL0_WDV; else begin NextWalkerState = LEVEL0; - PRegEn = 1'b1; + //PRegEn = 1'b1; end end LEVEL0: diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 46dfd00b..4f805536 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -746,6 +746,7 @@ module riscvassertions(); initial begin assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries"); assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float"); + assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); end endmodule From 708f8cc3a25678c3e1aafafa183e5ca6b4b8b133 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 11:25:52 -0400 Subject: [PATCH 104/112] hptw: factored HPTWRead --- wally-pipelined/src/mmu/pagetablewalker.sv | 62 +++++++++------------- 1 file changed, 25 insertions(+), 37 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index d421a79c..04a84f5c 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -144,10 +144,18 @@ module pagetablewalker assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBMissMQ & ~MemStore; assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBMissMQ & MemStore; - assign PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? + always_comb // determine type of page being walked: + case (PreviousWalkerState) + LEVEL3: PageType = 2'b11; // terapage + LEVEL2: PageType = 2'b10; // gigapage + LEVEL1: PageType = 2'b01; // megapage + default: PageType = 2'b00; // kilopage + endcase +/* assign PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // is ((PreviousWalkerState == LEVEL2) ? 2'b10 : - ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); + ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00));*/ assign PRegEn = (NextWalkerState == LEVEL3) | (NextWalkerState == LEVEL2) | (NextWalkerState == LEVEL1) | (NextWalkerState == LEVEL0); + assign HPTWRead = (WalkerState == LEVEL3_WDV) | (WalkerState == LEVEL2_WDV) | (WalkerState == LEVEL1_WDV) | (WalkerState == LEVEL0_WDV); // is this really necessary? // *** is there a way to speed up HPTW? @@ -203,36 +211,29 @@ module pagetablewalker // State transition logic always_comb begin - //PRegEn = 1'b0; - HPTWRead = 1'b0; + //HPTWRead = 1'b0; case (WalkerState) IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; else NextWalkerState = IDLE; LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; LEVEL1_WDV: begin - HPTWRead = 1'b1; + //HPTWRead = 1'b1; if (HPTWStall) NextWalkerState = LEVEL1_WDV; - else begin - NextWalkerState = LEVEL1; - //PRegEn = 1'b1; - end + else NextWalkerState = LEVEL1; end LEVEL1: begin if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL0_SET_ADRE; - HPTWRead = 1'b1; + //HPTWRead = 1'b1; // *** seems this shouldn't be asserted here end else NextWalkerState = FAULT; end LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; LEVEL0_WDV: begin - HPTWRead = 1'b1; + //HPTWRead = 1'b1; if (HPTWStall) NextWalkerState = LEVEL0_WDV; - else begin - NextWalkerState = LEVEL0; - //PRegEn = 1'b1; - end + else NextWalkerState = LEVEL0; end LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; @@ -260,20 +261,16 @@ module pagetablewalker assign MegapageMisaligned = |(CurrentPPN[8:0]); always_comb begin - //PRegEn = 1'b0; - HPTWRead = 1'b0; + //HPTWRead = 1'b0; case (WalkerState) IDLE: if (AnyTLBMissM) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; else NextWalkerState = IDLE; LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV; LEVEL3_WDV: begin - HPTWRead = 1'b1; + //HPTWRead = 1'b1; if (HPTWStall) NextWalkerState = LEVEL3_WDV; - else begin - NextWalkerState = LEVEL3; - //PRegEn = 1'b1; - end + else NextWalkerState = LEVEL3; end LEVEL3: if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) NextWalkerState = LEAF; @@ -281,12 +278,9 @@ module pagetablewalker else NextWalkerState = FAULT; LEVEL2_SET_ADRE: NextWalkerState = LEVEL2_WDV; LEVEL2_WDV: begin - HPTWRead = 1'b1; + //HPTWRead = 1'b1; if (HPTWStall) NextWalkerState = LEVEL2_WDV; - else begin - NextWalkerState = LEVEL2; - //PRegEn = 1'b1; - end + else NextWalkerState = LEVEL2; end LEVEL2: if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) NextWalkerState = LEAF; @@ -294,12 +288,9 @@ module pagetablewalker else NextWalkerState = FAULT; LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; LEVEL1_WDV: begin - HPTWRead = 1'b1; + //HPTWRead = 1'b1; if (HPTWStall) NextWalkerState = LEVEL1_WDV; - else begin - NextWalkerState = LEVEL1; - //PRegEn = 1'b1; - end + else NextWalkerState = LEVEL1; end LEVEL1: if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) NextWalkerState = LEAF; @@ -307,12 +298,9 @@ module pagetablewalker else NextWalkerState = FAULT; LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; LEVEL0_WDV: begin - HPTWRead = 1'b1; + //HPTWRead = 1'b1; if (HPTWStall) NextWalkerState = LEVEL0_WDV; - else begin - NextWalkerState = LEVEL0; - //PRegEn = 1'b1; - end + else NextWalkerState = LEVEL0; end LEVEL0: if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; From fa12727bbba953d44f8b47284e7b4eee1909bd4b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 11:25:59 -0400 Subject: [PATCH 105/112] hptw: factored HPTWRead --- wally-pipelined/src/mmu/pagetablewalker.sv | 39 +++++----------------- 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 04a84f5c..23040772 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -211,28 +211,20 @@ module pagetablewalker // State transition logic always_comb begin - //HPTWRead = 1'b0; - - case (WalkerState) +å case (WalkerState) IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; else NextWalkerState = IDLE; LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; - LEVEL1_WDV: begin - //HPTWRead = 1'b1; - if (HPTWStall) NextWalkerState = LEVEL1_WDV; + LEVEL1_WDV: if (HPTWStall) NextWalkerState = LEVEL1_WDV; else NextWalkerState = LEVEL1; - end LEVEL1: begin if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL0_SET_ADRE; - //HPTWRead = 1'b1; // *** seems this shouldn't be asserted here end else NextWalkerState = FAULT; end LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; - LEVEL0_WDV: begin - //HPTWRead = 1'b1; - if (HPTWStall) NextWalkerState = LEVEL0_WDV; + LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV; else NextWalkerState = LEVEL0; end LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; @@ -261,47 +253,34 @@ module pagetablewalker assign MegapageMisaligned = |(CurrentPPN[8:0]); always_comb begin - //HPTWRead = 1'b0; - case (WalkerState) IDLE: if (AnyTLBMissM) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; else NextWalkerState = IDLE; LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV; - LEVEL3_WDV: begin - //HPTWRead = 1'b1; - if (HPTWStall) NextWalkerState = LEVEL3_WDV; + LEVEL3_WDV: if (HPTWStall) NextWalkerState = LEVEL3_WDV; else NextWalkerState = LEVEL3; - end LEVEL3: if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL2_SET_ADRE; else NextWalkerState = FAULT; LEVEL2_SET_ADRE: NextWalkerState = LEVEL2_WDV; - LEVEL2_WDV: begin - //HPTWRead = 1'b1; - if (HPTWStall) NextWalkerState = LEVEL2_WDV; + LEVEL2_WDV: if (HPTWStall) NextWalkerState = LEVEL2_WDV; else NextWalkerState = LEVEL2; - end LEVEL2: if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1_SET_ADRE; else NextWalkerState = FAULT; LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; - LEVEL1_WDV: begin - //HPTWRead = 1'b1; - if (HPTWStall) NextWalkerState = LEVEL1_WDV; + LEVEL1_WDV: if (HPTWStall) NextWalkerState = LEVEL1_WDV; else NextWalkerState = LEVEL1; - end LEVEL1: if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) NextWalkerState = LEAF; else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0_SET_ADRE; else NextWalkerState = FAULT; LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; - LEVEL0_WDV: begin - //HPTWRead = 1'b1; - if (HPTWStall) NextWalkerState = LEVEL0_WDV; - else NextWalkerState = LEVEL0; - end + LEVEL0_WDV: + if (HPTWStall) NextWalkerState = LEVEL0_WDV; + else NextWalkerState = LEVEL0; LEVEL0: if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; From 9cee6c22814de0cc0981e3f71b00c8b3b4cdcde0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 11:31:16 -0400 Subject: [PATCH 106/112] hptw: factored Misaligned --- wally-pipelined/src/mmu/pagetablewalker.sv | 34 +++++++++------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 23040772..0c0855e5 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -78,15 +78,8 @@ module pagetablewalker logic [`PPN_BITS-1:0] CurrentPPN; logic [`SVMODE_BITS-1:0] SvMode; logic MemStore; - - // PTE Control Bits - logic Dirty, Accessed, Global, User, - Executable, Writable, Readable, Valid; - // PTE descriptions - logic ValidPTE, ADPageFault, MegapageMisaligned, BadMegapage, LeafPTE; - - // Outputs of walker - //logic [`XLEN-1:0] PageTableEntry; + logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid; + logic ValidPTE, ADPageFault, MegapageMisaligned, TerapageMisaligned, GigapageMisaligned, BadMegapage, LeafPTE; logic StartWalk; logic EndWalk; @@ -203,15 +196,24 @@ module pagetablewalker default: TranslationPAdr = 0; // cause seg fault if this is improperly used endcase end + + if (`XLEN == 32) begin + assign TerapageMisaligned = 0; // not applicable + assign GigapageMisaligned = 0; // not applicable + assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 + end else begin + assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0 + assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0 + assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0 + end // generate if (`XLEN == 32) begin // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[9:0]); // State transition logic always_comb begin -å case (WalkerState) + case (WalkerState) IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; else NextWalkerState = IDLE; LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; @@ -226,7 +228,6 @@ module pagetablewalker LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV; else NextWalkerState = LEVEL0; - end LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; else NextWalkerState = FAULT; LEAF: NextWalkerState = IDLE; @@ -242,15 +243,6 @@ module pagetablewalker assign HPTWPAdrE = TranslationPAdr[31:0]; end else begin - logic TerapageMisaligned, GigapageMisaligned; - // A terapage is a level 3 leaf page. This page must have zero PPN[2], - // zero PPN[1], and zero PPN[0] - assign TerapageMisaligned = |(CurrentPPN[26:0]); - // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and - // zero PPN[0] - assign GigapageMisaligned = |(CurrentPPN[17:0]); - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[8:0]); always_comb begin case (WalkerState) From 4469b5a4b3cbb58293b00a38d2143c08b787560d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 11:33:16 -0400 Subject: [PATCH 107/112] hptw: default state should be unreachable --- wally-pipelined/src/mmu/pagetablewalker.sv | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 0c0855e5..4e906cc9 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -201,6 +201,7 @@ module pagetablewalker assign TerapageMisaligned = 0; // not applicable assign GigapageMisaligned = 0; // not applicable assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 + assign HPTWPAdrE = TranslationPAdr[31:0]; // ***not right? end else begin assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0 assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0 @@ -232,15 +233,16 @@ module pagetablewalker else NextWalkerState = FAULT; LEAF: NextWalkerState = IDLE; FAULT: NextWalkerState = IDLE; - // Default case should never happen, but is included for linter. - default: NextWalkerState = IDLE; + default: begin + $error("Default state in HPTW should be unreachable") + NextWalkerState = IDLE; // should never be reached + end endcase end // Assign outputs to ahblite // *** Currently truncate address to 32 bits. This must be changed if // we support larger physical address spaces - assign HPTWPAdrE = TranslationPAdr[31:0]; end else begin @@ -278,7 +280,10 @@ module pagetablewalker else NextWalkerState = FAULT; LEAF: NextWalkerState = IDLE; FAULT: NextWalkerState = IDLE; - default: NextWalkerState = IDLE; // should never be reached + default: begin + $error("Default state in HPTW should be unreachable") + NextWalkerState = IDLE; // should never be reached + end endcase end From cf0975c93779205f62cef1fcab41361193f7ecc0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 11:41:43 -0400 Subject: [PATCH 108/112] hptw: FSM simplification --- wally-pipelined/src/mmu/pagetablewalker.sv | 76 ++++++++++------------ 1 file changed, 35 insertions(+), 41 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 4e906cc9..2303f707 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -206,12 +206,10 @@ module pagetablewalker assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0 assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0 assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0 - end + assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + end // generate if (`XLEN == 32) begin - - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - // State transition logic always_comb begin case (WalkerState) @@ -234,7 +232,7 @@ module pagetablewalker LEAF: NextWalkerState = IDLE; FAULT: NextWalkerState = IDLE; default: begin - $error("Default state in HPTW should be unreachable") + $error("Default state in HPTW should be unreachable"); NextWalkerState = IDLE; // should never be reached end endcase @@ -248,47 +246,43 @@ module pagetablewalker always_comb begin case (WalkerState) - IDLE: if (AnyTLBMissM) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; - else NextWalkerState = IDLE; - LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV; - LEVEL3_WDV: if (HPTWStall) NextWalkerState = LEVEL3_WDV; - else NextWalkerState = LEVEL3; - LEVEL3: - if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) NextWalkerState = LEAF; - else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL2_SET_ADRE; - else NextWalkerState = FAULT; - LEVEL2_SET_ADRE: NextWalkerState = LEVEL2_WDV; - LEVEL2_WDV: if (HPTWStall) NextWalkerState = LEVEL2_WDV; - else NextWalkerState = LEVEL2; - LEVEL2: - if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) NextWalkerState = LEAF; - else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1_SET_ADRE; - else NextWalkerState = FAULT; - LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; - LEVEL1_WDV: if (HPTWStall) NextWalkerState = LEVEL1_WDV; - else NextWalkerState = LEVEL1; - LEVEL1: - if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) NextWalkerState = LEAF; - else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0_SET_ADRE; - else NextWalkerState = FAULT; - LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; - LEVEL0_WDV: - if (HPTWStall) NextWalkerState = LEVEL0_WDV; - else NextWalkerState = LEVEL0; - LEVEL0: - if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; - else NextWalkerState = FAULT; - LEAF: NextWalkerState = IDLE; - FAULT: NextWalkerState = IDLE; + IDLE: if (AnyTLBMissM) + if (`XLEN == 64) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; + else NextWalkerState = LEVEL1_SET_ADRE; + else NextWalkerState = IDLE; + LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV; + LEVEL3_WDV: if (HPTWStall) NextWalkerState = LEVEL3_WDV; + else NextWalkerState = LEVEL3; + LEVEL3: if (ValidPTE && LeafPTE && ~(TerapageMisaligned || ADPageFault)) NextWalkerState = LEAF; + else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL2_SET_ADRE; + else NextWalkerState = FAULT; + LEVEL2_SET_ADRE: NextWalkerState = LEVEL2_WDV; + LEVEL2_WDV: if (HPTWStall) NextWalkerState = LEVEL2_WDV; + else NextWalkerState = LEVEL2; + LEVEL2: if (ValidPTE && LeafPTE && ~(GigapageMisaligned || ADPageFault)) NextWalkerState = LEAF; + else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1_SET_ADRE; + else NextWalkerState = FAULT; + LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; + LEVEL1_WDV: if (HPTWStall) NextWalkerState = LEVEL1_WDV; + else NextWalkerState = LEVEL1; + LEVEL1: if (ValidPTE && LeafPTE && ~(MegapageMisaligned || ADPageFault)) NextWalkerState = LEAF; + else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0_SET_ADRE; + else NextWalkerState = FAULT; + LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; + LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV; + else NextWalkerState = LEVEL0; + LEVEL0: if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; + else NextWalkerState = FAULT; + LEAF: NextWalkerState = IDLE; + FAULT: NextWalkerState = IDLE; default: begin - $error("Default state in HPTW should be unreachable") - NextWalkerState = IDLE; // should never be reached + $error("Default state in HPTW should be unreachable"); + NextWalkerState = IDLE; // should never be reached end endcase end - assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; - end + end end else begin assign HPTWPAdrE = 0; assign HPTWRead = 0; From 0a6622a6fb6a2a3bf3f4326a28e4929ba35bbf21 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 11:55:24 -0400 Subject: [PATCH 109/112] hptw: Merged RV32/64 FSMs --- wally-pipelined/src/mmu/pagetablewalker.sv | 61 ++++------------------ 1 file changed, 9 insertions(+), 52 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 2303f707..63f57543 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -76,7 +76,6 @@ module pagetablewalker logic [`XLEN-1:0] CurrentPTE; logic [`PA_BITS-1:0] TranslationPAdr; logic [`PPN_BITS-1:0] CurrentPPN; - logic [`SVMODE_BITS-1:0] SvMode; logic MemStore; logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid; logic ValidPTE, ADPageFault, MegapageMisaligned, TerapageMisaligned, GigapageMisaligned, BadMegapage, LeafPTE; @@ -89,13 +88,15 @@ module pagetablewalker LEVEL3_SET_ADRE, LEVEL3_WDV, LEVEL3, LEAF, IDLE, FAULT} statetype; - statetype WalkerState, NextWalkerState, PreviousWalkerState; + statetype WalkerState, NextWalkerState, PreviousWalkerState, InitialWalkerState; logic PRegEn; logic SelDataTranslation; logic AnyTLBMissM; + logic [`SVMODE_BITS-1:0] SvMode; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; + assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; assign MemStore = MemRWM[0]; @@ -115,11 +116,8 @@ module pagetablewalker assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM; assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT); - // unswizzle PTE bits - assign {Dirty, Accessed, Global, User, - Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; - // Assign PTE descriptors common across all XLEN values + assign {Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; assign LeafPTE = Executable | Writable | Readable; assign ValidPTE = Valid && ~(Writable && ~Readable); assign ADPageFault = ~Accessed | (MemStore & ~Dirty); @@ -144,9 +142,6 @@ module pagetablewalker LEVEL1: PageType = 2'b01; // megapage default: PageType = 2'b00; // kilopage endcase -/* assign PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // is - ((PreviousWalkerState == LEVEL2) ? 2'b10 : - ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00));*/ assign PRegEn = (NextWalkerState == LEVEL3) | (NextWalkerState == LEVEL2) | (NextWalkerState == LEVEL1) | (NextWalkerState == LEVEL0); assign HPTWRead = (WalkerState == LEVEL3_WDV) | (WalkerState == LEVEL2_WDV) | (WalkerState == LEVEL1_WDV) | (WalkerState == LEVEL0_WDV); // is this really necessary? @@ -198,57 +193,22 @@ module pagetablewalker end if (`XLEN == 32) begin + assign InitialWalkerState = LEVEL1_SET_ADRE; assign TerapageMisaligned = 0; // not applicable assign GigapageMisaligned = 0; // not applicable assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 assign HPTWPAdrE = TranslationPAdr[31:0]; // ***not right? end else begin + assign InitialWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0 assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0 assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0 assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; end - // generate - if (`XLEN == 32) begin - // State transition logic - always_comb begin + + always_comb case (WalkerState) - IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; - else NextWalkerState = IDLE; - LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV; - LEVEL1_WDV: if (HPTWStall) NextWalkerState = LEVEL1_WDV; - else NextWalkerState = LEVEL1; - LEVEL1: begin - if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) NextWalkerState = LEAF; - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_SET_ADRE; - end else NextWalkerState = FAULT; - end - LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV; - LEVEL0_WDV: if (HPTWStall) NextWalkerState = LEVEL0_WDV; - else NextWalkerState = LEVEL0; - LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF; - else NextWalkerState = FAULT; - LEAF: NextWalkerState = IDLE; - FAULT: NextWalkerState = IDLE; - default: begin - $error("Default state in HPTW should be unreachable"); - NextWalkerState = IDLE; // should never be reached - end - endcase - end - - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - - end else begin - - always_comb begin - case (WalkerState) - IDLE: if (AnyTLBMissM) - if (`XLEN == 64) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE; - else NextWalkerState = LEVEL1_SET_ADRE; + IDLE: if (AnyTLBMissM) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV; LEVEL3_WDV: if (HPTWStall) NextWalkerState = LEVEL3_WDV; @@ -279,10 +239,7 @@ module pagetablewalker $error("Default state in HPTW should be unreachable"); NextWalkerState = IDLE; // should never be reached end - endcase - end - end end else begin assign HPTWPAdrE = 0; assign HPTWRead = 0; From 784e6cf5389e945d59116e4eb3c89e90b67f3a35 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 12:01:43 -0400 Subject: [PATCH 110/112] hptw: Renamed Memstore to MemWrite --- wally-pipelined/src/mmu/pagetablewalker.sv | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 63f57543..5ca42801 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -76,7 +76,7 @@ module pagetablewalker logic [`XLEN-1:0] CurrentPTE; logic [`PA_BITS-1:0] TranslationPAdr; logic [`PPN_BITS-1:0] CurrentPPN; - logic MemStore; + logic MemWrite; logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid; logic ValidPTE, ADPageFault, MegapageMisaligned, TerapageMisaligned, GigapageMisaligned, BadMegapage, LeafPTE; logic StartWalk; @@ -96,9 +96,9 @@ module pagetablewalker logic [`SVMODE_BITS-1:0] SvMode; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; - + assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; - assign MemStore = MemRWM[0]; + assign MemWrite = MemRWM[0]; // Prefer data address translations over instruction address translations assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; @@ -120,7 +120,7 @@ module pagetablewalker assign {Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; assign LeafPTE = Executable | Writable | Readable; assign ValidPTE = Valid && ~(Writable && ~Readable); - assign ADPageFault = ~Accessed | (MemStore & ~Dirty); + assign ADPageFault = ~Accessed | (MemWrite & ~Dirty); // Assign specific outputs to general outputs // *** try to eliminate this duplication, but attempts caused MMU to hang @@ -132,8 +132,8 @@ module pagetablewalker assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBMissMQ; assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBMissMQ; //*** why do these only get raised on TLB misses? Should they always fault even for ADpagefaults, invalid addresses,etc?? - assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBMissMQ & ~MemStore; - assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBMissMQ & MemStore; + assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBMissMQ & ~MemWrite; + assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBMissMQ & MemWrite; always_comb // determine type of page being walked: case (PreviousWalkerState) @@ -206,6 +206,7 @@ module pagetablewalker assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; end + // Walker FSM always_comb case (WalkerState) IDLE: if (AnyTLBMissM) NextWalkerState = InitialWalkerState; From ea2aa469a1df0d20a8f70fcf449d9af8908359c0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 12:07:51 -0400 Subject: [PATCH 111/112] hptw: Simplifed out AnyTLBMiss --- wally-pipelined/src/mmu/pagetablewalker.sv | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 5ca42801..cd080a8f 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -92,7 +92,6 @@ module pagetablewalker logic PRegEn; logic SelDataTranslation; - logic AnyTLBMissM; logic [`SVMODE_BITS-1:0] SvMode; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; @@ -111,14 +110,12 @@ module pagetablewalker flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - assign AnyTLBMissM = DTLBMissM | ITLBMissF; - - assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM; + assign StartWalk = (WalkerState == IDLE) & (DTLBMissM | ITLBMissF); assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT); // Assign PTE descriptors common across all XLEN values assign {Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; - assign LeafPTE = Executable | Writable | Readable; + assign LeafPTE = Executable | Readable; // leaf PTE never has only Writable assign ValidPTE = Valid && ~(Writable && ~Readable); assign ADPageFault = ~Accessed | (MemWrite & ~Dirty); @@ -209,7 +206,7 @@ module pagetablewalker // Walker FSM always_comb case (WalkerState) - IDLE: if (AnyTLBMissM) NextWalkerState = InitialWalkerState; + IDLE: if (StartWalk) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; LEVEL3_SET_ADRE: NextWalkerState = LEVEL3_WDV; LEVEL3_WDV: if (HPTWStall) NextWalkerState = LEVEL3_WDV; From 87aa527de7a2145ef2e1592a2c82849fd84d2d62 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 13:40:12 -0400 Subject: [PATCH 112/112] hptw: minor cleanup --- wally-pipelined/regression/wally-busybear-batch.do | 1 - wally-pipelined/regression/wally-pipelined-batch.do | 7 +++++++ wally-pipelined/src/lsu/lsu.sv | 2 -- wally-pipelined/src/lsu/lsuArb.sv | 3 --- wally-pipelined/src/mmu/pagetablewalker.sv | 4 +--- wally-pipelined/testbench/testbench-imperas.sv | 7 +------ 6 files changed, 9 insertions(+), 15 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear-batch.do b/wally-pipelined/regression/wally-busybear-batch.do index e2817dfa..e9beed4c 100644 --- a/wally-pipelined/regression/wally-busybear-batch.do +++ b/wally-pipelined/regression/wally-busybear-batch.do @@ -32,7 +32,6 @@ vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared .. # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt work_busybear.testbench -o workopt_busybear - vsim workopt_busybear -suppress 8852,12070 run -all diff --git a/wally-pipelined/regression/wally-pipelined-batch.do b/wally-pipelined/regression/wally-pipelined-batch.do index 49ed8cf7..1e67b836 100644 --- a/wally-pipelined/regression/wally-pipelined-batch.do +++ b/wally-pipelined/regression/wally-pipelined-batch.do @@ -38,6 +38,13 @@ switch $argc { # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt work_$2.testbench -work work_$2 -o workopt_$2 vsim -lib work_$2 workopt_$2 +# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time +#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf +#vsim -coverage -lib work_$2 workopt_$2 run -all +#coverage report -file wally-pipelined-coverage.txt +# These aren't doing anything helpful +#coverage report -memory +#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 quit diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 46f174a9..81a22f79 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -121,7 +121,6 @@ module lsu logic [`XLEN-1:0] PageTableEntryM; logic DTLBWriteM; logic [`XLEN-1:0] HPTWReadPTE; - logic MMUReady; logic HPTWStall; logic [`XLEN-1:0] HPTWPAdrE; logic [`XLEN-1:0] HPTWPAdrM; @@ -164,7 +163,6 @@ module lsu .ITLBWriteF(ITLBWriteF), .DTLBWriteM(DTLBWriteM), .HPTWReadPTE(HPTWReadPTE), - .MMUReady(HPTWReady), .HPTWStall(HPTWStall), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 13a77243..d84c2d60 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -34,8 +34,6 @@ module lsuArb input logic HPTWRead, input logic [`XLEN-1:0] HPTWPAdrE, input logic [`XLEN-1:0] HPTWPAdrM, - // to page table walker. - //output logic [`XLEN-1:0] HPTWReadPTE, output logic HPTWStall, // from CPU @@ -94,7 +92,6 @@ module lsuArb // demux the inputs from LSU to walker or cpu's data port. assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux - //assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache; assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index cd080a8f..02d20632 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -49,7 +49,6 @@ module pagetablewalker // *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU input logic [`XLEN-1:0] HPTWReadPTE, - input logic MMUReady, input logic HPTWStall, // *** modify to send to LSU @@ -140,8 +139,7 @@ module pagetablewalker default: PageType = 2'b00; // kilopage endcase assign PRegEn = (NextWalkerState == LEVEL3) | (NextWalkerState == LEVEL2) | (NextWalkerState == LEVEL1) | (NextWalkerState == LEVEL0); - assign HPTWRead = (WalkerState == LEVEL3_WDV) | (WalkerState == LEVEL2_WDV) | (WalkerState == LEVEL1_WDV) | (WalkerState == LEVEL0_WDV); // is this really necessary? - + assign HPTWRead = (WalkerState == LEVEL3_WDV) | (WalkerState == LEVEL2_WDV) | (WalkerState == LEVEL1_WDV) | (WalkerState == LEVEL0_WDV); // *** is there a way to speed up HPTW? // TranslationPAdr mux diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 4f805536..8559c555 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -283,7 +283,6 @@ string tests32f[] = '{ "rv64i/WALLY-SLLI", "3000", "rv64i/WALLY-SRLI", "3000", "rv64i/WALLY-SRAI", "3000", - "rv64i/WALLY-JAL", "4000", "rv64i/WALLY-JALR", "3000", "rv64i/WALLY-STORE", "3000", @@ -511,11 +510,7 @@ string tests32f[] = '{ logic [`XLEN-1:0] PCW; logic DCacheFlushDone, DCacheFlushStart; - - - logic [`XLEN-1:0] debug; - assign debug = dut.uncore.dtim.RAM[536872960]; - + flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);