From 580ac1c4df12dbca650c54ad4f43eac8f873b663 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 18 Jun 2021 09:36:22 -0400
Subject: [PATCH] Made MemPAdrM and related signals PA_BITS wide

---
 wally-pipelined/src/dmem/dcache.sv              | 12 ++++++------
 wally-pipelined/src/dmem/dmem.sv                | 12 ++----------
 wally-pipelined/src/ebu/ahblite.sv              |  2 +-
 wally-pipelined/src/wally/wallypipelinedhart.sv |  3 ++-
 4 files changed, 11 insertions(+), 18 deletions(-)

diff --git a/wally-pipelined/src/dmem/dcache.sv b/wally-pipelined/src/dmem/dcache.sv
index 243c6975..fec70ef4 100644
--- a/wally-pipelined/src/dmem/dcache.sv
+++ b/wally-pipelined/src/dmem/dcache.sv
@@ -31,7 +31,7 @@ module dcache(
   input  logic              StallW,
   input  logic              FlushW,
   // Upper bits of physical address
-  input  logic [`XLEN-1:12] UpperPAdrM,
+  input  logic [`PA_BITS-1:12] UpperPAdrM,
   // Lower 12 bits of virtual address, since it's faster this way
   input  logic [11:0]       LowerVAdrM,
   // Write to the dcache
@@ -41,7 +41,7 @@ module dcache(
   input  logic [`XLEN-1:0]  ReadDataW,
   input  logic              MemAckW,
   // Access requested from the ebu unit
-  output logic [`XLEN-1:0]  MemPAdrM,
+  output logic [`PA_BITS-1:0]  MemPAdrM,
   output logic              MemReadM, MemWriteM,
   // High if the dcache is requesting a stall
   output logic              DCacheStallW,
@@ -56,7 +56,7 @@ module dcache(
 
     // Input signals to cache memory
     logic                       FlushMem;
-    logic [`XLEN-1:12]          DCacheMemUpperPAdr;
+    logic [`PA_BITS-1:12]       DCacheMemUpperPAdr;
     logic [11:0]                DCacheMemLowerAdr;
     logic                       DCacheMemWriteEnable;
     logic [DCACHELINESIZE-1:0]  DCacheMemWriteData;
@@ -98,7 +98,7 @@ module dcachecontroller #(parameter LINESIZE = 256) (
 
     // Input the address to read
     // The upper bits of the physical pc
-    input  logic [`XLEN-1:12]   DCacheMemUpperPAdr,
+    input  logic [`PA_BITS-1:12]   DCacheMemUpperPAdr,
     // The lower bits of the virtual pc
     input  logic [11:0]         DCacheMemLowerAdr,
 
@@ -122,7 +122,7 @@ module dcachecontroller #(parameter LINESIZE = 256) (
     input  logic [`XLEN-1:0] ReadDataW,
     input  logic             MemAckW,
     // The read we request from main memory
-    output logic [`XLEN-1:0] MemPAdrM,
+    output logic [`PA_BITS-1:0] MemPAdrM,
     output logic             MemReadM, MemWriteM
 );
 
@@ -144,7 +144,7 @@ module dcachecontroller #(parameter LINESIZE = 256) (
 
     logic               FetchState, BeginFetchState;
     logic [LOGWPL:0]    FetchWordNum, NextFetchWordNum;
-    logic [`XLEN-1:0]   LineAlignedPCPF;
+    logic [`PA_BITS-1:0]   LineAlignedPCPF;
 
     flopr #(1) FetchStateFlop(clk, reset, BeginFetchState | (FetchState & ~EndFetchState), FetchState);
     flopr #(LOGWPL+1) FetchWordNumFlop(clk, reset, NextFetchWordNum, FetchWordNum);
diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv
index 65791300..ba3617d0 100644
--- a/wally-pipelined/src/dmem/dmem.sv
+++ b/wally-pipelined/src/dmem/dmem.sv
@@ -40,7 +40,7 @@ module dmem (
   input  logic [`XLEN-1:0] WriteDataM, 
   input  logic [1:0]       AtomicM,
   input  logic             CommitM,
-  output logic [`XLEN-1:0] MemPAdrM,
+  output logic [`PA_BITS-1:0] MemPAdrM,
   output logic             MemReadM, MemWriteM,
   output logic [1:0]       AtomicMaskedM,
   output logic             DataMisalignedM,
@@ -87,8 +87,6 @@ module dmem (
   logic [1:0] CurrState, NextState;
   logic preCommittedM;
 
-  logic [`PA_BITS-1:0] MemPAdrMmmu;
-
   localparam STATE_READY = 0;
   localparam STATE_FETCH = 1;
   localparam STATE_FETCH_AMO = 2;
@@ -97,16 +95,10 @@ module dmem (
   logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
   // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
   
-  generate
-    if (`XLEN==32)
-      assign MemPAdrM = MemPAdrMmmu[31:0];
-    else
-      assign MemPAdrM = {8'b0, MemPAdrMmmu};
-  endgenerate
   mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM),
                 .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM),
                 .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
-                .PhysicalAddress(MemPAdrMmmu), .TLBMiss(DTLBMissM),
+                .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),
                 .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM),
 
                 .ExecuteAccessF(1'b0),
diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index ea76556c..88e8f27a 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -47,7 +47,7 @@ module ahblite (
   output logic [`XLEN-1:0] InstrRData,
   output logic             InstrAckF,
   // Signals from Data Cache
-  input  logic [`XLEN-1:0] MemPAdrM,
+  input  logic [`PA_BITS-1:0] MemPAdrM,
   input  logic             MemReadM, MemWriteM,
   input  logic [`XLEN-1:0] WriteDataM,
   input  logic [1:0]       MemSizeM,
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 2535eef3..c2dfd437 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -135,7 +135,8 @@ module wallypipelinedhart (
   logic             MemReadM, MemWriteM;
   logic [1:0] 	    AtomicMaskedM;
   logic [2:0]       Funct3M;
-  logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM;
+  logic [`XLEN-1:0] MemAdrM, WriteDataM;
+  logic [`PA_BITS-1:0] MemPAdrM;
   logic [`XLEN-1:0] ReadDataW;
   logic [`XLEN-1:0] InstrPAdrF;
   logic [`XLEN-1:0] InstrRData;