From 57a70748001799f3e9e2dcdba1d8055fb998cd2d Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Fri, 25 Jun 2021 15:07:41 -0500
Subject: [PATCH] Some progress.  Had to change how the page table walker got
 it's ready.

---
 wally-pipelined/src/lsu/lsu.sv                  | 6 +++++-
 wally-pipelined/src/lsu/lsuArb.sv               | 3 ++-
 wally-pipelined/src/wally/wallypipelinedhart.sv | 7 ++++++-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 8063ae48..37a44a93 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -32,6 +32,7 @@ module lsu (
   input  logic             clk, reset,
   input  logic             StallM, FlushM, StallW, FlushW,
   output logic             DataStall,
+  output logic             HPTWReady,
   // Memory Stage
 
   // connected to cpu (controls)
@@ -197,6 +198,8 @@ module lsu (
 
   // Data stall
   //assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2);
+  assign HPTWReady = (CurrState == STATE_READY);
+  
 
   // Ross Thompson April 22, 2021
   // for now we need to handle the issue where the data memory interface repeately
@@ -221,13 +224,14 @@ module lsu (
           NextState = STATE_READY;
 	  DataStall = 1'b0;
 	end
-      STATE_FETCH_AMO_1:
+      STATE_FETCH_AMO_1: begin
 	DataStall = 1'b1;
 	if (MemAckW) begin
 	  NextState = STATE_FETCH_AMO_2;
 	end else begin 
 	  NextState = STATE_FETCH_AMO_1;
 	end
+      end
       STATE_FETCH_AMO_2: begin
 	DataStall = 1'b1;	
 	if (MemAckW & ~StallW) begin
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index 158bdbb2..e1a3b996 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -61,6 +61,7 @@ module lsuArb
    input logic 		    SquashSCWfromLSU,
    input logic 		    DataMisalignedMfromLSU,
    input logic [`XLEN-1:0]  ReadDataWFromLSU,
+   input logic              HPTWReadyfromLSU,		    
    input logic 		    DataStall
   
    );
@@ -131,7 +132,7 @@ module lsuArb
   assign CommittedM = SelPTW ? 1'b0 : CommittedMfromLSU;
   assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromLSU;
   assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromLSU;
-  assign HPTWReady = ~ DataStall;
+  assign HPTWReady = HPTWReadyfromLSU;
   assign DCacheStall = DataStall; // *** this is probably going to change.
   
 endmodule
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index e494d346..3985adae 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -131,6 +131,8 @@ module wallypipelinedhart
   logic [`XLEN-1:0] 	    MMUPAdr, MMUReadPTE;
   logic 		    MMUStall;
   logic 		    MMUTranslate, MMUReady;
+  logic 		    HPTWReadyfromLSU;
+  
 
   // bus interface to dmem
   logic 		    MemReadM, MemWriteM;
@@ -219,6 +221,7 @@ module wallypipelinedhart
 		 .SquashSCWfromLSU(SquashSCWfromLSU),      
 		 .DataMisalignedMfromLSU(DataMisalignedMfromLSU),
 		 .ReadDataWFromLSU(ReadDataWFromLSU),
+		 .HPTWReadyfromLSU(HPTWReadyfromLSU),
 		 .DataStall(DataStall),
 		 .*);
 
@@ -235,7 +238,9 @@ module wallypipelinedhart
 	  .DataMisalignedM(DataMisalignedMfromLSU),
 	  .DisableTranslation(DisableTranslation),
 
-	  .DataStall(DataStall), .* ); // data cache unit
+	  .DataStall(DataStall),
+	  .HPTWReady(HPTWReadyfromLSU), 
+	  .* ); // data cache unit
 
   ahblite ebu( 
 	       //.InstrReadF(1'b0),