diff --git a/wally-pipelined/lint-wally b/wally-pipelined/lint-wally
index f90a1010..9d5a20ba 100755
--- a/wally-pipelined/lint-wally
+++ b/wally-pipelined/lint-wally
@@ -1,7 +1,10 @@
 # check for warnings in Verilog code
 # The verilator lint tool is faster and better than Modelsim so it is best to run this first.
 
+echo "rv64ic linting..."
 verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv 
+echo "rv32ic linting..."
+verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv32ic src/*/*.sv 
 #verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv src/*/div/*.sv
 
 # --lint-only just runs lint rather than trying to compile and simulate