From 55df8bc3f7ceafab95e6c5d3e64ed3757969d9c7 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 31 Mar 2022 17:54:32 -0700 Subject: [PATCH] fix lingering overrun error bug --- pipelined/src/uncore/uartPC16550D.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 36ce77ee..267e38fd 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -308,7 +308,10 @@ module uartPC16550D( if (fifoenabled) begin if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1; if (rxfifohead == rxfifotail +1) rxdataready <= #1 0; - end else rxdataready <= #1 0; + end else begin + rxdataready <= #1 0; + RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) + end end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents rxfifohead <= #1 0; rxfifotail <= #1 0;