diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv
index 2e984223..a2e4ca89 100644
--- a/pipelined/src/lsu/busfsm.sv
+++ b/pipelined/src/lsu/busfsm.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 
-module busfsm #(parameter integer LOGWPL, parameter logic CACHE_ENABLED )
+module busfsm #(parameter integer LOGWPL)
   (input logic               clk,
    input logic               reset,
 
@@ -74,7 +74,7 @@ module busfsm #(parameter integer LOGWPL, parameter logic CACHE_ENABLED )
 
    assign WordCountFlag = 1; // Detect when we are waiting on the final access.
 
-  assign UnCachedAccess = ~CACHE_ENABLED | ~Cacheable;
+  assign UnCachedAccess = 1;
 
   always_ff @(posedge clk)
     if (reset)    BusCurrState <= #1 STATE_BUS_READY;
@@ -126,10 +126,5 @@ module busfsm #(parameter integer LOGWPL, parameter logic CACHE_ENABLED )
 
   assign CacheBusAck = 0;
   assign BusCommitted = BusCurrState != STATE_BUS_READY;
-  assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RW & UnCachedAccess)) |
-						  (BusCurrState == STATE_BUS_UNCACHED_READ |
-						   BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
-						   BusCurrState == STATE_BUS_UNCACHED_WRITE |
-						   BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) |
-						  ~CACHE_ENABLED; // if no Cache always select uncachedadr.
+  assign SelUncachedAdr = 1;
 endmodule
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 9e700dae..cd2601af 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -256,7 +256,7 @@ module lsu (
       flopen #(`XLEN) fb(.clk, .en(BufferCaptureEn), .d(HRDATA), .q(ReadDataWordMuxM));
       assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
 
-      busfsm #(LOGBWPL, `DCACHE) busfsm(
+      busfsm #(LOGBWPL) busfsm(
         .clk, .reset, .IgnoreRequest, .RW(LSURWM), 
         .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .Cacheable(1'b0), .BusStall, .BusWrite(LSUBusWrite), 
         .SelBusWord, .BusRead(LSUBusRead), .BufferCaptureEn,