From 5506efc115deceaa5f9da310655260be26983ea4 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Mon, 17 May 2021 17:02:13 -0500
Subject: [PATCH] Add 32/64-bit shifter for update to shifter block

---
 wally-pipelined/src/muldiv/div.sv | 45 +++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv
index 308a934a..72677122 100755
--- a/wally-pipelined/src/muldiv/div.sv
+++ b/wally-pipelined/src/muldiv/div.sv
@@ -1564,5 +1564,50 @@ module shifter_r32 (Z, A, Shift);
    
 endmodule // shifter_r32
 
+module shift_right #(parameter WIDTH=8) 
+   (input logic [`XLEN-1:0]         A,
+    input logic [$clog2(`XLEN)-1:0] Shift,
+    output logic [`XLEN-1:0] 	    Z);
+   
+   logic [`XLEN-1:0] 							 stage [$clog2(`XLEN):0];
+   genvar 								 i;
+   
+   assign stage[0] = A;   
+   generate
+      for (i=0;i<$clog2(`XLEN);i=i+1)
+	begin : genbit
+	   mux2 #(`XLEN) mux_inst (stage[i], 
+				   {{(`XLEN/(2**(i+1))){1'b0}}, stage[i][`XLEN-1:`XLEN/(2**(i+1))]}, 
+				   Shift[$clog2(`XLEN)-i-1], 
+				   stage[i+1]);
+	end
+   endgenerate
+   assign Z = stage[$clog2(`XLEN)];   
+
+endmodule // shift_right
+
+module shift_left #(parameter WIDTH=8) 
+   (input logic [`XLEN-1:0]         A,
+    input logic [$clog2(`XLEN)-1:0] Shift,
+    output logic [`XLEN-1:0] 	    Z);
+   
+   logic [`XLEN-1:0] 							stage [$clog2(`XLEN):0];
+   genvar 								i;
+   
+   assign stage[0] = A;   
+   generate
+      for (i=0;i<$clog2(`XLEN);i=i+1)
+	begin : genbit
+	   mux2 #(`XLEN) mux_inst (stage[i], 
+				   {stage[i][`XLEN-1-`XLEN/(2**(i+1)):0], {(`XLEN/(2**(i+1))){1'b0}}}, 
+				   Shift[$clog2(`XLEN)-i-1], 
+				   stage[i+1]);
+	end
+   endgenerate
+   assign Z = stage[$clog2(`XLEN)];   
+
+endmodule // shift_right
+
 /* verilator lint_on COMBDLY */
 /* verilator lint_on IMPLICIT */
+