diff --git a/pipelined/src/generic/mem/SRAM2P1R1W.sv b/pipelined/src/generic/mem/SRAM2P1R1W.sv deleted file mode 100644 index 513b7a36..00000000 --- a/pipelined/src/generic/mem/SRAM2P1R1W.sv +++ /dev/null @@ -1,109 +0,0 @@ -/////////////////////////////////////////// -// SRAM2P1R1W -// -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 14, 2021 -// Modified: -// -// Purpose: Behavioral model of two port SRAM. While this is synthesizable it will produce a flip flop based memory whi -// behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm. -// -// -// to preload this memory we can use the following command -// in modelsim's do file. -// mem load -infile -format -// example -// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module SRAM2P1R1W - #(parameter int DEPTH = 10, - parameter int WIDTH = 2 - ) - - (input logic clk, - // *** have to remove reset eventually - input logic reset, - - // port 1 is read only - input logic [DEPTH-1:0] RA1, - output logic [WIDTH-1:0] RD1, - input logic REN1, - - // port 2 is write only - input logic [DEPTH-1:0] WA1, - input logic [WIDTH-1:0] WD1, - input logic WEN1, - input logic [WIDTH-1:0] BitWEN1 - ); - - - logic [DEPTH-1:0] RA1Q, WA1Q; - logic WEN1Q; - logic [WIDTH-1:0] WD1Q; - - logic [WIDTH-1:0] mem[2**DEPTH-1:0]; - logic [WIDTH-1:0] bwe; - - - // SRAMs address busses are always registered first. - - flopenr #(DEPTH) RA1Reg(.clk(clk), - .reset(reset), - .en(REN1), - .d(RA1), - .q(RA1Q)); - - - flopenr #(DEPTH) WA1Reg(.clk(clk), - .reset(reset), - .en(REN1), - .d(WA1), - .q(WA1Q)); - - flopenr #(1) WEN1Reg(.clk(clk), - .reset(reset), - .en(1'b1), - .d(WEN1), - .q(WEN1Q)); - - flopenr #(WIDTH) WD1Reg(.clk(clk), - .reset(reset), - .en(REN1), - .d(WD1), - .q(WD1Q)); - // read port - assign RD1 = mem[RA1Q]; - - // write port - assign bwe = {WIDTH{WEN1Q}} & BitWEN1; - always_ff @(posedge clk) - mem[WA1Q] <= WD1Q & bwe | mem[WA1Q] & ~bwe; - -endmodule - - diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index bcd04b8b..a07efcdf 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// SRAM2P1R1W +// sram2p1r1w // // Written: Ross Thomposn // Email: ross1728@gmail.com @@ -103,7 +103,7 @@ module BTBPredictor // *** need to add forwarding. // *** optimize for byte write enables - SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk), + sram2p1r1w #(Depth, `XLEN+5) memory(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1({{InstrClass, TargetPC}}), diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index dd940140..f40eb172 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -113,7 +113,7 @@ module globalHistoryPredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - SRAM2P1R1W #(k, 2) PHT(.clk(clk), + sram2p1r1w #(k, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[k-1:0]), .RA1(GHRLookup), diff --git a/pipelined/src/ifu/gsharePredictor.sv b/pipelined/src/ifu/gsharePredictor.sv index f175361d..7a2b5627 100644 --- a/pipelined/src/ifu/gsharePredictor.sv +++ b/pipelined/src/ifu/gsharePredictor.sv @@ -110,7 +110,7 @@ module gsharePredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - SRAM2P1R1W #(`BPRED_SIZE, 2) PHT(.clk(clk), + sram2p1r1w #(`BPRED_SIZE, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[`BPRED_SIZE-1:0]), .RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 75798586..5826496a 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -60,7 +60,7 @@ module localHistoryPredictor assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]}; // INCASE we do ahead pipelining - // SRAM2P1R1W #(m,k) LHR(.clk(clk)), + // sram2p1r1w #(m,k) LHR(.clk(clk)), // .reset(reset), // .RA1(LookUpPCIndex), // need hashing function to get correct PC address // .RD1(LHRF), @@ -84,7 +84,7 @@ module localHistoryPredictor // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT // LHR referes to the address that the past k branches points to in the prediction stage // LHRE refers to the address that the past k branches points to in the exectution stage - SRAM2P1R1W #(k, 2) PHT(.clk(clk), + sram2p1r1w #(k, 2) PHT(.clk(clk), .reset(reset), .RA1(ForwardLHRNext), .RD1(PredictionMemory), diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index 295f5e5e..59827526 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -60,7 +60,7 @@ module twoBitPredictor assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]}; - SRAM2P1R1W #(Depth, 2) PHT(.clk(clk), + sram2p1r1w #(Depth, 2) PHT(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1(PredictionMemory),