From 54bd1fb806749ec19566c657148e7c7e629f082d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 22 Oct 2022 16:29:51 -0500 Subject: [PATCH] Small cleanup of interlockfsm. --- pipelined/src/lsu/interlockfsm.sv | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 73b22a7a..d73d1b5c 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -68,13 +68,12 @@ module interlockfsm( always_comb begin case(InterlockCurrState) - STATE_T0_READY: if(EitherTLBMiss & ~TrapM) InterlockNextState = STATE_T3_TLB_MISS; - else InterlockNextState = STATE_T0_READY; - STATE_T3_TLB_MISS: if(~(EitherTLBWrite)) InterlockNextState = STATE_T3_TLB_MISS; - else if(PendingTLBMiss) InterlockNextState = STATE_T3_TLB_MISS; - else if(AnyCPUReqM) InterlockNextState = STATE_T0_READY; - else InterlockNextState = STATE_T0_READY; - default: InterlockNextState = STATE_T0_READY; + STATE_T0_READY: if(EitherTLBMiss & ~TrapM) InterlockNextState = STATE_T3_TLB_MISS; + else InterlockNextState = STATE_T0_READY; + STATE_T3_TLB_MISS: if(PendingTLBMiss | ~(EitherTLBWrite)) InterlockNextState = STATE_T3_TLB_MISS; + else if(AnyCPUReqM) InterlockNextState = STATE_T0_READY; + else InterlockNextState = STATE_T0_READY; + default: InterlockNextState = STATE_T0_READY; endcase end // always_comb