From 54b6a2dcad58a2d4cf50e785fb3bda90cdc42947 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 17 Jun 2021 18:54:39 -0400
Subject: [PATCH] added inputs to pmaadrdec

---
 wally-pipelined/src/mmu/pmaadrdec.sv  |  7 +++++--
 wally-pipelined/src/mmu/pmachecker.sv | 18 +++++++++---------
 2 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/wally-pipelined/src/mmu/pmaadrdec.sv b/wally-pipelined/src/mmu/pmaadrdec.sv
index ea7688a2..bc217876 100644
--- a/wally-pipelined/src/mmu/pmaadrdec.sv
+++ b/wally-pipelined/src/mmu/pmaadrdec.sv
@@ -29,6 +29,9 @@ module pmaadrdec (
   input  logic [31:0] HADDR,
   input  logic [31:0] Base, Range,
   input  logic        Supported,
+  input  logic        AccessValid,
+  input  logic [2:0]  Size,
+  input  logic [3:0]  SizeMask,
   output logic        HSEL
 );
 
@@ -38,8 +41,8 @@ module pmaadrdec (
   // for example, if Base = 0x04002000 and range = 0x00000FFF,
   // then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1)
 
-  assign match = (HADDR ~^ Base) | Range;
-  assign HSEL = &match & Supported;
+  assign match = &((HADDR ~^ Base) | Range);
+  assign HSEL = match & Supported;
 
 endmodule
 
diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv
index f188bb27..95a82179 100644
--- a/wally-pipelined/src/mmu/pmachecker.sv
+++ b/wally-pipelined/src/mmu/pmachecker.sv
@@ -64,20 +64,20 @@ module pmachecker (
 
 
   // Determine which region of physical memory (if any) is being accessed
-  pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, BootTim);
-  pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, Tim);
-  pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, CLINT);
-  pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, GPIO);
-  pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, UART);
-  pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, PLIC);
+  pmaadrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, `BOOTTIMSUPPORTED, AccessRX, Size, 4'b1111, BootTim);
+  pmaadrdec timdec(HADDR, `TIMBASE, `TIMRANGE, `TIMSUPPORTED, AccessRWX, Size, 4'b1111, Tim);
+  pmaadrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, `CLINTSUPPORTED, AccessRW, Size, (`XLEN==64 ? 4'b1000 : 4'b0100), CLINT);
+  pmaadrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, `GPIOSUPPORTED, AccessRW, Size, 4'b0100, GPIO);
+  pmaadrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, `UARTSUPPORTED, AccessRW, Size, 4'b0001, UART);
+  pmaadrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, `PLICSUPPORTED, AccessRW, Size, 4'b0100, PLIC);
 
   // Swizzle region bits
   assign Regions = {BootTim, Tim, CLINT, GPIO, UART, PLIC};
 
   // Only RAM memory regions are cacheable
   assign Cacheable = BootTim | Tim;
-  assign Idempotent = BootTim | Tim;
-  assign AtomicAllowed = BootTim | Tim;
+  assign Idempotent = Tim;
+  assign AtomicAllowed = Tim;
 
   assign ValidBootTim = '1;
   assign ValidTim = '1;
@@ -98,9 +98,9 @@ module pmachecker (
 
   assign PMAAccessFault = ~|HSELRegions;
 
+  // Detect access faults
   assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
   assign PMALoadAccessFaultM  = ReadAccessM    && PMAAccessFault;
   assign PMAStoreAccessFaultM = WriteAccessM   && PMAAccessFault;
-
   assign PMASquashBusAccess = PMAAccessFault && AccessRWX;
 endmodule